diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2011-09-13 12:58:09 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2011-09-13 12:58:09 -0400 |
| commit | 28a2236ec18e3d5a82d6f7caffbf8285aec48b38 (patch) | |
| tree | bfd2d8d78733f95b30e9f671229ce2f0f55f4d94 /tests/long | |
| parent | 649c239ceef2d107fae253b1008c6f214f242d73 (diff) | |
| download | gem5-28a2236ec18e3d5a82d6f7caffbf8285aec48b38.tar.xz | |
O3: Update stats for new ordering fix.
Diffstat (limited to 'tests/long')
73 files changed, 11038 insertions, 11067 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index cdf647d08..b11fadb7f 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/alpha/tru64/gzip +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index 81484db61..9acd0ed7e 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timin gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 14:47:20 -gem5 started Aug 17 2011 14:50:17 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 16:10:02 +gem5 started Aug 20 2011 16:10:09 +gem5 executing on zizzer command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -41,4 +41,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 145301847500 because target called exit() +Exiting @ tick 144450185500 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 5c2b0fbb8..bcb696265 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.145302 # Number of seconds simulated -sim_ticks 145301847500 # Number of ticks simulated +sim_seconds 0.144450 # Number of seconds simulated +sim_ticks 144450185500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 168398 # Simulator instruction rate (inst/s) -host_tick_rate 43264868 # Simulator tick rate (ticks/s) -host_mem_usage 252140 # Number of bytes of host memory used -host_seconds 3358.43 # Real time elapsed on the host +host_inst_rate 180758 # Simulator instruction rate (inst/s) +host_tick_rate 46168195 # Simulator tick rate (ticks/s) +host_mem_usage 205240 # Number of bytes of host memory used +host_seconds 3128.78 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 125931819 # DTB read hits -system.cpu.dtb.read_misses 26714 # DTB read misses +system.cpu.dtb.read_hits 125584378 # DTB read hits +system.cpu.dtb.read_misses 26780 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 125958533 # DTB read accesses -system.cpu.dtb.write_hits 41424543 # DTB write hits -system.cpu.dtb.write_misses 32276 # DTB write misses +system.cpu.dtb.read_accesses 125611158 # DTB read accesses +system.cpu.dtb.write_hits 41433696 # DTB write hits +system.cpu.dtb.write_misses 32002 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 41456819 # DTB write accesses -system.cpu.dtb.data_hits 167356362 # DTB hits -system.cpu.dtb.data_misses 58990 # DTB misses +system.cpu.dtb.write_accesses 41465698 # DTB write accesses +system.cpu.dtb.data_hits 167018074 # DTB hits +system.cpu.dtb.data_misses 58782 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 167415352 # DTB accesses -system.cpu.itb.fetch_hits 71387266 # ITB hits +system.cpu.dtb.data_accesses 167076856 # DTB accesses +system.cpu.itb.fetch_hits 70952399 # ITB hits system.cpu.itb.fetch_misses 40 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 71387306 # ITB accesses +system.cpu.itb.fetch_accesses 70952439 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,246 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 290603696 # number of cpu cycles simulated +system.cpu.numCycles 288900372 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 81919814 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 75390266 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 4129357 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 77614173 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 69618230 # Number of BTB hits +system.cpu.BPredUnit.lookups 81329377 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 74804974 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 4133006 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 77032590 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 69317648 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1955958 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 217 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 74192269 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 739424750 # Number of instructions fetch has processed -system.cpu.fetch.Branches 81919814 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 71574188 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 139080989 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 17172234 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 64410456 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1953991 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 213 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 73654881 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 736311086 # Number of instructions fetch has processed +system.cpu.fetch.Branches 81329377 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 71271639 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 138478958 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 16551941 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 64286783 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 957 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 71387266 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1210642 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 290534603 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.545049 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.198246 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 70952399 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1183706 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 288831482 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.549276 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.199825 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 151453614 52.13% 52.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 11687885 4.02% 56.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15898742 5.47% 61.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 15854935 5.46% 67.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 13240035 4.56% 71.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15603650 5.37% 77.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6697784 2.31% 79.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3574182 1.23% 80.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 56523776 19.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 150352524 52.06% 52.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 11670569 4.04% 56.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15804098 5.47% 61.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 15798949 5.47% 67.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 13114109 4.54% 71.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15608541 5.40% 76.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6620136 2.29% 79.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3484931 1.21% 80.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 56377625 19.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 290534603 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.281895 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.544444 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 90310656 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 50731551 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 126219695 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10423604 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 12849097 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4446391 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 868 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 727740839 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3152 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 12849097 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 98621596 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12675857 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 639 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 123066068 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 43321346 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 713725381 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 266 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 34127954 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3740820 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 543893835 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 937350842 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 937348775 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2067 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 288831482 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.281514 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.548668 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 89767727 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 50572891 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 125759213 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10322601 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 12409050 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4445174 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 884 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 724769065 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3300 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 12409050 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 98007088 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12678191 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 619 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 122576240 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 43160294 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 711155131 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 265 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 33840558 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3866582 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 542435988 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 934956599 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 934954553 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2046 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 80038946 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 38 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 39 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 85210895 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 131427932 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 43788464 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14719547 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6869694 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 643138163 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 78581099 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 84659517 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 130961315 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 43800509 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14632120 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10811841 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 641773186 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 621184561 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 428348 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 76303449 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41228761 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 620620587 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 312645 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 75146534 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 39896926 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 290534603 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.138074 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.876724 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 288831482 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.148729 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.863512 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 70371393 24.22% 24.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 59001774 20.31% 44.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 56407615 19.42% 63.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 31734464 10.92% 74.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 32252552 11.10% 85.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 24569230 8.46% 94.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 11680867 4.02% 98.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3911059 1.35% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 605649 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 69246295 23.97% 23.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 56834943 19.68% 43.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 56336980 19.51% 63.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34937865 12.10% 75.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31450731 10.89% 86.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 24967668 8.64% 94.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10438059 3.61% 98.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3923057 1.36% 99.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 695884 0.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 290534603 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 288831482 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4149748 79.41% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 46 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 79.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 644138 12.33% 91.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 431804 8.26% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3711133 78.36% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 47 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 78.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 592679 12.51% 90.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 432117 9.12% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 450716451 72.56% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7786 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 128329931 20.66% 93.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 42130345 6.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 450541493 72.60% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7929 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 127924018 20.61% 93.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 42147099 6.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 621184561 # Type of FU issued -system.cpu.iq.rate 2.137566 # Inst issue rate -system.cpu.iq.fu_busy_cnt 5225736 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008413 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1538554428 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 719791910 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 609163875 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3381 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1868 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1606 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 626408589 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1708 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11777609 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 620620587 # Type of FU issued +system.cpu.iq.rate 2.148217 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4735976 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007631 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1535117897 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 716922572 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 608986825 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3380 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1870 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1597 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 625354857 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1706 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11780563 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 16913890 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 148570 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 370604 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4337143 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 16447273 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 150139 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 4778 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4349188 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 5917 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 50743 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 5903 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 50771 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 12849097 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1534890 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 101054 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 688747962 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2386448 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 131427932 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 43788464 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 12409050 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1537752 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 101062 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 686807741 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2379158 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 130961315 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 43800509 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 40995 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13802 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 370604 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4041048 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 603771 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4644819 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 613556554 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 125958678 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7628007 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 40948 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13806 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 4778 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4044271 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 603642 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4647913 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 613128186 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 125611295 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7492401 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 45609769 # number of nop insts executed -system.cpu.iew.exec_refs 167435052 # number of memory reference insts executed -system.cpu.iew.exec_branches 68567792 # Number of branches executed -system.cpu.iew.exec_stores 41476374 # Number of stores executed -system.cpu.iew.exec_rate 2.111317 # Inst execution rate -system.cpu.iew.wb_sent 610651273 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 609165481 # cumulative count of insts written-back -system.cpu.iew.wb_producers 420066604 # num instructions producing a value -system.cpu.iew.wb_consumers 531633628 # num instructions consuming a value +system.cpu.iew.exec_nop 45034525 # number of nop insts executed +system.cpu.iew.exec_refs 167096489 # number of memory reference insts executed +system.cpu.iew.exec_branches 68658345 # Number of branches executed +system.cpu.iew.exec_stores 41485194 # Number of stores executed +system.cpu.iew.exec_rate 2.122282 # Inst execution rate +system.cpu.iew.wb_sent 610318268 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 608988422 # cumulative count of insts written-back +system.cpu.iew.wb_producers 420036286 # num instructions producing a value +system.cpu.iew.wb_consumers 531421352 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.096207 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.790143 # average fanout of values written-back +system.cpu.iew.wb_rate 2.107953 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.790402 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 86736991 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 84796787 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4128553 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 277685506 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.167405 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.598933 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 4132184 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 276422432 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.177309 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.603924 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 91049633 32.79% 32.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 76164348 27.43% 60.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 31609265 11.38% 71.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9610599 3.46% 75.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10212120 3.68% 78.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 21618987 7.79% 86.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6091791 2.19% 88.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2481977 0.89% 89.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 28846786 10.39% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 90291943 32.66% 32.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 75645741 27.37% 60.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 32420379 11.73% 71.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8741969 3.16% 74.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10320203 3.73% 78.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 19633028 7.10% 85.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6964693 2.52% 88.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5325361 1.93% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 27079115 9.80% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 277685506 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 276422432 # Number of insts commited each cycle system.cpu.commit.count 601856963 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 153965363 # Number of memory references committed @@ -290,50 +290,50 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 28846786 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 27079115 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 937368285 # The number of ROB reads -system.cpu.rob.rob_writes 1390043178 # The number of ROB writes -system.cpu.timesIdled 2213 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 69093 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 935932678 # The number of ROB reads +system.cpu.rob.rob_writes 1385724156 # The number of ROB writes +system.cpu.timesIdled 2221 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 68890 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.513840 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.513840 # CPI: Total CPI of All Threads -system.cpu.ipc 1.946130 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.946130 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 864034550 # number of integer regfile reads -system.cpu.int_regfile_writes 501250515 # number of integer regfile writes -system.cpu.fp_regfile_reads 281 # number of floating regfile reads +system.cpu.cpi 0.510829 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.510829 # CPI: Total CPI of All Threads +system.cpu.ipc 1.957604 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.957604 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 863490102 # number of integer regfile reads +system.cpu.int_regfile_writes 500818441 # number of integer regfile writes +system.cpu.fp_regfile_reads 272 # number of floating regfile reads system.cpu.fp_regfile_writes 54 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 34 # number of replacements -system.cpu.icache.tagsinuse 800.952347 # Cycle average of tags in use -system.cpu.icache.total_refs 71385990 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 943 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 75700.943796 # Average number of references to valid blocks. +system.cpu.icache.replacements 36 # number of replacements +system.cpu.icache.tagsinuse 801.236568 # Cycle average of tags in use +system.cpu.icache.total_refs 70951127 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 944 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 75160.092161 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 800.952347 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.391090 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 71385990 # number of ReadReq hits -system.cpu.icache.demand_hits 71385990 # number of demand (read+write) hits -system.cpu.icache.overall_hits 71385990 # number of overall hits -system.cpu.icache.ReadReq_misses 1276 # number of ReadReq misses -system.cpu.icache.demand_misses 1276 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1276 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 46038500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 46038500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 46038500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 71387266 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 71387266 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 71387266 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 801.236568 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.391229 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 70951127 # number of ReadReq hits +system.cpu.icache.demand_hits 70951127 # number of demand (read+write) hits +system.cpu.icache.overall_hits 70951127 # number of overall hits +system.cpu.icache.ReadReq_misses 1272 # number of ReadReq misses +system.cpu.icache.demand_misses 1272 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1272 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 45919500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 45919500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 45919500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 70952399 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 70952399 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 70952399 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36080.329154 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36080.329154 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36080.329154 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 36100.235849 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36100.235849 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36100.235849 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -343,161 +343,161 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 333 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 333 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 333 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 943 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 943 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 943 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 328 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 328 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 328 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 944 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 944 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 944 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 33661000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 33661000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 33661000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 33676000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 33676000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 33676000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35695.652174 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35695.652174 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35695.652174 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35673.728814 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35673.728814 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35673.728814 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 470870 # number of replacements -system.cpu.dcache.tagsinuse 4093.952106 # Cycle average of tags in use -system.cpu.dcache.total_refs 151563529 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 474966 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 319.103955 # Average number of references to valid blocks. +system.cpu.dcache.replacements 470690 # number of replacements +system.cpu.dcache.tagsinuse 4093.940031 # Cycle average of tags in use +system.cpu.dcache.total_refs 151212527 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 474786 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 318.485648 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 126051000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4093.952106 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999500 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 113415940 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 38147585 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 151563525 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 151563525 # number of overall hits -system.cpu.dcache.ReadReq_misses 731363 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1303736 # number of WriteReq misses -system.cpu.dcache.demand_misses 2035099 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2035099 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 11802867000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 19634898764 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 31437765764 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 31437765764 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 114147303 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 4093.940031 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999497 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 113064898 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 38147626 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 151212524 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 151212524 # number of overall hits +system.cpu.dcache.ReadReq_misses 732041 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1303695 # number of WriteReq misses +system.cpu.dcache.demand_misses 2035736 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2035736 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 11783533000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 19632740219 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 31416273219 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 31416273219 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 113796939 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 153598624 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 153598624 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.006407 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.033047 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.013249 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.013249 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 16138.178989 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 15060.486758 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 15447.782031 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 15447.782031 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 886996 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 153248260 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 153248260 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.006433 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.033046 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.013284 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.013284 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 16096.821080 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 15059.304683 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 15432.390653 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 15432.390653 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 804496 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 236500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 116 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7646.517241 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6935.310345 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 423193 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 512453 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1047680 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1560133 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1560133 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 218910 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 256056 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 474966 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 474966 # number of overall MSHR misses +system.cpu.dcache.writebacks 423044 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 513277 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1047673 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1560950 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1560950 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 218764 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 256022 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 474786 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 474786 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1640097000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3028332494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4668429494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4668429494 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1640072500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3027658494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4667730994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4667730994 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001918 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001922 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.006490 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.003092 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.003092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7492.106345 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11826.836684 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9828.976167 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9828.976167 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.003098 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.003098 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7496.994478 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11825.774715 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9831.231321 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9831.231321 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 74473 # number of replacements -system.cpu.l2cache.tagsinuse 17668.898791 # Cycle average of tags in use -system.cpu.l2cache.total_refs 478122 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 90370 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.290716 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 74463 # number of replacements +system.cpu.l2cache.tagsinuse 17661.712037 # Cycle average of tags in use +system.cpu.l2cache.total_refs 478021 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 90363 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.290008 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1750.296576 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15918.602215 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.053415 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.485797 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 186900 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 423193 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 196240 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 383140 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 383140 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32953 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 59816 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 92769 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 92769 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1133504500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2066596000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3200100500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3200100500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 219853 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 423193 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 256056 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 475909 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 475909 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.149887 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.233605 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.194930 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.194930 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34397.611750 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34549.217601 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34495.364831 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34495.364831 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 453500 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::0 1743.919943 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15917.792095 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.053220 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.485772 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 186750 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 423044 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 196218 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 382968 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 382968 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32958 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 59804 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 92762 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 92762 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1133680000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2065878500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3199558500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3199558500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 219708 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 423044 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 256022 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 475730 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 475730 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.150008 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.233589 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.194989 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.194989 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34397.718308 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34544.152565 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34492.125008 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34492.125008 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 370500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 76 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5967.105263 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5145.833333 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59331 # number of writebacks +system.cpu.l2cache.writebacks 59330 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32953 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 59816 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 92769 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 92769 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 32958 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 59804 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 92762 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 92762 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1022169500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1878238500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2900408000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2900408000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1022345000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1877543500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2899888500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2899888500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.149887 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.233605 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.194930 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.194930 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.011926 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31400.269159 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31264.840626 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31264.840626 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150008 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.233589 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.194989 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.194989 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.631046 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31394.948498 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31261.599577 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31261.599577 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini index fea8ea4a1..e2efd077d 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/arm/linux/gzip +executable=/dist/m5/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout index a9117199d..ffc55a28a 100755 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing/si gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 19:27:45 -gem5 started Aug 17 2011 20:12:24 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 12:27:58 +gem5 started Aug 20 2011 12:28:18 +gem5 executing on zizzer command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -40,4 +40,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 181028108500 because target called exit() +Exiting @ tick 177134936000 because target called exit() diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt index 701011da6..be7b06491 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.181028 # Number of seconds simulated -sim_ticks 181028108500 # Number of ticks simulated +sim_seconds 0.177135 # Number of seconds simulated +sim_ticks 177134936000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110603 # Simulator instruction rate (inst/s) -host_tick_rate 33239774 # Simulator tick rate (ticks/s) -host_mem_usage 263548 # Number of bytes of host memory used -host_seconds 5446.13 # Real time elapsed on the host -sim_insts 602359805 # Number of instructions simulated +host_inst_rate 142557 # Simulator instruction rate (inst/s) +host_tick_rate 41921641 # Simulator tick rate (ticks/s) +host_mem_usage 216920 # Number of bytes of host memory used +host_seconds 4225.38 # Real time elapsed on the host +sim_insts 602359810 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,299 +51,299 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 362056218 # number of cpu cycles simulated +system.cpu.numCycles 354269873 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 93448154 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 85911629 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3923569 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 88397798 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 81789381 # Number of BTB hits +system.cpu.BPredUnit.lookups 91159436 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 84245505 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 4004866 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 86334569 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 80046410 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1790445 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1821 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 79878814 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 718366767 # Number of instructions fetch has processed -system.cpu.fetch.Branches 93448154 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83579826 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 162526152 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20714981 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 102669649 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 673 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 77174070 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1530906 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 361172763 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.127936 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.978152 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1704802 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1819 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 76808344 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 703901675 # Number of instructions fetch has processed +system.cpu.fetch.Branches 91159436 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 81751212 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 159188980 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 18469359 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 103024732 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 658 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 74435954 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1343690 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 353410599 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.128136 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.980644 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 198646777 55.00% 55.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25571456 7.08% 62.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 19827264 5.49% 67.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 25093348 6.95% 74.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 12488036 3.46% 77.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13650153 3.78% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4767489 1.32% 83.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7787203 2.16% 85.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 53341037 14.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 194221784 54.96% 54.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25626631 7.25% 62.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 19263980 5.45% 67.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 24389254 6.90% 74.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11789340 3.34% 77.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13441910 3.80% 81.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4603453 1.30% 83.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7798173 2.21% 85.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52276074 14.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 361172763 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258104 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.984130 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 102343616 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 83020024 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 140521738 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 19192459 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16094926 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6886310 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 2563 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 756045465 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 7091 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 16094926 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 115645953 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9675212 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 105916 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 146342748 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 73308008 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 741744489 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 294 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59347402 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10155907 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 308 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 765934734 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3449682594 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3449682466 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 353410599 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.257316 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.986908 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 98916904 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 83485006 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 137131028 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 19492362 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14385299 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6301332 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 2598 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 740264204 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 7138 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14385299 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 111881934 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9577242 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 106466 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 143552765 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 73906893 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 727334722 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 296 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59781135 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10308783 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 341 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 753003460 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3381092272 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3381092144 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627417394 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 138517335 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6417 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6420 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 130475053 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 183427028 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 85118109 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 19617047 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 24959505 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 714042486 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7344 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 668482439 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 813187 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 110903932 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 272103092 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1046 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 361172763 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.850866 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.720469 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627417402 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 125586053 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6434 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6436 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 132024310 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 179771780 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 82868403 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 19149565 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 24496609 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 702530034 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7346 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 663102893 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 740706 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 99626728 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 237214631 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1047 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 353410599 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.876296 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.734600 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 89609578 24.81% 24.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 92103808 25.50% 50.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 76957239 21.31% 71.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 43677932 12.09% 83.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 26190048 7.25% 90.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 17902760 4.96% 95.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7158113 1.98% 97.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6378593 1.77% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1194692 0.33% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 85472706 24.19% 24.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 90623075 25.64% 49.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 75986397 21.50% 71.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 42524156 12.03% 83.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 25503318 7.22% 90.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 18123112 5.13% 95.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7244001 2.05% 97.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6628954 1.88% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1304880 0.37% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 361172763 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 353410599 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 174743 4.36% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2924154 73.03% 77.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 905037 22.60% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 202122 4.87% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2984901 71.87% 76.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 966402 23.27% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 414572332 62.02% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6557 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 174888345 26.16% 88.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79015202 11.82% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 412611240 62.22% 62.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6564 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 172508534 26.02% 88.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 77976552 11.76% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 668482439 # Type of FU issued -system.cpu.iq.rate 1.846350 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4003934 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005990 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1702954726 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 825626408 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 654174988 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 663102893 # Type of FU issued +system.cpu.iq.rate 1.871745 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4153425 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006264 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1684510480 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 802175669 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 650244511 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 672486353 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 667256298 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 28890587 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 29664426 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 34474432 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 123741 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 677004 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 14897095 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 30819183 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 223952 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11801 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12647388 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 16171 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12604 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 13674 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12619 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16094926 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 778321 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 50892 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 714119394 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2033981 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 183427028 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 85118109 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6015 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 12993 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5224 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 677004 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4081658 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 498372 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4580030 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 660769173 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 171345747 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7713266 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 14385299 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 811787 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 58163 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 702606824 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1856146 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 179771780 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 82868403 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6016 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13064 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5095 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11801 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4163103 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 495424 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4658527 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 656117429 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 169139334 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6985464 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 69564 # number of nop insts executed -system.cpu.iew.exec_refs 248875630 # number of memory reference insts executed -system.cpu.iew.exec_branches 76892303 # Number of branches executed -system.cpu.iew.exec_stores 77529883 # Number of stores executed -system.cpu.iew.exec_rate 1.825046 # Inst execution rate -system.cpu.iew.wb_sent 656292597 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 654175004 # cumulative count of insts written-back -system.cpu.iew.wb_producers 424501609 # num instructions producing a value -system.cpu.iew.wb_consumers 659455960 # num instructions consuming a value +system.cpu.iew.exec_nop 69444 # number of nop insts executed +system.cpu.iew.exec_refs 245837823 # number of memory reference insts executed +system.cpu.iew.exec_branches 76466943 # Number of branches executed +system.cpu.iew.exec_stores 76698489 # Number of stores executed +system.cpu.iew.exec_rate 1.852027 # Inst execution rate +system.cpu.iew.wb_sent 652257551 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 650244527 # cumulative count of insts written-back +system.cpu.iew.wb_producers 423314128 # num instructions producing a value +system.cpu.iew.wb_consumers 657393243 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.806833 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.643715 # average fanout of values written-back +system.cpu.iew.wb_rate 1.835450 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.643928 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 602359856 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 111769419 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 6298 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3982936 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 345077838 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.745577 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.124891 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 602359861 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 100255909 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 6299 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 4064207 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 339025301 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.776740 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.152545 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 111837000 32.41% 32.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 108539519 31.45% 63.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 49573446 14.37% 78.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 10197254 2.96% 81.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 23493632 6.81% 87.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14599312 4.23% 92.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8154465 2.36% 94.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1281875 0.37% 94.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 17401335 5.04% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 108189269 31.91% 31.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 106528342 31.42% 63.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 49314404 14.55% 77.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9858111 2.91% 80.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 23334525 6.88% 87.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14310366 4.22% 91.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7925881 2.34% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1332062 0.39% 94.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 18232341 5.38% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 345077838 # Number of insts commited each cycle -system.cpu.commit.count 602359856 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 339025301 # Number of insts commited each cycle +system.cpu.commit.count 602359861 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219173609 # Number of memory references committed -system.cpu.commit.loads 148952595 # Number of loads committed +system.cpu.commit.refs 219173611 # Number of memory references committed +system.cpu.commit.loads 148952596 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70828602 # Number of branches committed +system.cpu.commit.branches 70828603 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533522643 # Number of committed integer instructions. +system.cpu.commit.int_insts 533522647 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 17401335 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 18232341 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1041805166 # The number of ROB reads -system.cpu.rob.rob_writes 1444392656 # The number of ROB writes -system.cpu.timesIdled 37065 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 883455 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 602359805 # Number of Instructions Simulated -system.cpu.committedInsts_total 602359805 # Number of Instructions Simulated -system.cpu.cpi 0.601063 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.601063 # CPI: Total CPI of All Threads -system.cpu.ipc 1.663719 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.663719 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3299876653 # number of integer regfile reads -system.cpu.int_regfile_writes 679084326 # number of integer regfile writes +system.cpu.rob.rob_reads 1023408118 # The number of ROB reads +system.cpu.rob.rob_writes 1419658807 # The number of ROB writes +system.cpu.timesIdled 37049 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 859274 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 602359810 # Number of Instructions Simulated +system.cpu.committedInsts_total 602359810 # Number of Instructions Simulated +system.cpu.cpi 0.588137 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.588137 # CPI: Total CPI of All Threads +system.cpu.ipc 1.700285 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.700285 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3276148182 # number of integer regfile reads +system.cpu.int_regfile_writes 676030301 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 960654614 # number of misc regfile reads -system.cpu.misc_regfile_writes 2658 # number of misc regfile writes -system.cpu.icache.replacements 39 # number of replacements -system.cpu.icache.tagsinuse 659.213464 # Cycle average of tags in use -system.cpu.icache.total_refs 77173072 # Total number of references to valid blocks. +system.cpu.misc_regfile_reads 943785902 # number of misc regfile reads +system.cpu.misc_regfile_writes 2660 # number of misc regfile writes +system.cpu.icache.replacements 38 # number of replacements +system.cpu.icache.tagsinuse 657.730766 # Cycle average of tags in use +system.cpu.icache.total_refs 74434959 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 761 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 101410.081472 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 97812.035480 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 659.213464 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.321882 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 77173072 # number of ReadReq hits -system.cpu.icache.demand_hits 77173072 # number of demand (read+write) hits -system.cpu.icache.overall_hits 77173072 # number of overall hits -system.cpu.icache.ReadReq_misses 998 # number of ReadReq misses -system.cpu.icache.demand_misses 998 # number of demand (read+write) misses -system.cpu.icache.overall_misses 998 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 34962500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 34962500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 34962500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 77174070 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 77174070 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 77174070 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 657.730766 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.321158 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 74434959 # number of ReadReq hits +system.cpu.icache.demand_hits 74434959 # number of demand (read+write) hits +system.cpu.icache.overall_hits 74434959 # number of overall hits +system.cpu.icache.ReadReq_misses 995 # number of ReadReq misses +system.cpu.icache.demand_misses 995 # number of demand (read+write) misses +system.cpu.icache.overall_misses 995 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 34724500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 34724500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 34724500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 74435954 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 74435954 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 74435954 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35032.565130 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35032.565130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35032.565130 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 34898.994975 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34898.994975 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34898.994975 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,67 +353,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 236 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 236 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 236 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 762 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 762 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 762 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 234 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 234 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 234 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 761 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 761 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 761 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 26035000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 26035000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 26035000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 25975000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 25975000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 25975000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34166.666667 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34166.666667 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34166.666667 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34132.720105 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34132.720105 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34132.720105 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 441073 # number of replacements -system.cpu.dcache.tagsinuse 4094.780664 # Cycle average of tags in use -system.cpu.dcache.total_refs 208769486 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 445169 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 468.966810 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 87843000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.780664 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999702 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 140903051 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 67863771 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 1333 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 1328 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 208766822 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 208766822 # number of overall hits -system.cpu.dcache.ReadReq_misses 249137 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1553760 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 9 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1802897 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1802897 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3284237500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 27026235527 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 199500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 30310473027 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 30310473027 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 141152188 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 441231 # number of replacements +system.cpu.dcache.tagsinuse 4094.754255 # Cycle average of tags in use +system.cpu.dcache.total_refs 205797010 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 445327 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 462.125607 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 87838000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.754255 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999696 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 137942409 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 67851936 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 1336 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 1329 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 205794345 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 205794345 # number of overall hits +system.cpu.dcache.ReadReq_misses 249307 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1565595 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 8 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 1814902 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1814902 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3284045500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 27041000027 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 163000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 30325045527 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 30325045527 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 138191716 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 1342 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 1328 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 210569719 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 210569719 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.001765 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.022383 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.006706 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.008562 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.008562 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 13182.455838 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 17394.086298 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 22166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 16812.093551 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 16812.093551 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses 1344 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 1329 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 207609247 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 207609247 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.001804 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.022553 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.005952 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.008742 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.008742 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 13172.696715 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 17272.027585 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 20375 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 16708.916254 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 16708.916254 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked @@ -422,72 +422,70 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.824714 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 395116 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 51340 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1306387 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 9 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1357727 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1357727 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 197797 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 247373 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 445170 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 445170 # number of overall MSHR misses +system.cpu.dcache.writebacks 395260 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 51378 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1318197 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 8 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1369575 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1369575 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 197929 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 247398 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 445327 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 445327 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1624472000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2544428527 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4168900527 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4168900527 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1625138000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2544850527 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4169988527 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4169988527 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001401 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001432 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.003564 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.002114 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.002114 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8212.824259 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10285.797266 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9364.738251 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9364.738251 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.002145 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.002145 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8210.711922 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10286.463621 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9363.879861 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9363.879861 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 72968 # number of replacements -system.cpu.l2cache.tagsinuse 17823.256167 # Cycle average of tags in use -system.cpu.l2cache.total_refs 421257 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 88492 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.760396 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 72978 # number of replacements +system.cpu.l2cache.tagsinuse 17806.299437 # Cycle average of tags in use +system.cpu.l2cache.total_refs 422221 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 88511 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.770266 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1903.843188 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15919.412978 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058101 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.485822 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 165755 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 395116 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 189016 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 354771 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 354771 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32799 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 58360 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 91159 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 91159 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1126738500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2004231000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3130969500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3130969500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 198554 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 395116 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 247376 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 445930 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 445930 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.165189 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.235916 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.204424 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.204424 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34352.830879 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34342.546265 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34346.246668 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34346.246668 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 1880.880475 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15925.418963 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.057400 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.486005 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 165873 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 395260 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 189038 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 354911 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 354911 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32814 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 58363 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 91177 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 91177 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1126440500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2003739500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3130180000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3130180000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 198687 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 395260 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 247401 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 446088 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 446088 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.165154 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.235904 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.204392 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.204392 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34328.045956 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34332.359543 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34330.807111 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34330.807111 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked @@ -496,28 +494,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58122 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 9 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 9 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32790 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58360 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 91150 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 91150 # number of overall MSHR misses +system.cpu.l2cache.writebacks 58123 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 8 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 8 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 32806 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58363 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 91169 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 91169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1020255000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822537500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2842792500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2842792500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1019567500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822366000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2841933500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2841933500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165144 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235916 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.204404 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.204404 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31114.821592 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31229.223783 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31188.069117 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31188.069117 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165114 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235904 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.204374 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.204374 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31078.689874 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31224.680020 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31172.147331 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31172.147331 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 69d6d5791..80ace0dc5 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/sparc/linux/gzip +executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index f40ea4f95..cea2acb5a 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timin gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 16:58:37 -gem5 started Aug 17 2011 16:59:36 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 13:07:22 +gem5 started Aug 20 2011 13:07:33 +gem5 executing on zizzer command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -40,4 +40,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 424846003000 because target called exit() +Exiting @ tick 408816360000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 386994981..58e0bfc8f 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,148 +1,148 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.424846 # Number of seconds simulated -sim_ticks 424846003000 # Number of ticks simulated +sim_seconds 0.408816 # Number of seconds simulated +sim_ticks 408816360000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 130905 # Simulator instruction rate (inst/s) -host_tick_rate 39566335 # Simulator tick rate (ticks/s) -host_mem_usage 260032 # Number of bytes of host memory used -host_seconds 10737.56 # Real time elapsed on the host +host_inst_rate 166907 # Simulator instruction rate (inst/s) +host_tick_rate 48544601 # Simulator tick rate (ticks/s) +host_mem_usage 212296 # Number of bytes of host memory used +host_seconds 8421.46 # Real time elapsed on the host sim_insts 1405604152 # Number of instructions simulated system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 849692007 # number of cpu cycles simulated +system.cpu.numCycles 817632721 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 103951242 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 92817618 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 5441892 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 101027131 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 99845588 # Number of BTB hits +system.cpu.BPredUnit.lookups 103174324 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 92051331 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 5438120 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 100325127 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 99277633 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1240 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 176461208 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1731297968 # Number of instructions fetch has processed -system.cpu.fetch.Branches 103951242 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99846828 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 372380430 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 32542357 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 273950532 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1598 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 171982366 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1072419 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 849334249 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.043796 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.987927 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1230 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 220 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 175005792 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1720391035 # Number of instructions fetch has processed +system.cpu.fetch.Branches 103174324 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99278863 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 370286255 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31094297 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 246539947 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 21 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1680 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 170773896 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 991956 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 817274934 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.110623 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.012258 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 476953819 56.16% 56.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 82874443 9.76% 65.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 45104012 5.31% 71.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 23823207 2.80% 74.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 33449263 3.94% 77.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 34018296 4.01% 81.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 14934889 1.76% 83.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7594649 0.89% 84.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 130581671 15.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 446988679 54.69% 54.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 82419688 10.08% 64.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 45028734 5.51% 70.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 23714407 2.90% 73.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 33177153 4.06% 77.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 33877408 4.15% 81.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 14961867 1.83% 83.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7384305 0.90% 84.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 129722693 15.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 849334249 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122340 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.037559 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 228750775 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 225010682 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 340329593 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 28702732 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 26540467 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1719853048 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 26540467 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 263479088 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 41404306 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 55665718 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 333164025 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 129080645 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1702621917 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 27946870 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 65424391 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 16478266 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1420563184 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2876973295 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2842990293 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 33983002 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 817274934 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126187 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.104112 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 224321388 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 200349407 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 337624010 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 29538890 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 25441239 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1710162106 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 25441239 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 255728945 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 34334751 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 55175561 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 334633255 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 111961183 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1694040603 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 27905496 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 64677715 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3154928 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1413596061 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2861791975 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2827818793 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 33973182 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 175792732 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3237844 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3287220 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 297721307 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 456905033 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 186186881 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 277685429 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 94682535 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1573041480 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3078086 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1493571680 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 168879 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 169173312 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 193746620 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 834415 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 849334249 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.758520 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.350284 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 168825609 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3228150 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3270628 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 258968806 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 454536844 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 185491805 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 260927641 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 90896258 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1566773345 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3062819 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1493172729 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 111198 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 163655037 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 180232812 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 819148 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 817274934 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.827014 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.412188 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 177901650 20.95% 20.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 206358445 24.30% 45.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 226462970 26.66% 71.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 151667203 17.86% 89.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 64968416 7.65% 97.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14273144 1.68% 99.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6071046 0.71% 99.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1430974 0.17% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 200401 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 168134039 20.57% 20.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 190992211 23.37% 43.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 210117454 25.71% 69.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 154482053 18.90% 88.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 65263213 7.99% 96.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16377311 2.00% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7979086 0.98% 99.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3751008 0.46% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 178559 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 849334249 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 817274934 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 106837 5.02% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 176348 8.29% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1497549 70.41% 83.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 346224 16.28% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 154618 7.33% 7.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 176227 8.36% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1421289 67.40% 83.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 356622 16.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 886788388 59.37% 59.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2623578 0.18% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 886609078 59.38% 59.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2623677 0.18% 59.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued @@ -168,85 +168,85 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 430759220 28.84% 88.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 173400494 11.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 430399729 28.82% 88.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173540245 11.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1493571680 # Type of FU issued -system.cpu.iq.rate 1.757780 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2126958 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001424 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3820899737 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1736825318 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1473365597 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17873709 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9212850 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8524107 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1486479437 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9219201 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 209970408 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1493172729 # Type of FU issued +system.cpu.iq.rate 1.826214 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2108756 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001412 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3787980335 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1724526520 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1473498966 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17860011 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9206634 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8523998 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1486074999 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9206486 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 205830187 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 54392189 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 142413 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 763229 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 19338739 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 52024000 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 213849 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 253991 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 18643663 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 609 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 45345 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 681 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 45180 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 26540467 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2525220 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 145175 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1675654819 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4255922 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 456905033 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 186186881 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2976415 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 59600 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 9064 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 763229 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5291175 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 468114 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 5759289 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1486215446 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 427697474 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7356234 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 25441239 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2526766 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 145081 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1668881823 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4258646 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 454536844 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 185491805 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2961001 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 59126 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7519 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 253991 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5294422 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 459505 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 5753927 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1485801812 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 427360543 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7370917 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 99535253 # number of nop insts executed -system.cpu.iew.exec_refs 599761085 # number of memory reference insts executed -system.cpu.iew.exec_branches 90544158 # Number of branches executed -system.cpu.iew.exec_stores 172063611 # Number of stores executed -system.cpu.iew.exec_rate 1.749123 # Inst execution rate -system.cpu.iew.wb_sent 1483627085 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1481889704 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1175309728 # num instructions producing a value -system.cpu.iew.wb_consumers 1225337993 # num instructions consuming a value +system.cpu.iew.exec_nop 99045659 # number of nop insts executed +system.cpu.iew.exec_refs 599531836 # number of memory reference insts executed +system.cpu.iew.exec_branches 90620288 # Number of branches executed +system.cpu.iew.exec_stores 172171293 # Number of stores executed +system.cpu.iew.exec_rate 1.817200 # Inst execution rate +system.cpu.iew.wb_sent 1483493878 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1482022964 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1178273779 # num instructions producing a value +system.cpu.iew.wb_consumers 1228157747 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.744032 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.959172 # average fanout of values written-back +system.cpu.iew.wb_rate 1.812578 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.959383 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 186029259 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 179255835 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5441892 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 822794393 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.810323 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.360899 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5438120 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 791834306 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.881105 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.451655 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 271095175 32.95% 32.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 302645797 36.78% 69.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 45322356 5.51% 75.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 68686908 8.35% 83.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 22732084 2.76% 86.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 9729610 1.18% 87.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 29628308 3.60% 91.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10807412 1.31% 92.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 62146743 7.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 260467018 32.89% 32.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288028220 36.37% 69.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 45072234 5.69% 74.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 56206737 7.10% 82.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24021941 3.03% 85.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8787658 1.11% 86.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30300633 3.83% 90.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10698376 1.35% 91.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 68251489 8.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 822794393 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 791834306 # Number of insts commited each cycle system.cpu.commit.count 1489523295 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 569360986 # Number of memory references committed @@ -256,50 +256,50 @@ system.cpu.commit.branches 86248929 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 62146743 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 68251489 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2436135334 # The number of ROB reads -system.cpu.rob.rob_writes 3377694632 # The number of ROB writes -system.cpu.timesIdled 11301 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 357758 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2392297077 # The number of ROB reads +system.cpu.rob.rob_writes 3363039880 # The number of ROB writes +system.cpu.timesIdled 11286 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 357787 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1405604152 # Number of Instructions Simulated system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated -system.cpu.cpi 0.604503 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.604503 # CPI: Total CPI of All Threads -system.cpu.ipc 1.654251 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.654251 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2015965671 # number of integer regfile reads -system.cpu.int_regfile_writes 1304123959 # number of integer regfile writes -system.cpu.fp_regfile_reads 16988422 # number of floating regfile reads -system.cpu.fp_regfile_writes 10452078 # number of floating regfile writes -system.cpu.misc_regfile_reads 605607850 # number of misc regfile reads +system.cpu.cpi 0.581695 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.581695 # CPI: Total CPI of All Threads +system.cpu.ipc 1.719114 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.719114 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2016058791 # number of integer regfile reads +system.cpu.int_regfile_writes 1303867666 # number of integer regfile writes +system.cpu.fp_regfile_reads 16986540 # number of floating regfile reads +system.cpu.fp_regfile_writes 10452290 # number of floating regfile writes +system.cpu.misc_regfile_reads 605383822 # number of misc regfile reads system.cpu.misc_regfile_writes 2258933 # number of misc regfile writes system.cpu.icache.replacements 166 # number of replacements -system.cpu.icache.tagsinuse 1030.164560 # Cycle average of tags in use -system.cpu.icache.total_refs 171980565 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1297 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 132598.739399 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 1031.400456 # Cycle average of tags in use +system.cpu.icache.total_refs 170772098 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1298 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 131565.560863 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1030.164560 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.503010 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 171980565 # number of ReadReq hits -system.cpu.icache.demand_hits 171980565 # number of demand (read+write) hits -system.cpu.icache.overall_hits 171980565 # number of overall hits -system.cpu.icache.ReadReq_misses 1801 # number of ReadReq misses -system.cpu.icache.demand_misses 1801 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1801 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 62794000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 62794000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 62794000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 171982366 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 171982366 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 171982366 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000010 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000010 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34866.185453 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34866.185453 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34866.185453 # average overall miss latency +system.cpu.icache.occ_blocks::0 1031.400456 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.503614 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 170772098 # number of ReadReq hits +system.cpu.icache.demand_hits 170772098 # number of demand (read+write) hits +system.cpu.icache.overall_hits 170772098 # number of overall hits +system.cpu.icache.ReadReq_misses 1798 # number of ReadReq misses +system.cpu.icache.demand_misses 1798 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1798 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 62741500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 62741500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 62741500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 170773896 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 170773896 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 170773896 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000011 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000011 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000011 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 34895.161290 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34895.161290 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34895.161290 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -309,140 +309,140 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 503 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 503 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 503 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1298 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1298 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1298 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 499 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 499 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 499 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1299 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1299 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1299 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 45168500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 45168500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 45168500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 45206000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 45206000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 45206000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34798.536210 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34798.536210 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34798.536210 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34800.615858 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34800.615858 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34800.615858 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 475459 # number of replacements -system.cpu.dcache.tagsinuse 4095.196777 # Cycle average of tags in use -system.cpu.dcache.total_refs 381789765 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 479555 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 796.133426 # Average number of references to valid blocks. +system.cpu.dcache.replacements 475353 # number of replacements +system.cpu.dcache.tagsinuse 4095.165283 # Cycle average of tags in use +system.cpu.dcache.total_refs 385593109 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 479449 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 804.242180 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 131001000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4095.196777 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999804 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 216852847 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 164935599 # number of WriteReq hits +system.cpu.dcache.occ_blocks::0 4095.165283 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999796 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 220654856 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 164936934 # number of WriteReq hits system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits 381788446 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 381788446 # number of overall hits -system.cpu.dcache.ReadReq_misses 816608 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1911217 # number of WriteReq misses +system.cpu.dcache.demand_hits 385591790 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 385591790 # number of overall hits +system.cpu.dcache.ReadReq_misses 815916 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1909882 # number of WriteReq misses system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses -system.cpu.dcache.demand_misses 2727825 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2727825 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 11966798000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 30001558232 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 2725798 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2725798 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 11966603000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 29861651909 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency 268000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency 41968356232 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 41968356232 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 217669455 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 41828254909 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 41828254909 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 221470772 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 384516271 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 384516271 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.003752 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.011455 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses 388317588 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 388317588 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.003684 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.011447 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate 0.007094 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.007094 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 14654.274756 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 15697.620015 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate 0.007020 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.007020 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 14666.464440 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 15635.338680 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency 38285.714286 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency 15385.281766 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 15385.281766 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency 15345.324528 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 15345.324528 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2071.428571 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2153.846154 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 3000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 426734 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 604334 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1643943 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2248277 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2248277 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 212274 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 267274 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks 426654 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 603731 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1642625 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2246356 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2246356 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 212185 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 267257 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses 479548 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 479548 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 479442 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 479442 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1589212000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3626989841 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1589383500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3625603341 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency 247000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5216201841 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5216201841 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5214986841 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5214986841 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000975 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000958 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.001602 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.001247 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.001247 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7486.606933 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13570.305533 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.001235 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.001235 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7490.555412 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13565.980839 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35285.714286 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 10877.329988 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 10877.329988 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 10877.200665 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 10877.200665 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 75834 # number of replacements -system.cpu.l2cache.tagsinuse 17835.857801 # Cycle average of tags in use -system.cpu.l2cache.total_refs 464745 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 91356 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.087186 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 75859 # number of replacements +system.cpu.l2cache.tagsinuse 17814.801426 # Cycle average of tags in use +system.cpu.l2cache.total_refs 464590 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 91380 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.084154 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2067.900619 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15767.957182 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.063107 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.481200 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 179917 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 426734 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 206874 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 386791 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 386791 # number of overall hits -system.cpu.l2cache.ReadReq_misses 33655 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 60407 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 94062 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 94062 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1145507000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2078924500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3224431500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3224431500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 213572 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 426734 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 267281 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 480853 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 480853 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.157582 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.226006 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.195615 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.195615 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34036.755311 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34415.291274 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34279.852650 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34279.852650 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 2079.678027 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15735.123399 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.063467 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.480198 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 179822 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 426654 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 206842 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 386664 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 386664 # number of overall hits +system.cpu.l2cache.ReadReq_misses 33662 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 60422 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 94084 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 94084 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1145731000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2079178500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3224909500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3224909500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 213484 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 426654 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 267264 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 480748 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 480748 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.157679 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.226076 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.195703 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.195703 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34036.331769 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34410.951309 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34276.917435 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34276.917435 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -451,27 +451,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59251 # number of writebacks +system.cpu.l2cache.writebacks 59257 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 33655 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 60407 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 94062 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 94062 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 33662 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 60422 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 94084 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 94084 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1043470000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1892046500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2935516500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2935516500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1043686000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1892150500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2935836500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2935836500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157582 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.226006 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.195615 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.195615 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.902689 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31321.643187 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.314729 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.314729 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157679 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.226076 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.195703 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.195703 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.871962 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31315.588693 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31204.418392 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31204.418392 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini index 244f95975..a12b8078f 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/x86/linux/gzip +executable=/dist/m5/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index 03608f531..8176c7e05 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/si gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 18 2011 15:15:16 -gem5 started Aug 18 2011 15:56:00 -gem5 executing on nadc-0330 +gem5 compiled Aug 20 2011 13:24:14 +gem5 started Aug 20 2011 13:24:28 +gem5 executing on zizzer command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1064,4 +1064,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 631043541000 because target called exit() +Exiting @ tick 586755503000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index e79e605fc..5610b27f8 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,251 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.631044 # Number of seconds simulated -sim_ticks 631043541000 # Number of ticks simulated +sim_seconds 0.586756 # Number of seconds simulated +sim_ticks 586755503000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115557 # Simulator instruction rate (inst/s) -host_tick_rate 44971725 # Simulator tick rate (ticks/s) -host_mem_usage 259448 # Number of bytes of host memory used -host_seconds 14032.01 # Real time elapsed on the host +host_inst_rate 143909 # Simulator instruction rate (inst/s) +host_tick_rate 52074943 # Simulator tick rate (ticks/s) +host_mem_usage 212036 # Number of bytes of host memory used +host_seconds 11267.52 # Real time elapsed on the host sim_insts 1621493982 # Number of instructions simulated system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1262087083 # number of cpu cycles simulated +system.cpu.numCycles 1173511007 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 172291796 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 172291796 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 7138140 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 165694672 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 164669298 # Number of BTB hits +system.cpu.BPredUnit.lookups 142841694 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 142841694 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7891104 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 135940863 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 135060067 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 187457062 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1372690648 # Number of instructions fetch has processed -system.cpu.fetch.Branches 172291796 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 164669298 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 395189805 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 112734719 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 580214048 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 58 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 390 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 176517375 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1196842 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1261930799 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.983622 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.216635 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 143543484 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1144373207 # Number of instructions fetch has processed +system.cpu.fetch.Branches 142841694 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 135060067 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 330625683 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 57747911 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 649508878 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 57 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 359 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 137309352 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 979465 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1173333177 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.784853 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.106580 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 869789775 68.93% 68.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 26036678 2.06% 70.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 17623388 1.40% 72.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 17507853 1.39% 73.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 23833900 1.89% 75.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 16948501 1.34% 77.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 37076715 2.94% 79.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 38063595 3.02% 82.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 215050394 17.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 845712931 72.08% 72.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 16031093 1.37% 73.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 18099843 1.54% 74.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 17610691 1.50% 76.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 23355712 1.99% 78.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 16618957 1.42% 79.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 23183901 1.98% 81.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28217498 2.40% 84.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 184502551 15.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1261930799 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.136513 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.087635 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 280972137 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 498778976 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 296140618 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 86969632 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 99069436 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2448347491 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 99069436 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 329963846 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 111715541 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3471 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 317046121 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 404132384 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2409604498 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5352 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 248907784 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 129341699 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2413708682 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5838625893 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5838622529 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3364 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1173333177 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.121722 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.975170 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 241132491 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 558355752 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 229474776 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 94715442 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 49654716 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2072768748 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 49654716 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 290885704 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 132416469 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3327 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 257077103 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 443295858 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2043085659 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2266 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 278274210 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 129493006 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2031275937 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4957669219 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4957665711 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3508 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 795714032 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 96 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 96 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 735209031 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 621902213 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 256079721 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 462456843 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 162376544 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2335230964 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 413281287 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 97 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 97 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 792932011 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 519352258 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 227004848 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 355033834 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 148905529 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1987362019 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 91 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1868917555 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 372085 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 713469187 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1453396284 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1782207350 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 181989 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 365718291 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 672335048 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1261930799 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.480998 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.347284 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1173333177 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.518927 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.333963 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 328585186 26.04% 26.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 421239585 33.38% 59.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 248611798 19.70% 79.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 160686589 12.73% 91.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 61778588 4.90% 96.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 27094790 2.15% 98.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 12009524 0.95% 99.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1648751 0.13% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 275988 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 272616502 23.23% 23.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 416904584 35.53% 58.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234897308 20.02% 78.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 156871571 13.37% 92.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 54320414 4.63% 96.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 21136145 1.80% 98.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 14479536 1.23% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1803096 0.15% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 304021 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1261930799 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1173333177 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 173659 2.51% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6577211 95.02% 97.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 171078 2.47% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 181055 7.04% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2242910 87.15% 94.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 149595 5.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 26325646 1.41% 1.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1180659411 63.17% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 64.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 467364876 25.01% 89.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 194567622 10.41% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 26996432 1.51% 1.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1102299326 61.85% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 458202367 25.71% 89.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 194709225 10.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1868917555 # Type of FU issued -system.cpu.iq.rate 1.480815 # Inst issue rate -system.cpu.iq.fu_busy_cnt 6921948 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003704 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5007059820 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3055406588 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1845403489 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 122 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 754 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1849513807 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 50 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 191278132 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1782207350 # Type of FU issued +system.cpu.iq.rate 1.518697 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2573560 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001444 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4740503284 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2353289601 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1760306484 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 142 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 608 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 36 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1757784406 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 72 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 205673181 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 202860088 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 64357 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6719705 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 67893664 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 100310133 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 59834 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 216613 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 38818791 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 674 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 36961 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1385 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 35852 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 99069436 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1201433 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 112801 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2335231055 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 659652 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 621902213 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 256079721 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 49654716 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1300952 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 134624 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1987362110 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 591185 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 519352258 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 227004848 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 91 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 57218 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 59 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6719705 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4534206 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2790969 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7325175 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1852764474 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 461769012 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 16153081 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 65366 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 32 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 216613 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4590434 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3486470 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8076904 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1768811104 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 452331737 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 13396246 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 655479520 # number of memory reference insts executed -system.cpu.iew.exec_branches 112349751 # Number of branches executed -system.cpu.iew.exec_stores 193710508 # Number of stores executed -system.cpu.iew.exec_rate 1.468016 # Inst execution rate -system.cpu.iew.wb_sent 1850700108 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1845403509 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1443346270 # num instructions producing a value -system.cpu.iew.wb_consumers 2115960944 # num instructions consuming a value +system.cpu.iew.exec_refs 646217865 # number of memory reference insts executed +system.cpu.iew.exec_branches 112172746 # Number of branches executed +system.cpu.iew.exec_stores 193886128 # Number of stores executed +system.cpu.iew.exec_rate 1.507281 # Inst execution rate +system.cpu.iew.wb_sent 1766741886 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1760306520 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1336435928 # num instructions producing a value +system.cpu.iew.wb_consumers 2002913192 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.462184 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.682123 # average fanout of values written-back +system.cpu.iew.wb_rate 1.500034 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.667246 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 713749948 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 365887065 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7138191 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1162861363 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.394400 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.690304 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7891152 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1123678461 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.443023 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.662640 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 395572650 34.02% 34.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 431612406 37.12% 71.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 98230430 8.45% 79.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 129131818 11.10% 90.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 30975376 2.66% 93.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25883779 2.23% 95.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22467188 1.93% 97.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 13999993 1.20% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14987723 1.29% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 347480674 30.92% 30.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 438655867 39.04% 69.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 94938828 8.45% 78.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 133745830 11.90% 90.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36833685 3.28% 93.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26175862 2.33% 95.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22548594 2.01% 97.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8175613 0.73% 98.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15123508 1.35% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1162861363 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1123678461 # Number of insts commited each cycle system.cpu.commit.count 1621493982 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 607228182 # Number of memory references committed @@ -255,48 +255,48 @@ system.cpu.commit.branches 107161579 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14987723 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15123508 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3483117570 # The number of ROB reads -system.cpu.rob.rob_writes 4770120987 # The number of ROB writes -system.cpu.timesIdled 44517 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 156284 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3095936000 # The number of ROB reads +system.cpu.rob.rob_writes 4024437562 # The number of ROB writes +system.cpu.timesIdled 44153 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 177830 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1621493982 # Number of Instructions Simulated system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated -system.cpu.cpi 0.778348 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.778348 # CPI: Total CPI of All Threads -system.cpu.ipc 1.284772 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.284772 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3289423155 # number of integer regfile reads -system.cpu.int_regfile_writes 1840387955 # number of integer regfile writes -system.cpu.fp_regfile_reads 20 # number of floating regfile reads -system.cpu.misc_regfile_reads 943704220 # number of misc regfile reads -system.cpu.icache.replacements 12 # number of replacements -system.cpu.icache.tagsinuse 813.354682 # Cycle average of tags in use -system.cpu.icache.total_refs 176516095 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 894 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 197445.296421 # Average number of references to valid blocks. +system.cpu.cpi 0.723722 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.723722 # CPI: Total CPI of All Threads +system.cpu.ipc 1.381746 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.381746 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3273654764 # number of integer regfile reads +system.cpu.int_regfile_writes 1756473314 # number of integer regfile writes +system.cpu.fp_regfile_reads 36 # number of floating regfile reads +system.cpu.misc_regfile_reads 909253494 # number of misc regfile reads +system.cpu.icache.replacements 16 # number of replacements +system.cpu.icache.tagsinuse 813.268656 # Cycle average of tags in use +system.cpu.icache.total_refs 137308116 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 900 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 152564.573333 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 813.354682 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.397146 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 176516138 # number of ReadReq hits -system.cpu.icache.demand_hits 176516138 # number of demand (read+write) hits -system.cpu.icache.overall_hits 176516138 # number of overall hits -system.cpu.icache.ReadReq_misses 1237 # number of ReadReq misses -system.cpu.icache.demand_misses 1237 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1237 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 43406000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 43406000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 43406000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 176517375 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 176517375 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 176517375 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35089.733226 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35089.733226 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35089.733226 # average overall miss latency +system.cpu.icache.occ_blocks::0 813.268656 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.397104 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 137308116 # number of ReadReq hits +system.cpu.icache.demand_hits 137308116 # number of demand (read+write) hits +system.cpu.icache.overall_hits 137308116 # number of overall hits +system.cpu.icache.ReadReq_misses 1236 # number of ReadReq misses +system.cpu.icache.demand_misses 1236 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1236 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 43480000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 43480000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 43480000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 137309352 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 137309352 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 137309352 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35177.993528 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35177.993528 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35177.993528 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -306,167 +306,159 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 339 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 339 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 339 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 898 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 898 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 898 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 336 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 336 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 336 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 900 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 900 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 900 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 31587000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 31587000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 31587000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 31792500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 31792500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 31792500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35174.832962 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35174.832962 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35174.832962 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35325 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35325 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35325 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 459230 # number of replacements -system.cpu.dcache.tagsinuse 4094.984798 # Cycle average of tags in use -system.cpu.dcache.total_refs 457142531 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 463326 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 986.654172 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 317737000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.984798 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999752 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 270249416 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 186893112 # number of WriteReq hits -system.cpu.dcache.demand_hits 457142528 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 457142528 # number of overall hits -system.cpu.dcache.ReadReq_misses 217407 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1292945 # number of WriteReq misses -system.cpu.dcache.demand_misses 1510352 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1510352 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2208510500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 25332209498 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 27540719998 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 27540719998 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 270466823 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 459082 # number of replacements +system.cpu.dcache.tagsinuse 4094.908409 # Cycle average of tags in use +system.cpu.dcache.total_refs 433296852 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 463178 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 935.486685 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 317735000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.908409 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999733 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 246417961 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 186878891 # number of WriteReq hits +system.cpu.dcache.demand_hits 433296852 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 433296852 # number of overall hits +system.cpu.dcache.ReadReq_misses 217222 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1307166 # number of WriteReq misses +system.cpu.dcache.demand_misses 1524388 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1524388 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 2206460500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 25191688497 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 27398148997 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 27398148997 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 246635183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 458652880 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 458652880 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000804 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.006871 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.003293 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.003293 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 10158.414862 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 19592.642764 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 18234.636693 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 18234.636693 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1882500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 494592500 # number of cycles access was blocked +system.cpu.dcache.demand_accesses 434821240 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 434821240 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000881 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.006946 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.003506 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.003506 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 10157.629062 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 19271.988789 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 17973.212199 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 17973.212199 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1884500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 490158000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 482 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 34873 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3905.601660 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 14182.677143 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 33499 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3909.751037 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 14632.018866 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 410188 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 3582 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1043440 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1047022 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1047022 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 213825 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 249505 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 463330 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 463330 # number of overall MSHR misses +system.cpu.dcache.writebacks 410010 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 3618 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1057590 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1061208 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1061208 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 213604 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 249576 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 463180 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 463180 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1535603000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2500577500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4036180500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4036180500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1533784000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2518332500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4052116500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4052116500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000791 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000866 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.001326 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.001010 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.001010 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7181.587747 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10022.153865 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8711.243606 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8711.243606 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.001065 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.001065 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7180.502238 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10090.443392 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8748.470357 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8748.470357 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 73611 # number of replacements -system.cpu.l2cache.tagsinuse 18032.065292 # Cycle average of tags in use -system.cpu.l2cache.total_refs 453266 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89232 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.079635 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 73626 # number of replacements +system.cpu.l2cache.tagsinuse 17961.057219 # Cycle average of tags in use +system.cpu.l2cache.total_refs 452680 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 89247 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.072215 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1960.203068 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16071.862223 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.059821 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.490474 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 181561 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 410188 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 190780 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 372341 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 372341 # number of overall hits -system.cpu.l2cache.ReadReq_misses 33157 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 58724 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 91881 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 91881 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1130411500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2017247500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3147659000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3147659000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 214718 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 410188 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 249504 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 464222 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 464222 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.154421 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.500000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.235363 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.197925 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.197925 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34092.695358 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34351.329950 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34257.996757 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34257.996757 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 204000 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::0 1976.377276 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15984.679942 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.060314 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.487814 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 181326 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 410010 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 190857 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 372183 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 372183 # number of overall hits +system.cpu.l2cache.ReadReq_misses 33178 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 58719 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 91897 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 91897 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1131489500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2019003500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3150493000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3150493000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 214504 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 410010 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 249576 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 464080 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 464080 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.154673 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.235275 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.198020 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.198020 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34103.607812 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34384.160153 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34282.871040 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34282.871040 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 202000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 121 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 122 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1685.950413 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1655.737705 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58498 # number of writebacks +system.cpu.l2cache.writebacks 58507 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 33157 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58724 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 91881 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 91881 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 33178 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58719 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 91897 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 91897 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1028041500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1829105500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2857147000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2857147000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1028691000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1828336500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2857027500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2857027500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154421 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235363 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.197925 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.197925 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.262840 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31147.495062 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31096.167869 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31096.167869 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154673 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235275 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.198020 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.198020 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.214299 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31137.051040 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31089.453410 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31089.453410 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index f372f8ce3..51444fd65 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -10,13 +10,13 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/arm/scratch/sysexplr/dist/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem -pal=/arm/scratch/sysexplr/dist/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -933,7 +933,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -953,7 +953,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/arm/scratch/sysexplr/dist/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -1082,7 +1082,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 72ae91dc7..35487e816 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/ts gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 16:33:41 -gem5 started Aug 17 2011 16:35:58 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 15:21:47 +gem5 started Aug 20 2011 15:21:55 +gem5 executing on zizzer command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 98887000 -Exiting @ tick 1897470973500 because m5_exit instruction encountered +info: Launching CPU 1 @ 106949500 +Exiting @ tick 1897465263500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index d4f86dcbd..d2a095e1d 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,133 +1,133 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.897471 # Number of seconds simulated -sim_ticks 1897470973500 # Number of ticks simulated +sim_seconds 1.897465 # Number of seconds simulated +sim_ticks 1897465263500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 112670 # Simulator instruction rate (inst/s) -host_tick_rate 3808310962 # Simulator tick rate (ticks/s) -host_mem_usage 344004 # Number of bytes of host memory used -host_seconds 498.24 # Real time elapsed on the host -sim_insts 56137023 # Number of instructions simulated -system.l2c.replacements 397425 # number of replacements -system.l2c.tagsinuse 35089.523512 # Cycle average of tags in use -system.l2c.total_refs 2483901 # Total number of references to valid blocks. -system.l2c.sampled_refs 433413 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.731026 # Average number of references to valid blocks. -system.l2c.warmup_cycle 9244135000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11999.654790 # Average occupied blocks per context -system.l2c.occ_blocks::1 233.124353 # Average occupied blocks per context -system.l2c.occ_blocks::2 22856.744369 # Average occupied blocks per context -system.l2c.occ_percent::0 0.183100 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.003557 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.348766 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1722706 # number of ReadReq hits -system.l2c.ReadReq_hits::1 146059 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1868765 # number of ReadReq hits -system.l2c.Writeback_hits::0 827102 # number of Writeback hits -system.l2c.Writeback_hits::total 827102 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 179 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 47 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 226 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 26 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 27 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 53 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 168351 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 11011 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 179362 # number of ReadExReq hits -system.l2c.demand_hits::0 1891057 # number of demand (read+write) hits -system.l2c.demand_hits::1 157070 # number of demand (read+write) hits +host_inst_rate 131766 # Simulator instruction rate (inst/s) +host_tick_rate 4454253159 # Simulator tick rate (ticks/s) +host_mem_usage 298700 # Number of bytes of host memory used +host_seconds 425.99 # Real time elapsed on the host +sim_insts 56130966 # Number of instructions simulated +system.l2c.replacements 397795 # number of replacements +system.l2c.tagsinuse 35116.884908 # Cycle average of tags in use +system.l2c.total_refs 2482671 # Total number of references to valid blocks. +system.l2c.sampled_refs 433561 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.726232 # Average number of references to valid blocks. +system.l2c.warmup_cycle 9252063000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::0 12003.983788 # Average occupied blocks per context +system.l2c.occ_blocks::1 238.395777 # Average occupied blocks per context +system.l2c.occ_blocks::2 22874.505342 # Average occupied blocks per context +system.l2c.occ_percent::0 0.183166 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.003638 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.349037 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1719678 # number of ReadReq hits +system.l2c.ReadReq_hits::1 147350 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1867028 # number of ReadReq hits +system.l2c.Writeback_hits::0 826540 # number of Writeback hits +system.l2c.Writeback_hits::total 826540 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 172 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 46 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 218 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 28 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 28 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 56 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 168225 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 11091 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 179316 # number of ReadExReq hits +system.l2c.demand_hits::0 1887903 # number of demand (read+write) hits +system.l2c.demand_hits::1 158441 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 2048127 # number of demand (read+write) hits -system.l2c.overall_hits::0 1891057 # number of overall hits -system.l2c.overall_hits::1 157070 # number of overall hits +system.l2c.demand_hits::total 2046344 # number of demand (read+write) hits +system.l2c.overall_hits::0 1887903 # number of overall hits +system.l2c.overall_hits::1 158441 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 2048127 # number of overall hits -system.l2c.ReadReq_misses::0 305325 # number of ReadReq misses -system.l2c.ReadReq_misses::1 4048 # number of ReadReq misses -system.l2c.ReadReq_misses::total 309373 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 2451 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 556 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3007 # number of UpgradeReq misses +system.l2c.overall_hits::total 2046344 # number of overall hits +system.l2c.ReadReq_misses::0 305537 # number of ReadReq misses +system.l2c.ReadReq_misses::1 4057 # number of ReadReq misses +system.l2c.ReadReq_misses::total 309594 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 2453 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 560 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3013 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::0 48 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 82 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 130 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 113992 # number of ReadExReq misses +system.l2c.SCUpgradeReq_misses::1 84 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 132 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 113925 # number of ReadExReq misses system.l2c.ReadExReq_misses::1 10735 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124727 # number of ReadExReq misses -system.l2c.demand_misses::0 419317 # number of demand (read+write) misses -system.l2c.demand_misses::1 14783 # number of demand (read+write) misses +system.l2c.ReadExReq_misses::total 124660 # number of ReadExReq misses +system.l2c.demand_misses::0 419462 # number of demand (read+write) misses +system.l2c.demand_misses::1 14792 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 434100 # number of demand (read+write) misses -system.l2c.overall_misses::0 419317 # number of overall misses -system.l2c.overall_misses::1 14783 # number of overall misses +system.l2c.demand_misses::total 434254 # number of demand (read+write) misses +system.l2c.overall_misses::0 419462 # number of overall misses +system.l2c.overall_misses::1 14792 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 434100 # number of overall misses -system.l2c.ReadReq_miss_latency 16104881500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 3975000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency 681000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6543645500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 22648527000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 22648527000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2028031 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 150107 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2178138 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 827102 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 827102 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 2630 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 603 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3233 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 74 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 109 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 183 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 282343 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 21746 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 304089 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2310374 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 171853 # number of demand (read+write) accesses +system.l2c.overall_misses::total 434254 # number of overall misses +system.l2c.ReadReq_miss_latency 16116451000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 3978500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency 680500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 6538718500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 22655169500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 22655169500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2025215 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 151407 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2176622 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 826540 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 826540 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 2625 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 606 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3231 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 76 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 112 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 282150 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 21826 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 303976 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2307365 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 173233 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2482227 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2310374 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 171853 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2480598 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2307365 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 173233 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2482227 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.150552 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.026967 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.931939 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.922056 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.648649 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.752294 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.403736 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.493654 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.181493 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.086021 # miss rate for demand accesses +system.l2c.overall_accesses::total 2480598 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.150866 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.026795 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.934476 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.924092 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.631579 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.750000 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.403775 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.491845 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.181793 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.085388 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.181493 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.086021 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.181793 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.085388 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52746.684680 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 3978478.631423 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::0 52747.951967 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 3972504.560020 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 1621.787026 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 7149.280576 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 1621.891561 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 7104.464286 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 14187.500000 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 8304.878049 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::0 14177.083333 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 8101.190476 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 57404.427504 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 609561.760596 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 57394.939653 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 609102.794597 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 54012.899549 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1532065.683555 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 54010.064082 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1531582.578421 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 54012.899549 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1532065.683555 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 54010.064082 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1531582.578421 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -138,100 +138,100 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 122219 # number of writebacks -system.l2c.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 17 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 17 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 309356 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3007 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 130 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 124727 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 434083 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 434083 # number of overall MSHR misses +system.l2c.writebacks 122051 # number of writebacks +system.l2c.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits 18 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 18 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 309576 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3013 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses 132 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 124660 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 434236 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 434236 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12384389500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 120345500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 5200000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5026892500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 17411282000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 17411282000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 838237000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1420706998 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 2258943998 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.152540 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 2.060903 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12393243000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 120589000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency 5280000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5022395000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 17415638000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 17415638000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 838122500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1421433998 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 2259556498 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.152861 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 2.044661 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 1.143346 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 4.986733 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1.147810 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 4.971947 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.756757 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.192661 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.736842 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.178571 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.441757 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 5.735630 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.441822 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 5.711537 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.187884 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 2.525897 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.188196 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 2.506659 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.187884 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 2.525897 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.188196 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 2.506659 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40032.808480 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40021.782507 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40032.957981 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40022.900763 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40303.162106 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40110.490390 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40110.490390 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40288.745387 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40106.389152 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40106.389152 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41699 # number of replacements -system.iocache.tagsinuse 0.463134 # Cycle average of tags in use +system.iocache.replacements 41697 # number of replacements +system.iocache.tagsinuse 0.463240 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41715 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1709323096000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.463134 # Average occupied blocks per context -system.iocache.occ_percent::1 0.028946 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1709322874000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.463240 # Average occupied blocks per context +system.iocache.occ_percent::1 0.028953 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 179 # number of ReadReq misses -system.iocache.ReadReq_misses::total 179 # number of ReadReq misses +system.iocache.ReadReq_misses::1 177 # number of ReadReq misses +system.iocache.ReadReq_misses::total 177 # number of ReadReq misses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41731 # number of demand (read+write) misses -system.iocache.demand_misses::total 41731 # number of demand (read+write) misses +system.iocache.demand_misses::1 41729 # number of demand (read+write) misses +system.iocache.demand_misses::total 41729 # number of demand (read+write) misses system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41731 # number of overall misses -system.iocache.overall_misses::total 41731 # number of overall misses -system.iocache.ReadReq_miss_latency 20616998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5721081806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5741698804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5741698804 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 179 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) +system.iocache.overall_misses::1 41729 # number of overall misses +system.iocache.overall_misses::total 41729 # number of overall misses +system.iocache.ReadReq_miss_latency 20390998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 5721236806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 5741627804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 5741627804 # number of overall miss cycles +system.iocache.ReadReq_accesses::1 177 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41731 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41729 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41731 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41729 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses @@ -241,37 +241,37 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115178.759777 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115203.378531 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137684.872112 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137688.602378 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137588.334907 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137593.227827 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137588.334907 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137593.227827 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64637068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64620068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10458 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6180.633773 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6179.008223 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks 41520 # number of writebacks system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.ReadReq_mshr_misses 179 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses 177 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses 41731 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 41731 # number of overall MSHR misses +system.iocache.demand_mshr_misses 41729 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses 41729 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 11308998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3560223994 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3571532992 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3571532992 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 11186998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3560378000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3571564998 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3571564998 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -285,10 +285,10 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 63178.759777 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85681.170437 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85584.649110 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85584.649110 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63203.378531 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85684.876781 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85589.518033 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85589.518033 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -309,22 +309,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9537119 # DTB read hits -system.cpu0.dtb.read_misses 35694 # DTB read misses -system.cpu0.dtb.read_acv 589 # DTB read access violations -system.cpu0.dtb.read_accesses 644456 # DTB read accesses -system.cpu0.dtb.write_hits 6201700 # DTB write hits -system.cpu0.dtb.write_misses 7404 # DTB write misses -system.cpu0.dtb.write_acv 340 # DTB write access violations -system.cpu0.dtb.write_accesses 219479 # DTB write accesses -system.cpu0.dtb.data_hits 15738819 # DTB hits -system.cpu0.dtb.data_misses 43098 # DTB misses -system.cpu0.dtb.data_acv 929 # DTB access violations -system.cpu0.dtb.data_accesses 863935 # DTB accesses -system.cpu0.itb.fetch_hits 1065001 # ITB hits -system.cpu0.itb.fetch_misses 28395 # ITB misses -system.cpu0.itb.fetch_acv 959 # ITB acv -system.cpu0.itb.fetch_accesses 1093396 # ITB accesses +system.cpu0.dtb.read_hits 9507417 # DTB read hits +system.cpu0.dtb.read_misses 35968 # DTB read misses +system.cpu0.dtb.read_acv 598 # DTB read access violations +system.cpu0.dtb.read_accesses 640032 # DTB read accesses +system.cpu0.dtb.write_hits 6191307 # DTB write hits +system.cpu0.dtb.write_misses 8160 # DTB write misses +system.cpu0.dtb.write_acv 353 # DTB write access violations +system.cpu0.dtb.write_accesses 218604 # DTB write accesses +system.cpu0.dtb.data_hits 15698724 # DTB hits +system.cpu0.dtb.data_misses 44128 # DTB misses +system.cpu0.dtb.data_acv 951 # DTB access violations +system.cpu0.dtb.data_accesses 858636 # DTB accesses +system.cpu0.itb.fetch_hits 1059111 # ITB hits +system.cpu0.itb.fetch_misses 28345 # ITB misses +system.cpu0.itb.fetch_acv 951 # ITB acv +system.cpu0.itb.fetch_accesses 1087456 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -337,147 +337,147 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 112251413 # number of cpu cycles simulated +system.cpu0.numCycles 112078637 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 13715156 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 11502951 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 484161 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 12377728 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 6363664 # Number of BTB hits +system.cpu0.BPredUnit.lookups 13676513 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 11471993 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 481224 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 12342117 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 6355141 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 918279 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 37972 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 28099564 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 69844028 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 13715156 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 7281943 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 13538078 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2172072 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 34812736 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 29955 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 193219 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 330912 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 98 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8567969 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 303515 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 78411579 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.890736 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.207630 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 915334 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 37832 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 28007609 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 69419364 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 13676513 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 7270475 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 13464854 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2130456 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 34838342 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 29311 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 192876 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 330870 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 82 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8508842 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 295697 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 78241728 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.887242 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.203788 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 64873501 82.73% 82.73% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 956509 1.22% 83.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1906420 2.43% 86.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 900643 1.15% 87.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2836490 3.62% 91.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 653196 0.83% 91.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 748865 0.96% 92.94% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1020020 1.30% 94.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4515935 5.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 64776874 82.79% 82.79% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 958993 1.23% 84.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1895458 2.42% 86.44% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 896557 1.15% 87.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2826529 3.61% 91.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 644193 0.82% 92.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 736181 0.94% 92.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1019927 1.30% 94.27% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4487016 5.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 78411579 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.122182 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.622211 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 29218734 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 34518564 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 12397503 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 907653 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1369124 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 565623 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 38130 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 68326357 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 115471 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1369124 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 30359966 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12420002 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18653448 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 11559609 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4049428 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 64489639 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6675 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 459269 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1452522 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 43185187 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 78281955 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 77849999 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 431956 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36504578 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 6680601 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1578071 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 238750 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11394232 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10044360 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6546770 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1193752 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 777018 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 56531127 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 2009866 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 55005856 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 111558 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 7605242 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3895552 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1371310 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 78411579 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.701502 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.348295 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 78241728 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.122026 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.619381 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 29114965 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 34547748 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 12317154 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 921824 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1340036 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 563514 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 37992 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 67952438 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 114909 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1340036 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 30246504 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12447336 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18631420 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 11494424 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4082006 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 64196257 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6719 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 464674 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1470831 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 42946380 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 77900777 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 77469173 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 431604 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36477108 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 6469264 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1576496 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 238440 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11483101 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10008373 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6527102 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1185571 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 771360 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 56320474 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 2007436 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 54875963 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 110266 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 7429207 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3754226 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1369428 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 78241728 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.701364 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.347589 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54224531 69.15% 69.15% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10651966 13.58% 82.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 5211873 6.65% 89.39% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3322855 4.24% 93.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2518388 3.21% 96.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1465679 1.87% 98.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 653633 0.83% 99.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 263398 0.34% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 99256 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54100520 69.15% 69.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10639232 13.60% 82.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 5191485 6.64% 89.38% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3321136 4.24% 93.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2520069 3.22% 96.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1468713 1.88% 98.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 637402 0.81% 99.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 263268 0.34% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 99903 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 78411579 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 78241728 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 63058 8.97% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 343865 48.92% 57.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 295935 42.10% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 61581 8.74% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 342929 48.66% 57.40% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 300261 42.60% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3328 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 37799296 68.72% 68.72% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 60344 0.11% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15686 0.03% 68.86% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.86% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.86% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.86% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3329 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 37711302 68.72% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 60327 0.11% 68.84% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.84% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15682 0.03% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.87% # Type of FU issued system.cpu0.iq.FU_type_0::FloatDiv 1654 0.00% 68.87% # Type of FU issued system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.87% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.87% # Type of FU issued @@ -500,112 +500,112 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.87% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.87% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.87% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9967542 18.12% 86.99% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6280275 11.42% 98.40% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 877731 1.60% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9937545 18.11% 86.98% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6268980 11.42% 98.40% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 877144 1.60% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 55005856 # Type of FU issued -system.cpu0.iq.rate 0.490024 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 702858 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.012778 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 188615716 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 65871549 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 53572345 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 621990 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 297473 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 294666 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 55378554 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 326832 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 547956 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 54875963 # Type of FU issued +system.cpu0.iq.rate 0.489620 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 704772 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.012843 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 188187092 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 65472775 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 53463452 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 621599 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 297101 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 294471 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 55250754 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 326652 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 544032 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1439562 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 14656 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 23453 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 541104 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1411765 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 14119 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13054 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 526523 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18437 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 167543 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 19033 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 166880 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1369124 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8683441 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 605421 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 62052001 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 831027 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10044360 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6546770 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1774362 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 483184 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 10442 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 23453 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 350905 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 357470 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 708375 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 54360123 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9599991 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 645732 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1340036 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8692237 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 606269 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 61830785 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 830784 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10008373 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6527102 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1772467 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 482817 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 10549 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13054 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 346528 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 358003 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 704531 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 54241616 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9570533 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 634346 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3511008 # number of nop insts executed -system.cpu0.iew.exec_refs 15823517 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8665836 # Number of branches executed -system.cpu0.iew.exec_stores 6223526 # Number of stores executed -system.cpu0.iew.exec_rate 0.484271 # Inst execution rate -system.cpu0.iew.wb_sent 53987864 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 53867011 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26614200 # num instructions producing a value -system.cpu0.iew.wb_consumers 35806994 # num instructions consuming a value +system.cpu0.iew.exec_nop 3502875 # number of nop insts executed +system.cpu0.iew.exec_refs 15784325 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8657029 # Number of branches executed +system.cpu0.iew.exec_stores 6213792 # Number of stores executed +system.cpu0.iew.exec_rate 0.483960 # Inst execution rate +system.cpu0.iew.wb_sent 53872827 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 53757923 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26542591 # num instructions producing a value +system.cpu0.iew.wb_consumers 35724968 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.479878 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.743268 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.479645 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.742970 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 53695815 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 8260876 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638556 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 645745 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 77042455 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.696964 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.608185 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 53656716 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 8078010 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638008 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 642783 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 76901692 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.697731 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.609209 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 56792844 73.72% 73.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8505609 11.04% 84.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4528626 5.88% 90.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2490278 3.23% 93.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1477167 1.92% 95.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 617055 0.80% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 444256 0.58% 97.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 490319 0.64% 97.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1696301 2.20% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 56673915 73.70% 73.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8488315 11.04% 84.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4528829 5.89% 90.62% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2497024 3.25% 93.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1465718 1.91% 95.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 614414 0.80% 96.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 447034 0.58% 97.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 489019 0.64% 97.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1697424 2.21% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 77042455 # Number of insts commited each cycle -system.cpu0.commit.count 53695815 # Number of instructions committed +system.cpu0.commit.committed_per_cycle::total 76901692 # Number of insts commited each cycle +system.cpu0.commit.count 53656716 # Number of instructions committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14610464 # Number of memory references committed -system.cpu0.commit.loads 8604798 # Number of loads committed -system.cpu0.commit.membars 217772 # Number of memory barriers committed -system.cpu0.commit.branches 8097271 # Number of branches committed -system.cpu0.commit.fp_insts 292136 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 49674100 # Number of committed integer instructions. -system.cpu0.commit.function_calls 705369 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1696301 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14597187 # Number of memory references committed +system.cpu0.commit.loads 8596608 # Number of loads committed +system.cpu0.commit.membars 217615 # Number of memory barriers committed +system.cpu0.commit.branches 8092300 # Number of branches committed +system.cpu0.commit.fp_insts 291990 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 49637924 # Number of committed integer instructions. +system.cpu0.commit.function_calls 704482 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1697424 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 137112360 # The number of ROB reads -system.cpu0.rob.rob_writes 125284104 # The number of ROB writes -system.cpu0.timesIdled 1232970 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 33839834 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 50579161 # Number of Instructions Simulated -system.cpu0.committedInsts_total 50579161 # Number of Instructions Simulated -system.cpu0.cpi 2.219321 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.219321 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.450588 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.450588 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 71273377 # number of integer regfile reads -system.cpu0.int_regfile_writes 38974201 # number of integer regfile writes -system.cpu0.fp_regfile_reads 144005 # number of floating regfile reads -system.cpu0.fp_regfile_writes 146400 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1864820 # number of misc regfile reads -system.cpu0.misc_regfile_writes 888952 # number of misc regfile writes +system.cpu0.rob.rob_reads 136748495 # The number of ROB reads +system.cpu0.rob.rob_writes 124811050 # The number of ROB writes +system.cpu0.timesIdled 1231942 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 33836909 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 50542242 # Number of Instructions Simulated +system.cpu0.committedInsts_total 50542242 # Number of Instructions Simulated +system.cpu0.cpi 2.217524 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.217524 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.450953 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.450953 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 71124780 # number of integer regfile reads +system.cpu0.int_regfile_writes 38876207 # number of integer regfile writes +system.cpu0.fp_regfile_reads 143910 # number of floating regfile reads +system.cpu0.fp_regfile_writes 146325 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1863327 # number of misc regfile reads +system.cpu0.misc_regfile_writes 888204 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -637,233 +637,233 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 972255 # number of replacements -system.cpu0.icache.tagsinuse 509.997473 # Cycle average of tags in use -system.cpu0.icache.total_refs 7540990 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 972767 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.752103 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23351428000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 509.997473 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.996089 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 7540990 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7540990 # number of ReadReq hits -system.cpu0.icache.demand_hits::0 7540990 # number of demand (read+write) hits +system.cpu0.icache.replacements 970482 # number of replacements +system.cpu0.icache.tagsinuse 510.008508 # Cycle average of tags in use +system.cpu0.icache.total_refs 7483994 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 970994 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.707559 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23358720000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::0 510.008508 # Average occupied blocks per context +system.cpu0.icache.occ_percent::0 0.996110 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::0 7483994 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7483994 # number of ReadReq hits +system.cpu0.icache.demand_hits::0 7483994 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7540990 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::0 7540990 # number of overall hits +system.cpu0.icache.demand_hits::total 7483994 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::0 7483994 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 7540990 # number of overall hits -system.cpu0.icache.ReadReq_misses::0 1026979 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1026979 # number of ReadReq misses -system.cpu0.icache.demand_misses::0 1026979 # number of demand (read+write) misses +system.cpu0.icache.overall_hits::total 7483994 # number of overall hits +system.cpu0.icache.ReadReq_misses::0 1024848 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1024848 # number of ReadReq misses +system.cpu0.icache.demand_misses::0 1024848 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1026979 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::0 1026979 # number of overall misses +system.cpu0.icache.demand_misses::total 1024848 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::0 1024848 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 1026979 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 15345865496 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 15345865496 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 15345865496 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::0 8567969 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8567969 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::0 8567969 # number of demand (read+write) accesses +system.cpu0.icache.overall_misses::total 1024848 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency 15319794498 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency 15319794498 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency 15319794498 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::0 8508842 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8508842 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::0 8508842 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8567969 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::0 8567969 # number of overall (read+write) accesses +system.cpu0.icache.demand_accesses::total 8508842 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::0 8508842 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8567969 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::0 0.119863 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::0 0.119863 # miss rate for demand accesses +system.cpu0.icache.overall_accesses::total 8508842 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::0 0.120445 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::0 0.120445 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.119863 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::0 0.120445 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::0 14942.725699 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::0 14948.357706 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::0 14942.725699 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::0 14948.357706 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 14942.725699 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::0 14948.357706 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1169997 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 1225998 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 101 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 103 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11584.128713 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11902.893204 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 201 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits 54044 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits 54044 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 54044 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 972935 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 972935 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 972935 # number of overall MSHR misses +system.cpu0.icache.writebacks 218 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits 53716 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits 53716 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits 53716 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses 971132 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses 971132 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses 971132 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 11633224497 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 11633224497 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 11633224497 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency 11617050998 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 11617050998 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 11617050998 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.113555 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.114132 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::0 0.113555 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::0 0.114132 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::0 0.113555 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::0 0.114132 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11956.836271 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11956.836271 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11956.836271 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11962.381013 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 11962.381013 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11962.381013 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1341445 # number of replacements -system.cpu0.dcache.tagsinuse 503.508011 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11371142 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1341956 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.473558 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1339905 # number of replacements +system.cpu0.dcache.tagsinuse 503.729057 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11343106 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1340416 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.462377 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 504.508011 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::0 504.729057 # Average occupied blocks per context system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.985367 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::0 0.985799 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::1 -0.001953 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::0 7002154 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7002154 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::0 3971242 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3971242 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::0 182799 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 182799 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::0 208802 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 208802 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::0 10973396 # number of demand (read+write) hits +system.cpu0.dcache.ReadReq_hits::0 6978274 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6978274 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::0 3967577 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3967577 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::0 182488 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 182488 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::0 208558 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 208558 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::0 10945851 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10973396 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::0 10973396 # number of overall hits +system.cpu0.dcache.demand_hits::total 10945851 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::0 10945851 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 10973396 # number of overall hits -system.cpu0.dcache.ReadReq_misses::0 1698188 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1698188 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::0 1810110 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1810110 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::0 21696 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21696 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::0 665 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 665 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::0 3508298 # number of demand (read+write) misses +system.cpu0.dcache.overall_hits::total 10945851 # number of overall hits +system.cpu0.dcache.ReadReq_misses::0 1696520 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1696520 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::0 1808915 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1808915 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::0 21731 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21731 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::0 693 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 693 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::0 3505435 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3508298 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::0 3508298 # number of overall misses +system.cpu0.dcache.demand_misses::total 3505435 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::0 3505435 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 3508298 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 37024597500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 55205693695 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency 326548500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency 6352500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency 92230291195 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 92230291195 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::0 8700342 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8700342 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::0 5781352 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5781352 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::0 204495 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 204495 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::0 209467 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 209467 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::0 14481694 # number of demand (read+write) accesses +system.cpu0.dcache.overall_misses::total 3505435 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency 37036233000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency 55166183811 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency 327139500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency 6516000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency 92202416811 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency 92202416811 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::0 8674794 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8674794 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::0 5776492 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5776492 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::0 204219 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 204219 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::0 209251 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 209251 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::0 14451286 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14481694 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::0 14481694 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14451286 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::0 14451286 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14481694 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::0 0.195186 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.313095 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.106096 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.003175 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.242257 # miss rate for demand accesses +system.cpu0.dcache.overall_accesses::total 14451286 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::0 0.195569 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::0 0.313151 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.106410 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.003312 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::0 0.242569 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.242257 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::0 0.242569 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::0 21802.413808 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::0 21830.708156 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::0 30498.529755 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::0 30496.835844 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15051.092367 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15054.047214 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 9552.631579 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 9402.597403 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::0 26289.183871 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::0 26302.703320 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 26289.183871 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::0 26302.703320 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 889959290 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 192000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 98831 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9004.859710 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 886352311 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 210500 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 100011 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8862.548230 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 23388.888889 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 791115 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits 651520 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits 1525368 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits 4914 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits 2176888 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 2176888 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 1046668 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 284742 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses 16782 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses 665 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 1331410 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 1331410 # number of overall MSHR misses +system.cpu0.dcache.writebacks 790429 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits 651194 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits 1524352 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits 4898 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits 2175546 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits 2175546 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses 1045326 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses 284563 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses 16833 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses 693 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses 1329889 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses 1329889 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 24224955000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 8301968289 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 194959000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 4349000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 32526923289 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 32526923289 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 917419500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1254211998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 2171631498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.120302 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency 24217800500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency 8294565311 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 195726500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 4430000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 32512365811 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 32512365811 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 916795000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1253240498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency 2170035498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.120502 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.049252 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.049262 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.082066 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.082426 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.003175 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.003312 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::0 0.091937 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::0 0.092026 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0.091937 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::0 0.092026 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23144.831981 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 29156.107244 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11617.149327 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 6539.849624 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 24430.433367 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 24430.433367 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23167.701272 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 29148.432196 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11627.547080 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 6392.496392 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 24447.428177 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 24447.428177 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -874,22 +874,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1324275 # DTB read hits -system.cpu1.dtb.read_misses 10298 # DTB read misses +system.cpu1.dtb.read_hits 1326048 # DTB read hits +system.cpu1.dtb.read_misses 10245 # DTB read misses system.cpu1.dtb.read_acv 4 # DTB read access violations -system.cpu1.dtb.read_accesses 333543 # DTB read accesses -system.cpu1.dtb.write_hits 770562 # DTB write hits -system.cpu1.dtb.write_misses 3363 # DTB write misses -system.cpu1.dtb.write_acv 49 # DTB write access violations -system.cpu1.dtb.write_accesses 128416 # DTB write accesses -system.cpu1.dtb.data_hits 2094837 # DTB hits -system.cpu1.dtb.data_misses 13661 # DTB misses -system.cpu1.dtb.data_acv 53 # DTB access violations -system.cpu1.dtb.data_accesses 461959 # DTB accesses -system.cpu1.itb.fetch_hits 370005 # ITB hits -system.cpu1.itb.fetch_misses 7545 # ITB misses -system.cpu1.itb.fetch_acv 134 # ITB acv -system.cpu1.itb.fetch_accesses 377550 # ITB accesses +system.cpu1.dtb.read_accesses 331667 # DTB read accesses +system.cpu1.dtb.write_hits 775032 # DTB write hits +system.cpu1.dtb.write_misses 3356 # DTB write misses +system.cpu1.dtb.write_acv 50 # DTB write access violations +system.cpu1.dtb.write_accesses 128144 # DTB write accesses +system.cpu1.dtb.data_hits 2101080 # DTB hits +system.cpu1.dtb.data_misses 13601 # DTB misses +system.cpu1.dtb.data_acv 54 # DTB access violations +system.cpu1.dtb.data_accesses 459811 # DTB accesses +system.cpu1.itb.fetch_hits 367550 # ITB hits +system.cpu1.itb.fetch_misses 7752 # ITB misses +system.cpu1.itb.fetch_acv 129 # ITB acv +system.cpu1.itb.fetch_accesses 375302 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -902,500 +902,500 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 9912659 # number of cpu cycles simulated +system.cpu1.numCycles 9966962 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 1745252 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 1443345 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 65834 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 1584413 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 702878 # Number of BTB hits +system.cpu1.BPredUnit.lookups 1746608 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 1443175 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 66232 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 1579747 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 700902 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 119333 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 5152 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 3326193 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 8368967 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 1745252 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 822211 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 1597560 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 342353 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 3930227 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 24146 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65364 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 47873 # Number of stall cycles due to pending quiesce instructions +system.cpu1.BPredUnit.usedRAS 120007 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 5197 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 3352188 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 8389538 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 1746608 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 820909 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 1600088 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 340649 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 3953742 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 24318 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65300 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 48169 # Number of stall cycles due to pending quiesce instructions system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1048710 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 37506 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 9217508 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.907942 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.250031 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 1052111 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 37387 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 9268453 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.905171 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.248228 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 7619948 82.67% 82.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 115536 1.25% 83.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 231432 2.51% 86.43% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 132066 1.43% 87.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 251396 2.73% 90.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 87805 0.95% 91.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 105965 1.15% 92.69% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 72910 0.79% 93.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 600450 6.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 7668365 82.74% 82.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 115994 1.25% 83.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 231226 2.49% 86.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 132329 1.43% 87.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 251751 2.72% 90.63% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 85931 0.93% 91.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 105894 1.14% 92.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 73622 0.79% 93.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 603341 6.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 9217508 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.176063 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.844271 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 3400940 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 4036286 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1484850 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 73785 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 221646 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 74292 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 4556 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 8102747 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 13778 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 221646 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 3537754 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 421646 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 3194279 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1408453 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 433728 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 7527296 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 85 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 45933 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 92379 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 5035349 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 9221754 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 9169185 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52569 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 3992895 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1042454 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 304748 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 22314 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1288706 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1415531 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 837109 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 144169 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 91214 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 6583258 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 323533 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 6259296 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 22632 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1284449 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 724409 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 248666 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 9217508 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.679066 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.329101 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 9268453 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.175240 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.841735 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 3426888 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 4059985 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1487039 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 74425 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 220115 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 74752 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 4586 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 8123817 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 13801 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 220115 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 3563676 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 426586 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 3211249 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1411283 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 435542 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 7548530 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 102 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 46052 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 92764 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 5048861 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 9245845 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 9192898 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 52947 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 4017246 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1031615 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 305905 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 22528 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1292369 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1416426 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 841512 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 141179 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 90021 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 6602199 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 325316 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 6284355 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 22621 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1273450 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 716539 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 249793 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 9268453 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.678037 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.328780 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 6458729 70.07% 70.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1222372 13.26% 83.33% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 577704 6.27% 89.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 392327 4.26% 93.86% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 292985 3.18% 97.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 159359 1.73% 98.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 73107 0.79% 99.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 30242 0.33% 99.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 10683 0.12% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 6498051 70.11% 70.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1227525 13.24% 83.35% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 582679 6.29% 89.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 391581 4.22% 93.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 294983 3.18% 97.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 158395 1.71% 98.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 72456 0.78% 99.54% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 32178 0.35% 99.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 10605 0.11% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 9217508 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 9268453 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2814 1.95% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 81545 56.44% 58.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 60126 41.61% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2859 1.97% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 82047 56.45% 58.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 60446 41.59% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3976 0.06% 0.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 3873185 61.88% 61.94% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 10062 0.16% 62.10% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10067 0.16% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1988 0.03% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1379075 22.03% 84.33% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 790293 12.63% 96.95% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 190650 3.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3978 0.06% 0.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 3890788 61.91% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 10226 0.16% 62.14% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10071 0.16% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1988 0.03% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1381194 21.98% 84.31% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 794695 12.65% 96.95% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 191415 3.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 6259296 # Type of FU issued -system.cpu1.iq.rate 0.631445 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 144485 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.023083 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 21824812 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 8155075 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 6057514 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 78405 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 38858 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 37639 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 6359227 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 40578 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 60856 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 6284355 # Type of FU issued +system.cpu1.iq.rate 0.630519 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 145352 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.023129 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 21926150 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 8163461 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 6082297 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 78986 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 39141 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 37853 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 6384800 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 40929 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 61528 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 266775 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 6711 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 3171 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 114531 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 262809 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 6760 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1750 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 113415 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 348 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 21986 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 366 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 22210 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 221646 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 305727 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 11882 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 7168806 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 98535 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1415531 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 837109 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 301857 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4025 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4971 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 3171 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 47886 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 59778 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 107664 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 6180810 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1338159 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 78486 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 220115 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 309272 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 12037 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 7192077 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 99271 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1416426 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 841512 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 303434 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 3996 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4977 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1750 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 48213 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 60062 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 108275 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 6205529 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1339876 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 78826 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 262015 # number of nop insts executed -system.cpu1.iew.exec_refs 2115427 # number of memory reference insts executed -system.cpu1.iew.exec_branches 905329 # Number of branches executed -system.cpu1.iew.exec_stores 777268 # Number of stores executed -system.cpu1.iew.exec_rate 0.623527 # Inst execution rate -system.cpu1.iew.wb_sent 6122723 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 6095153 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 2947422 # num instructions producing a value -system.cpu1.iew.wb_consumers 4027218 # num instructions consuming a value +system.cpu1.iew.exec_nop 264562 # number of nop insts executed +system.cpu1.iew.exec_refs 2121617 # number of memory reference insts executed +system.cpu1.iew.exec_branches 906286 # Number of branches executed +system.cpu1.iew.exec_stores 781741 # Number of stores executed +system.cpu1.iew.exec_rate 0.622610 # Inst execution rate +system.cpu1.iew.wb_sent 6147670 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 6120150 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 2958458 # num instructions producing a value +system.cpu1.iew.wb_consumers 4045224 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.614886 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.731875 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.614044 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.731346 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 5779093 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 1316908 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 74867 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 99712 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 8995862 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.642417 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.546372 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 5812223 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 1307029 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 75523 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 100285 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 9048338 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.642353 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.547343 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 6736606 74.89% 74.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1094915 12.17% 87.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 391523 4.35% 91.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 242834 2.70% 94.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 155077 1.72% 95.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 75617 0.84% 96.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 76298 0.85% 97.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 67487 0.75% 98.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 155505 1.73% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 6777327 74.90% 74.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1099919 12.16% 87.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 394591 4.36% 91.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 244546 2.70% 94.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 155405 1.72% 95.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 74689 0.83% 96.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 76341 0.84% 97.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 67787 0.75% 98.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 157733 1.74% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 8995862 # Number of insts commited each cycle -system.cpu1.commit.count 5779093 # Number of instructions committed +system.cpu1.commit.committed_per_cycle::total 9048338 # Number of insts commited each cycle +system.cpu1.commit.count 5812223 # Number of instructions committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 1871334 # Number of memory references committed -system.cpu1.commit.loads 1148756 # Number of loads committed -system.cpu1.commit.membars 20308 # Number of memory barriers committed -system.cpu1.commit.branches 819762 # Number of branches committed -system.cpu1.commit.fp_insts 36255 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 5407958 # Number of committed integer instructions. -system.cpu1.commit.function_calls 88494 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 155505 # number cycles where commit BW limit reached +system.cpu1.commit.refs 1881714 # Number of memory references committed +system.cpu1.commit.loads 1153617 # Number of loads committed +system.cpu1.commit.membars 20508 # Number of memory barriers committed +system.cpu1.commit.branches 821256 # Number of branches committed +system.cpu1.commit.fp_insts 36401 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 5437919 # Number of committed integer instructions. +system.cpu1.commit.function_calls 89388 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 157733 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 15845699 # The number of ROB reads -system.cpu1.rob.rob_writes 14412433 # The number of ROB writes -system.cpu1.timesIdled 81222 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 695151 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.committedInsts 5557862 # Number of Instructions Simulated -system.cpu1.committedInsts_total 5557862 # Number of Instructions Simulated -system.cpu1.cpi 1.783538 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.783538 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.560683 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.560683 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 8056762 # number of integer regfile reads -system.cpu1.int_regfile_writes 4390923 # number of integer regfile writes -system.cpu1.fp_regfile_reads 24497 # number of floating regfile reads -system.cpu1.fp_regfile_writes 23023 # number of floating regfile writes -system.cpu1.misc_regfile_reads 283037 # number of misc regfile reads -system.cpu1.misc_regfile_writes 133939 # number of misc regfile writes -system.cpu1.icache.replacements 109497 # number of replacements -system.cpu1.icache.tagsinuse 452.896457 # Cycle average of tags in use -system.cpu1.icache.total_refs 933398 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 110009 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 8.484742 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1874842259000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 452.896457 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.884563 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 933398 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 933398 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 933398 # number of demand (read+write) hits +system.cpu1.rob.rob_reads 15919184 # The number of ROB reads +system.cpu1.rob.rob_writes 14457399 # The number of ROB writes +system.cpu1.timesIdled 81947 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 698509 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.committedInsts 5588724 # Number of Instructions Simulated +system.cpu1.committedInsts_total 5588724 # Number of Instructions Simulated +system.cpu1.cpi 1.783406 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.783406 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.560725 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.560725 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 8091693 # number of integer regfile reads +system.cpu1.int_regfile_writes 4410635 # number of integer regfile writes +system.cpu1.fp_regfile_reads 24636 # number of floating regfile reads +system.cpu1.fp_regfile_writes 23087 # number of floating regfile writes +system.cpu1.misc_regfile_reads 284786 # number of misc regfile reads +system.cpu1.misc_regfile_writes 134830 # number of misc regfile writes +system.cpu1.icache.replacements 110610 # number of replacements +system.cpu1.icache.tagsinuse 452.934793 # Cycle average of tags in use +system.cpu1.icache.total_refs 935676 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 111121 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 8.420335 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1874818206000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::0 452.934793 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.884638 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::0 935676 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 935676 # number of ReadReq hits +system.cpu1.icache.demand_hits::0 935676 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 933398 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 933398 # number of overall hits +system.cpu1.icache.demand_hits::total 935676 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::0 935676 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 933398 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 115312 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 115312 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 115312 # number of demand (read+write) misses +system.cpu1.icache.overall_hits::total 935676 # number of overall hits +system.cpu1.icache.ReadReq_misses::0 116435 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 116435 # number of ReadReq misses +system.cpu1.icache.demand_misses::0 116435 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 115312 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 115312 # number of overall misses +system.cpu1.icache.demand_misses::total 116435 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::0 116435 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 115312 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 1734763499 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 1734763499 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 1734763499 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 1048710 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1048710 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 1048710 # number of demand (read+write) accesses +system.cpu1.icache.overall_misses::total 116435 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency 1751730499 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency 1751730499 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency 1751730499 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::0 1052111 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1052111 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::0 1052111 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1048710 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 1048710 # number of overall (read+write) accesses +system.cpu1.icache.demand_accesses::total 1052111 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::0 1052111 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1048710 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.109956 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.109956 # miss rate for demand accesses +system.cpu1.icache.overall_accesses::total 1052111 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::0 0.110668 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::0 0.110668 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.109956 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::0 0.110668 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::0 15044.084735 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::0 15044.707339 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::0 15044.084735 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::0 15044.707339 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 15044.084735 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::0 15044.707339 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 115999 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 93999 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6444.388889 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7230.692308 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 32 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits 5233 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits 5233 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 5233 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 110079 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 110079 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 110079 # number of overall MSHR misses +system.cpu1.icache.writebacks 37 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits 5243 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits 5243 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits 5243 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses 111192 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses 111192 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses 111192 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 1320813499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 1320813499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 1320813499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency 1333669999 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 1333669999 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 1333669999 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.104966 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.105685 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::0 0.104966 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::0 0.105685 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0.104966 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::0 0.105685 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11998.778141 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11998.778141 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11998.778141 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11994.298142 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11994.298142 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11994.298142 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 62178 # number of replacements -system.cpu1.dcache.tagsinuse 392.683341 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1692677 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 62506 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 27.080232 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1874637412500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 392.683341 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.766960 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::0 1125457 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1125457 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::0 544800 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 544800 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::0 16569 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 16569 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::0 14697 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 14697 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::0 1670257 # number of demand (read+write) hits +system.cpu1.dcache.replacements 62429 # number of replacements +system.cpu1.dcache.tagsinuse 392.995073 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1698421 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 62755 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 27.064314 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1874613639500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::0 392.995073 # Average occupied blocks per context +system.cpu1.dcache.occ_percent::0 0.767569 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::0 1125916 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1125916 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::0 549554 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 549554 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::0 16796 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 16796 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::0 14923 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 14923 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::0 1675470 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1670257 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::0 1670257 # number of overall hits +system.cpu1.dcache.demand_hits::total 1675470 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::0 1675470 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 1670257 # number of overall hits -system.cpu1.dcache.ReadReq_misses::0 106593 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 106593 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::0 157299 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 157299 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::0 1471 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1471 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::0 688 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 688 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::0 263892 # number of demand (read+write) misses +system.cpu1.dcache.overall_hits::total 1675470 # number of overall hits +system.cpu1.dcache.ReadReq_misses::0 106694 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 106694 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::0 157811 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 157811 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::0 1480 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1480 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::0 700 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 700 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::0 264505 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 263892 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::0 263892 # number of overall misses +system.cpu1.dcache.demand_misses::total 264505 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::0 264505 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 263892 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 1779114500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 5160494262 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency 19390000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency 8230500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency 6939608762 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 6939608762 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::0 1232050 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1232050 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::0 702099 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 702099 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::0 18040 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 18040 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::0 15385 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 15385 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::0 1934149 # number of demand (read+write) accesses +system.cpu1.dcache.overall_misses::total 264505 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency 1790096000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency 5171682833 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency 19414000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency 8395500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency 6961778833 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency 6961778833 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::0 1232610 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1232610 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::0 707365 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 707365 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::0 18276 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 18276 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::0 15623 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 15623 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::0 1939975 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1934149 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 1934149 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1939975 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::0 1939975 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1934149 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.086517 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.224041 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.081541 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.044719 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.136438 # miss rate for demand accesses +system.cpu1.dcache.overall_accesses::total 1939975 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::0 0.086559 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::0 0.223097 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.080981 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.044806 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::0 0.136345 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.136438 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::0 0.136345 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::0 16690.725470 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::0 16777.850676 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::0 32806.910800 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::0 32771.371026 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13181.509177 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13117.567568 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 11962.936047 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 11993.571429 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::0 26297.154753 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::0 26320.027345 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 26297.154753 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::0 26320.027345 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 86924497 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 86579997 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6880 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6823 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12634.374564 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12689.432361 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 35754 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits 63001 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits 133631 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits 299 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits 196632 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 196632 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 43592 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 23668 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses 1172 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses 688 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 67260 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 67260 # number of overall MSHR misses +system.cpu1.dcache.writebacks 35856 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits 62883 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits 134026 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits 295 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits 196909 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits 196909 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses 43811 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses 23785 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses 1185 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses 699 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses 67596 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses 67596 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 554109500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 750522486 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 11597500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 6158000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 1304631986 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 1304631986 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 18620500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 319072500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 337693000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.035382 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_latency 556154000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 752491985 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 11636500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 6289000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 1308645985 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 1308645985 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 19117500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 320801000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency 339918500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.035543 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.033710 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.033625 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.064967 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.064839 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.044719 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.044742 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::0 0.034775 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::0 0.034844 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0.034775 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::0 0.034844 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12711.265829 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 31710.431215 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 9895.477816 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 8950.581395 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 19396.847844 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 19396.847844 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12694.391819 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 31637.249737 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 9819.831224 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 8997.138770 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 19359.813968 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 19359.813968 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -1403,31 +1403,31 @@ system.cpu1.dcache.mshr_cap_events 0 # nu system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6377 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 199477 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 71613 40.63% 40.63% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 237 0.13% 40.76% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1921 1.09% 41.85% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 8 0.00% 41.86% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 102492 58.14% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 176271 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 70248 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.quiesce 6372 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 199307 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 71537 40.62% 40.62% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 237 0.13% 40.75% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1922 1.09% 41.84% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 8 0.00% 41.85% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 102421 58.15% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 176125 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 70172 49.24% 49.24% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 237 0.17% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1921 1.35% 50.76% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1922 1.35% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 8 0.01% 50.76% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 70240 49.24% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 142654 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1858831999000 97.96% 97.96% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 90898500 0.00% 97.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 391654500 0.02% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 4204500 0.00% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 38151374000 2.01% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1897470130500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.980939 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 70164 49.24% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 142503 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1858853057000 97.97% 97.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 90805500 0.00% 97.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 391568500 0.02% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 4023000 0.00% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 38125490000 2.01% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1897464944000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.980919 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.685322 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.685055 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.72% 3.72% # number of syscalls executed system.cpu0.kern.syscall::3 18 8.37% 12.09% # number of syscalls executed system.cpu0.kern.syscall::4 3 1.40% 13.49% # number of syscalls executed @@ -1459,59 +1459,59 @@ system.cpu0.kern.syscall::144 2 0.93% 99.07% # nu system.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 215 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 104 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wripir 105 0.06% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3842 2.08% 2.14% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3840 2.08% 2.14% # number of callpals executed system.cpu0.kern.callpal::tbi 50 0.03% 2.16% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.17% # number of callpals executed -system.cpu0.kern.callpal::swpipl 169337 91.54% 93.71% # number of callpals executed -system.cpu0.kern.callpal::rdps 6360 3.44% 97.14% # number of callpals executed +system.cpu0.kern.callpal::swpipl 169189 91.54% 93.71% # number of callpals executed +system.cpu0.kern.callpal::rdps 6337 3.43% 97.14% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.14% # number of callpals executed system.cpu0.kern.callpal::wrusp 2 0.00% 97.14% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 97.15% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.15% # number of callpals executed -system.cpu0.kern.callpal::rti 4767 2.58% 99.73% # number of callpals executed +system.cpu0.kern.callpal::rti 4768 2.58% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 369 0.20% 99.93% # number of callpals executed system.cpu0.kern.callpal::imb 135 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 184989 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7265 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1246 # number of protection mode switches +system.cpu0.kern.callpal::total 184818 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7264 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1248 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1245 -system.cpu0.kern.mode_good::user 1246 +system.cpu0.kern.mode_good::kernel 1247 +system.cpu0.kern.mode_good::user 1248 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.171370 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.171669 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1895606727500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1863395000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1895604498000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1860438000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3843 # number of times the context was actually changed +system.cpu0.kern.swap_context 3841 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2270 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 38355 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10172 33.29% 33.29% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1920 6.28% 39.57% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 104 0.34% 39.91% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 18361 60.09% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 30557 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10160 45.68% 45.68% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1920 8.63% 54.32% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 104 0.47% 54.78% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10056 45.22% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 22240 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1871109076500 98.61% 98.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 343280000 0.02% 98.63% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 41782500 0.00% 98.63% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 25970941500 1.37% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1897465080500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998820 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2274 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 38564 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 10256 33.36% 33.36% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1920 6.25% 39.61% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 105 0.34% 39.95% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 18460 60.05% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 30741 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 10244 45.72% 45.72% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1920 8.57% 54.28% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 105 0.47% 54.75% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 10139 45.25% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 22408 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1871092276500 98.61% 98.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 343292500 0.02% 98.63% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 42130500 0.00% 98.63% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 25986985000 1.37% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1897464684500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.998830 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.547683 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.549242 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 12 10.81% 10.81% # number of syscalls executed system.cpu1.kern.syscall::4 1 0.90% 11.71% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.01% 20.72% # number of syscalls executed @@ -1531,32 +1531,32 @@ system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu1.kern.callpal::wripir 8 0.03% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 391 1.24% 1.27% # number of callpals executed +system.cpu1.kern.callpal::swpctx 393 1.24% 1.27% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.01% 1.28% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.31% # number of callpals executed -system.cpu1.kern.callpal::swpipl 26005 82.46% 83.77% # number of callpals executed -system.cpu1.kern.callpal::rdps 2390 7.58% 91.35% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.35% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.02% 91.37% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.38% # number of callpals executed -system.cpu1.kern.callpal::rti 2527 8.01% 99.39% # number of callpals executed -system.cpu1.kern.callpal::callsys 146 0.46% 99.85% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 1.30% # number of callpals executed +system.cpu1.kern.callpal::swpipl 26187 82.50% 83.80% # number of callpals executed +system.cpu1.kern.callpal::rdps 2413 7.60% 91.40% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.41% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.02% 91.42% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 91.43% # number of callpals executed +system.cpu1.kern.callpal::rti 2528 7.96% 99.40% # number of callpals executed +system.cpu1.kern.callpal::callsys 146 0.46% 99.86% # number of callpals executed system.cpu1.kern.callpal::imb 45 0.14% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 31535 # number of callpals executed +system.cpu1.kern.callpal::total 31743 # number of callpals executed system.cpu1.kern.mode_switch::kernel 869 # number of protection mode switches system.cpu1.kern.mode_switch::user 492 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2051 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 521 +system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 522 system.cpu1.kern.mode_good::user 492 -system.cpu1.kern.mode_good::idle 29 -system.cpu1.kern.mode_switch_good::kernel 0.599540 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 30 +system.cpu1.kern.mode_switch_good::kernel 0.600690 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.014139 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.613679 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 2030212000 0.11% 0.11% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 852485500 0.04% 0.15% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893908030500 99.85% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 392 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.014606 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.615296 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 2061638000 0.11% 0.11% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 848590000 0.04% 0.15% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893876047000 99.85% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 394 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index a8911f6cc..2cd4054d5 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -10,13 +10,13 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/arm/scratch/sysexplr/dist/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem -pal=/arm/scratch/sysexplr/dist/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -497,7 +497,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -517,7 +517,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/arm/scratch/sysexplr/dist/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -646,7 +646,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index b71599069..636c32218 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/ts gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 16:33:41 -gem5 started Aug 17 2011 16:35:09 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 15:21:47 +gem5 started Aug 20 2011 15:21:55 +gem5 executing on zizzer command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1857897393500 because m5_exit instruction encountered +Exiting @ tick 1858873594500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index c17b9a135..f8131be53 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,94 +1,94 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.857897 # Number of seconds simulated -sim_ticks 1857897393500 # Number of ticks simulated +sim_seconds 1.858874 # Number of seconds simulated +sim_ticks 1858873594500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111366 # Simulator instruction rate (inst/s) -host_tick_rate 3896929552 # Simulator tick rate (ticks/s) -host_mem_usage 340840 # Number of bytes of host memory used -host_seconds 476.76 # Real time elapsed on the host -sim_insts 53094627 # Number of instructions simulated -system.l2c.replacements 391325 # number of replacements -system.l2c.tagsinuse 34942.141711 # Cycle average of tags in use -system.l2c.total_refs 2407783 # Total number of references to valid blocks. -system.l2c.sampled_refs 424213 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.675882 # Average number of references to valid blocks. -system.l2c.warmup_cycle 5611809000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 12320.874417 # Average occupied blocks per context -system.l2c.occ_blocks::1 22621.267294 # Average occupied blocks per context -system.l2c.occ_percent::0 0.188002 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.345173 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1800422 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1800422 # number of ReadReq hits -system.l2c.Writeback_hits::0 834998 # number of Writeback hits -system.l2c.Writeback_hits::total 834998 # number of Writeback hits +host_inst_rate 131543 # Simulator instruction rate (inst/s) +host_tick_rate 4605131786 # Simulator tick rate (ticks/s) +host_mem_usage 295252 # Number of bytes of host memory used +host_seconds 403.65 # Real time elapsed on the host +sim_insts 53097697 # Number of instructions simulated +system.l2c.replacements 391354 # number of replacements +system.l2c.tagsinuse 34898.086140 # Cycle average of tags in use +system.l2c.total_refs 2410581 # Total number of references to valid blocks. +system.l2c.sampled_refs 424231 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.682237 # Average number of references to valid blocks. +system.l2c.warmup_cycle 5619831000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::0 12293.296692 # Average occupied blocks per context +system.l2c.occ_blocks::1 22604.789448 # Average occupied blocks per context +system.l2c.occ_percent::0 0.187581 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.344922 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1801188 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1801188 # number of ReadReq hits +system.l2c.Writeback_hits::0 835090 # number of Writeback hits +system.l2c.Writeback_hits::total 835090 # number of Writeback hits system.l2c.UpgradeReq_hits::0 16 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 16 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::0 2 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 183185 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183185 # number of ReadExReq hits -system.l2c.demand_hits::0 1983607 # number of demand (read+write) hits +system.l2c.ReadExReq_hits::0 183163 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 183163 # number of ReadExReq hits +system.l2c.demand_hits::0 1984351 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1983607 # number of demand (read+write) hits -system.l2c.overall_hits::0 1983607 # number of overall hits +system.l2c.demand_hits::total 1984351 # number of demand (read+write) hits +system.l2c.overall_hits::0 1984351 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1983607 # number of overall hits -system.l2c.ReadReq_misses::0 308136 # number of ReadReq misses -system.l2c.ReadReq_misses::total 308136 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 36 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 36 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 116850 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 116850 # number of ReadExReq misses -system.l2c.demand_misses::0 424986 # number of demand (read+write) misses +system.l2c.overall_hits::total 1984351 # number of overall hits +system.l2c.ReadReq_misses::0 308072 # number of ReadReq misses +system.l2c.ReadReq_misses::total 308072 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 33 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 33 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 116926 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 116926 # number of ReadExReq misses +system.l2c.demand_misses::0 424998 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 424986 # number of demand (read+write) misses -system.l2c.overall_misses::0 424986 # number of overall misses +system.l2c.demand_misses::total 424998 # number of demand (read+write) misses +system.l2c.overall_misses::0 424998 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 424986 # number of overall misses -system.l2c.ReadReq_miss_latency 16038372500 # number of ReadReq miss cycles +system.l2c.overall_misses::total 424998 # number of overall misses +system.l2c.ReadReq_miss_latency 16035098000 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency 425000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6129219000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 22167591500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 22167591500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2108558 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2108558 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 834998 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 834998 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 52 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 52 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_miss_latency 6133668000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 22168766000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 22168766000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2109260 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2109260 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 835090 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 835090 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 49 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 49 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::0 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 300035 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300035 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2408593 # number of demand (read+write) accesses +system.l2c.ReadExReq_accesses::0 300089 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300089 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2409349 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2408593 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2408593 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2409349 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2409349 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2408593 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.146136 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.692308 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.389455 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.176446 # miss rate for demand accesses +system.l2c.overall_accesses::total 2409349 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.146057 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.673469 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.389638 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.176395 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.176446 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.176395 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52049.655022 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::0 52049.838999 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 11805.555556 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 12878.787879 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52453.735558 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52457.691189 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52160.757060 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52162.047821 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52160.757060 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52162.047821 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -99,43 +99,43 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 117715 # number of writebacks +system.l2c.writebacks 117760 # number of writebacks system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 308136 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 36 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 116850 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 424986 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 424986 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 308072 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 33 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 116926 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 424998 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 424998 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12334391000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 1500000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 4708487500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 17042878500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 17042878500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 810033000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1115131998 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 1925164998 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.146136 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12331827500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 1380000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 4711722000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 17043549500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 17043549500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 810479000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1115452498 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 1925931498 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.146057 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.692308 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.673469 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.389455 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.389638 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.176446 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.176395 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.176446 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.176395 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40029.048862 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 41666.666667 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40295.143346 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40102.211602 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40102.211602 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40029.043535 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 41818.181818 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40296.614953 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40102.658130 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40102.658130 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -143,13 +143,13 @@ system.l2c.mshr_cap_events 0 # nu system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.260372 # Cycle average of tags in use +system.iocache.tagsinuse 1.268274 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1708338825000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 1.260372 # Average occupied blocks per context -system.iocache.occ_percent::1 0.078773 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1708338694000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 1.268274 # Average occupied blocks per context +system.iocache.occ_percent::1 0.079267 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits @@ -166,10 +166,10 @@ system.iocache.demand_misses::total 41725 # nu system.iocache.overall_misses::0 0 # number of overall misses system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5722330806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5742268804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5742268804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency 19939998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 5722643806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 5742583804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 5742583804 # number of overall miss cycles system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) @@ -189,22 +189,22 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115260.104046 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137714.930834 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137722.463564 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137621.780803 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137629.330234 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137621.780803 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137629.330234 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64585068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64634068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10462 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10468 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6173.300325 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6174.442874 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -216,10 +216,10 @@ system.iocache.WriteReq_mshr_misses 41552 # nu system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3561477996 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3572419994 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3572419994 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10943998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3561790996 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3572734994 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3572734994 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -233,10 +233,10 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85711.349538 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85618.214356 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85618.214356 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85718.882268 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85625.763787 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85625.763787 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -257,22 +257,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10156439 # DTB read hits -system.cpu.dtb.read_misses 47122 # DTB read misses -system.cpu.dtb.read_acv 587 # DTB read access violations -system.cpu.dtb.read_accesses 977122 # DTB read accesses -system.cpu.dtb.write_hits 6633598 # DTB write hits -system.cpu.dtb.write_misses 11598 # DTB write misses -system.cpu.dtb.write_acv 414 # DTB write access violations -system.cpu.dtb.write_accesses 348122 # DTB write accesses -system.cpu.dtb.data_hits 16790037 # DTB hits -system.cpu.dtb.data_misses 58720 # DTB misses -system.cpu.dtb.data_acv 1001 # DTB access violations -system.cpu.dtb.data_accesses 1325244 # DTB accesses -system.cpu.itb.fetch_hits 1333506 # ITB hits -system.cpu.itb.fetch_misses 39875 # ITB misses -system.cpu.itb.fetch_acv 1125 # ITB acv -system.cpu.itb.fetch_accesses 1373381 # ITB accesses +system.cpu.dtb.read_hits 10138302 # DTB read hits +system.cpu.dtb.read_misses 46569 # DTB read misses +system.cpu.dtb.read_acv 588 # DTB read access violations +system.cpu.dtb.read_accesses 971478 # DTB read accesses +system.cpu.dtb.write_hits 6627002 # DTB write hits +system.cpu.dtb.write_misses 12216 # DTB write misses +system.cpu.dtb.write_acv 416 # DTB write access violations +system.cpu.dtb.write_accesses 347261 # DTB write accesses +system.cpu.dtb.data_hits 16765304 # DTB hits +system.cpu.dtb.data_misses 58785 # DTB misses +system.cpu.dtb.data_acv 1004 # DTB access violations +system.cpu.dtb.data_accesses 1318739 # DTB accesses +system.cpu.itb.fetch_hits 1327158 # ITB hits +system.cpu.itb.fetch_misses 39816 # ITB misses +system.cpu.itb.fetch_acv 1096 # ITB acv +system.cpu.itb.fetch_accesses 1366974 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -285,147 +285,147 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 116343633 # number of cpu cycles simulated +system.cpu.numCycles 116293341 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14429393 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12066685 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 532769 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 13006399 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 6718907 # Number of BTB hits +system.cpu.BPredUnit.lookups 14403200 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12045652 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 530716 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12993662 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 6702662 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 975114 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 45137 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29132882 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 73870037 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14429393 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7694021 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 14329837 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2400358 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 36580859 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32012 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 259840 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 335514 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 170 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9103703 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 330872 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 82240103 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.898224 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.215946 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 972407 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 45058 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29094387 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 73505774 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14403200 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7675069 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 14268794 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2359863 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 36645005 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 31889 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 259043 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 335706 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 129 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9051868 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 321893 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 82174946 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.894503 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.211429 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67910266 82.58% 82.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1028745 1.25% 83.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2026192 2.46% 86.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 969086 1.18% 87.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2957231 3.60% 91.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 692695 0.84% 91.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 793723 0.97% 92.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1070407 1.30% 94.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4791758 5.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67906152 82.64% 82.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1023009 1.24% 83.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2022244 2.46% 86.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 965640 1.18% 87.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2953506 3.59% 91.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 686113 0.83% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 790817 0.96% 92.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1067854 1.30% 94.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4759611 5.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 82240103 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.124024 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.634930 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 30393620 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36243117 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 13115942 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 960226 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1527197 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 611480 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42119 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 72202344 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 128169 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1527197 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 31599738 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12790599 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19770106 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 12256569 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4295892 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 68223425 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6893 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 500375 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1520799 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 45688467 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 82930883 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 82451857 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479026 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38262876 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7425583 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1700626 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 251543 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12011289 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10748783 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7011270 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1273745 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 840870 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 59873388 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2116185 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 58064745 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 115927 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8494287 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4438181 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1448436 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 82240103 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.706039 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.353017 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 82174946 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.123852 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.632072 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 30353273 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36299982 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 13051372 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 972104 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1498214 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 610003 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42096 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 71896046 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 128197 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1498214 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 31555942 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12820674 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19773044 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 12199083 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4327987 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 67967172 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7022 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 504365 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1538985 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 45476353 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 82567749 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 82088652 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479097 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38265070 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 7211275 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1700634 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 251496 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12093975 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10722948 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6992313 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1255970 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 835280 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 59689379 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2116105 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57965210 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 118570 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8314088 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4277616 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1448303 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 82174946 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.705388 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.352124 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56753994 69.01% 69.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11193552 13.61% 82.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5499635 6.69% 89.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3512602 4.27% 93.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2643529 3.21% 96.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1548822 1.88% 98.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 707324 0.86% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 273213 0.33% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 107432 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56717955 69.02% 69.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11192734 13.62% 82.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5489796 6.68% 89.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3501881 4.26% 93.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2637968 3.21% 96.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1562716 1.90% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 689256 0.84% 99.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 274867 0.33% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 107773 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 82240103 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 82174946 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 64991 8.48% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 378109 49.32% 57.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 323577 42.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 67060 8.71% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 379426 49.28% 57.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 323507 42.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39655118 68.29% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 62174 0.11% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39583689 68.29% 68.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 62189 0.11% 68.41% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.46% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.46% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.46% # Type of FU issued @@ -448,112 +448,112 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.46% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.46% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.46% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10635929 18.32% 86.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6722688 11.58% 98.36% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 952312 1.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10615864 18.31% 86.77% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6714571 11.58% 98.36% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 952373 1.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 58064745 # Type of FU issued -system.cpu.iq.rate 0.499080 # Inst issue rate -system.cpu.iq.fu_busy_cnt 766677 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013204 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 198560467 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 70176120 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 56485252 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 691729 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 332805 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 328298 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58461376 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 362765 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 576950 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57965210 # Type of FU issued +system.cpu.iq.rate 0.498440 # Inst issue rate +system.cpu.iq.fu_busy_cnt 769993 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013284 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 198301844 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 69800593 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 56410393 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692084 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 332994 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 328299 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58364794 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 363128 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 575597 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1635037 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13784 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 26178 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 618376 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1608607 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13533 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14401 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 599018 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18266 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 170591 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18904 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 170936 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1527197 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8965647 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 616674 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 65615916 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 866303 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10748783 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 7011270 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1869859 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 484759 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15737 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 26178 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 387398 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 383164 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 770562 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 57355078 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10233934 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 709666 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1498214 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8974617 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 617389 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 65429620 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 865390 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10722948 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6992313 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1869565 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 485054 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15735 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14401 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 385242 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 382803 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 768045 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 57270091 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10215279 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 695118 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3626343 # number of nop insts executed -system.cpu.iew.exec_refs 16894519 # number of memory reference insts executed -system.cpu.iew.exec_branches 9105401 # Number of branches executed -system.cpu.iew.exec_stores 6660585 # Number of stores executed -system.cpu.iew.exec_rate 0.492980 # Inst execution rate -system.cpu.iew.wb_sent 56953037 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56813550 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28082126 # num instructions producing a value -system.cpu.iew.wb_consumers 37827297 # num instructions consuming a value +system.cpu.iew.exec_nop 3624136 # number of nop insts executed +system.cpu.iew.exec_refs 16869985 # number of memory reference insts executed +system.cpu.iew.exec_branches 9097351 # Number of branches executed +system.cpu.iew.exec_stores 6654706 # Number of stores executed +system.cpu.iew.exec_rate 0.492462 # Inst execution rate +system.cpu.iew.wb_sent 56872608 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56738692 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28028831 # num instructions producing a value +system.cpu.iew.wb_consumers 37767423 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.488325 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.742377 # average fanout of values written-back +system.cpu.iew.wb_rate 0.487893 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.742143 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 56289333 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 9199733 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 667749 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 702560 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80712906 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.697402 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.610815 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 56292492 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 9013620 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 667802 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 700532 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 80676732 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.697754 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.611305 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59526212 73.75% 73.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8907000 11.04% 84.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4712189 5.84% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2603041 3.23% 93.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1533921 1.90% 95.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 653559 0.81% 96.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 475046 0.59% 97.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 520427 0.64% 97.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1781511 2.21% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59494729 73.74% 73.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8894659 11.03% 84.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4715834 5.85% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2613071 3.24% 93.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1534221 1.90% 95.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 644957 0.80% 96.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 475888 0.59% 97.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 517029 0.64% 97.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1786344 2.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80712906 # Number of insts commited each cycle -system.cpu.commit.count 56289333 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 80676732 # Number of insts commited each cycle +system.cpu.commit.count 56292492 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15506640 # Number of memory references committed -system.cpu.commit.loads 9113746 # Number of loads committed -system.cpu.commit.membars 227885 # Number of memory barriers committed -system.cpu.commit.branches 8462674 # Number of branches committed +system.cpu.commit.refs 15507636 # Number of memory references committed +system.cpu.commit.loads 9114341 # Number of loads committed +system.cpu.commit.membars 227905 # Number of memory barriers committed +system.cpu.commit.branches 8463183 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52127663 # Number of committed integer instructions. -system.cpu.commit.function_calls 744579 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1781511 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52130666 # Number of committed integer instructions. +system.cpu.commit.function_calls 744656 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1786344 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 144169402 # The number of ROB reads -system.cpu.rob.rob_writes 132508314 # The number of ROB writes -system.cpu.timesIdled 1255085 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34103530 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 53094627 # Number of Instructions Simulated -system.cpu.committedInsts_total 53094627 # Number of Instructions Simulated -system.cpu.cpi 2.191251 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.191251 # CPI: Total CPI of All Threads -system.cpu.ipc 0.456360 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.456360 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 75184837 # number of integer regfile reads -system.cpu.int_regfile_writes 41033576 # number of integer regfile writes -system.cpu.fp_regfile_reads 166484 # number of floating regfile reads -system.cpu.fp_regfile_writes 167413 # number of floating regfile writes -system.cpu.misc_regfile_reads 1996811 # number of misc regfile reads -system.cpu.misc_regfile_writes 949905 # number of misc regfile writes +system.cpu.rob.rob_reads 143945413 # The number of ROB reads +system.cpu.rob.rob_writes 132113260 # The number of ROB writes +system.cpu.timesIdled 1256827 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34118395 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 53097697 # Number of Instructions Simulated +system.cpu.committedInsts_total 53097697 # Number of Instructions Simulated +system.cpu.cpi 2.190177 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.190177 # CPI: Total CPI of All Threads +system.cpu.ipc 0.456584 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.456584 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 75078413 # number of integer regfile reads +system.cpu.int_regfile_writes 40965985 # number of integer regfile writes +system.cpu.fp_regfile_reads 166494 # number of floating regfile reads +system.cpu.fp_regfile_writes 167403 # number of floating regfile writes +system.cpu.misc_regfile_reads 1996876 # number of misc regfile reads +system.cpu.misc_regfile_writes 949968 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -585,231 +585,231 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1004633 # number of replacements -system.cpu.icache.tagsinuse 509.950442 # Cycle average of tags in use -system.cpu.icache.total_refs 8037423 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1005142 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.996306 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 23350341000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 509.950442 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.995997 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 8037424 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8037424 # number of ReadReq hits -system.cpu.icache.demand_hits::0 8037424 # number of demand (read+write) hits +system.cpu.icache.replacements 1004954 # number of replacements +system.cpu.icache.tagsinuse 509.962774 # Cycle average of tags in use +system.cpu.icache.total_refs 7985922 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1005463 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.942532 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 23358245000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 509.962774 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.996021 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 7985923 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7985923 # number of ReadReq hits +system.cpu.icache.demand_hits::0 7985923 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8037424 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 8037424 # number of overall hits +system.cpu.icache.demand_hits::total 7985923 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 7985923 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 8037424 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1066279 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1066279 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1066279 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 7985923 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1065945 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1065945 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1065945 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1066279 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1066279 # number of overall misses +system.cpu.icache.demand_misses::total 1065945 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1065945 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1066279 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15932595494 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15932595494 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15932595494 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 9103703 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9103703 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 9103703 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1065945 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15930410995 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15930410995 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15930410995 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 9051868 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9051868 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 9051868 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9103703 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 9103703 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 9051868 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 9051868 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9103703 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.117126 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.117126 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 9051868 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.117760 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.117760 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.117126 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.117760 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14942.238846 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14944.871447 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14942.238846 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14944.871447 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14942.238846 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14944.871447 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1325996 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 1290996 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 125 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 122 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10607.968000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 10581.934426 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 235 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 60920 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 60920 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 60920 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1005359 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1005359 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1005359 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 60269 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 60269 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 60269 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1005676 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1005676 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1005676 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12047978496 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12047978496 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12047978496 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 12050431496 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12050431496 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12050431496 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110434 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.111101 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.110434 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.111101 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.110434 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.111101 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11983.757539 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11983.757539 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11983.757539 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11982.419284 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11982.419284 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11982.419284 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1402933 # number of replacements -system.cpu.dcache.tagsinuse 511.995988 # Cycle average of tags in use -system.cpu.dcache.total_refs 12110548 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1403445 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.629158 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 19282000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.995988 # Average occupied blocks per context +system.cpu.dcache.replacements 1403374 # number of replacements +system.cpu.dcache.tagsinuse 511.996006 # Cycle average of tags in use +system.cpu.dcache.total_refs 12090411 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1403886 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.612103 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 19221000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 511.996006 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 7476386 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7476386 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 4221734 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4221734 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 192117 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 192117 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 220089 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 220089 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 11698120 # number of demand (read+write) hits +system.cpu.dcache.ReadReq_hits::0 7456106 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7456106 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 4221921 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4221921 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 192075 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 192075 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 220104 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 220104 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 11678027 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11698120 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 11698120 # number of overall hits +system.cpu.dcache.demand_hits::total 11678027 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 11678027 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 11698120 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 1807054 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1807054 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 1935931 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1935931 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 22609 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22609 # number of LoadLockedReq misses +system.cpu.dcache.overall_hits::total 11678027 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 1809770 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1809770 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 1936125 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1936125 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::0 22580 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22580 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::0 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::0 3742985 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 3745895 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3742985 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 3742985 # number of overall misses +system.cpu.dcache.demand_misses::total 3745895 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 3745895 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3742985 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 38901669000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 57798606480 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 338580500 # number of LoadLockedReq miss cycles +system.cpu.dcache.overall_misses::total 3745895 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 38933932500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 57800126852 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 338100500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency 28500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency 96700275480 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 96700275480 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 9283440 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9283440 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 6157665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 214726 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 214726 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 220091 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 220091 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 15441105 # number of demand (read+write) accesses +system.cpu.dcache.demand_miss_latency 96734059352 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 96734059352 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 9265876 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9265876 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 6158046 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6158046 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 214655 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 214655 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 220106 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 220106 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 15423922 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15441105 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 15441105 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 15423922 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 15423922 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15441105 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.194653 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.314394 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.105292 # miss rate for LoadLockedReq accesses +system.cpu.dcache.overall_accesses::total 15423922 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.195316 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.314406 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.105192 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::0 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::0 0.242404 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::0 0.242863 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.242404 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.242863 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 21527.673772 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 21513.193665 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 29855.716180 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 29853.509898 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14975.474369 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14973.449956 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14250 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 25835.068930 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 25824.017852 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 25835.068930 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 25824.017852 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 919195309 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 917367309 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 193500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 102335 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 103073 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8982.218293 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8900.170840 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 24187.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 834763 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 719698 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1637137 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 5136 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2356835 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2356835 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1087356 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 298794 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 17473 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks 834855 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 722036 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1637277 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 5104 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2359313 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2359313 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1087734 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 298848 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 17476 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1386150 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1386150 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 1386582 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1386582 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24800644000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8504282309 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 206126500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 24802725500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8508331309 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 206132500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 33304926309 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 33304926309 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904508000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234433998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 2138941998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117129 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency 33311056809 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 33311056809 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 905005000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234795498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 2139800498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117391 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048524 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048530 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081373 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081414 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.089770 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.089898 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.089770 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.089898 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22808.210007 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28462.025037 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11796.858010 # average LoadLockedReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22802.197504 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28470.430818 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11795.176242 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24026.928045 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24026.928045 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 24023.863579 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 24023.863579 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -817,27 +817,27 @@ system.cpu.dcache.mshr_cap_events 0 # nu system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6435 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211583 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74879 40.96% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 243 0.13% 41.09% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1881 1.03% 42.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105809 57.88% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182812 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73512 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 243 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1881 1.26% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73515 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.inst.quiesce 6436 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211595 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74877 40.96% 40.96% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 245 0.13% 41.09% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1882 1.03% 42.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105819 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182823 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73510 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 245 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1882 1.26% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73514 49.29% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149151 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1819252477000 97.92% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 94027000 0.01% 97.93% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 384302500 0.02% 97.95% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 38165726500 2.05% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1857896533000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981744 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_ticks::0 1820223133000 97.92% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 94250000 0.01% 97.93% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 384615500 0.02% 97.95% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 38170735500 2.05% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1858872734000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981743 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694790 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694715 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -876,29 +876,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175475 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6786 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175482 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6787 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5215 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5217 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192432 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5954 # number of protection mode switches +system.cpu.kern.callpal::total 192442 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5953 # number of protection mode switches system.cpu.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2103 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2106 # number of protection mode switches system.cpu.kern.mode_good::kernel 1907 system.cpu.kern.mode_good::user 1737 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.320289 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320343 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080837 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.401126 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29181178000 1.57% 1.57% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2689752000 0.14% 1.72% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1826025595000 98.28% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080722 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.401064 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29154617000 1.57% 1.57% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2680769000 0.14% 1.71% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827037340000 98.29% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 4580778bd..3a986614c 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -9,13 +9,13 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver boot_cpu_frequency=500 -boot_loader=/chips/pd/randd/dist/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -63,7 +63,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu0] diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 523f8a126..04178bb32 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -13,7 +13,6 @@ warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index dcb3e878e..eb8b03237 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual/simout +Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 18 2011 16:54:46 -gem5 started Aug 18 2011 17:16:56 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 20 2011 15:41:18 +gem5 started Aug 20 2011 15:46:02 +gem5 executing on zizzer command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2582677547500 because m5_exit instruction encountered +Exiting @ tick 2582520130500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index a5d979727..b36a36f09 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.582678 # Number of seconds simulated -sim_ticks 2582677547500 # Number of ticks simulated +sim_seconds 2.582520 # Number of seconds simulated +sim_ticks 2582520130500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75295 # Simulator instruction rate (inst/s) -host_tick_rate 2435818565 # Simulator tick rate (ticks/s) -host_mem_usage 423776 # Number of bytes of host memory used -host_seconds 1060.29 # Real time elapsed on the host -sim_insts 79834358 # Number of instructions simulated -system.l2c.replacements 130785 # number of replacements -system.l2c.tagsinuse 27318.484309 # Cycle average of tags in use -system.l2c.total_refs 1826531 # Total number of references to valid blocks. -system.l2c.sampled_refs 161304 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.323532 # Average number of references to valid blocks. +host_inst_rate 84908 # Simulator instruction rate (inst/s) +host_tick_rate 2745493933 # Simulator tick rate (ticks/s) +host_mem_usage 385348 # Number of bytes of host memory used +host_seconds 940.64 # Real time elapsed on the host +sim_insts 79867485 # Number of instructions simulated +system.l2c.replacements 132224 # number of replacements +system.l2c.tagsinuse 27582.981749 # Cycle average of tags in use +system.l2c.total_refs 1821382 # Total number of references to valid blocks. +system.l2c.sampled_refs 162180 # Sample count of references to valid blocks. +system.l2c.avg_refs 11.230620 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 5406.863178 # Average occupied blocks per context -system.l2c.occ_blocks::1 6677.424533 # Average occupied blocks per context -system.l2c.occ_blocks::2 15234.196598 # Average occupied blocks per context -system.l2c.occ_percent::0 0.082502 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.101889 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.232455 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 803697 # number of ReadReq hits -system.l2c.ReadReq_hits::1 562068 # number of ReadReq hits -system.l2c.ReadReq_hits::2 188134 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1553899 # number of ReadReq hits -system.l2c.Writeback_hits::0 603483 # number of Writeback hits -system.l2c.Writeback_hits::total 603483 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 1202 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 810 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2012 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 219 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 351 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 570 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 63626 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 37284 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 100910 # number of ReadExReq hits -system.l2c.demand_hits::0 867323 # number of demand (read+write) hits -system.l2c.demand_hits::1 599352 # number of demand (read+write) hits -system.l2c.demand_hits::2 188134 # number of demand (read+write) hits -system.l2c.demand_hits::total 1654809 # number of demand (read+write) hits -system.l2c.overall_hits::0 867323 # number of overall hits -system.l2c.overall_hits::1 599352 # number of overall hits -system.l2c.overall_hits::2 188134 # number of overall hits -system.l2c.overall_hits::total 1654809 # number of overall hits -system.l2c.ReadReq_misses::0 22876 # number of ReadReq misses -system.l2c.ReadReq_misses::1 16980 # number of ReadReq misses -system.l2c.ReadReq_misses::2 159 # number of ReadReq misses -system.l2c.ReadReq_misses::total 40015 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 6837 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 3470 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 10307 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::0 768 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 499 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1267 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 99026 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 49105 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 148131 # number of ReadExReq misses -system.l2c.demand_misses::0 121902 # number of demand (read+write) misses -system.l2c.demand_misses::1 66085 # number of demand (read+write) misses -system.l2c.demand_misses::2 159 # number of demand (read+write) misses -system.l2c.demand_misses::total 188146 # number of demand (read+write) misses -system.l2c.overall_misses::0 121902 # number of overall misses -system.l2c.overall_misses::1 66085 # number of overall misses -system.l2c.overall_misses::2 159 # number of overall misses -system.l2c.overall_misses::total 188146 # number of overall misses -system.l2c.ReadReq_miss_latency 2090784500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 57155000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency 7364000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7771362499 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 9862146999 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 9862146999 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 826573 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 579048 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 188293 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1593914 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 603483 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 603483 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 8039 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 4280 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 12319 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 987 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 850 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1837 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 162652 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 86389 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 249041 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 989225 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 665437 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 188293 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1842955 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 989225 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 665437 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 188293 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1842955 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.027676 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.029324 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.000844 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.057844 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.850479 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.810748 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.778116 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.587059 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.608821 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.568417 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.123230 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.099311 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.000844 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.223385 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.123230 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.099311 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.000844 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.223385 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 91396.419829 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 123132.184923 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 13149588.050314 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 13364116.655067 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 8359.660670 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 16471.181556 # average UpgradeReq miss latency +system.l2c.occ_blocks::0 5000.765535 # Average occupied blocks per context +system.l2c.occ_blocks::1 7177.119061 # Average occupied blocks per context +system.l2c.occ_blocks::2 15405.097153 # Average occupied blocks per context +system.l2c.occ_percent::0 0.076306 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.109514 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.235063 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 739666 # number of ReadReq hits +system.l2c.ReadReq_hits::1 629011 # number of ReadReq hits +system.l2c.ReadReq_hits::2 183263 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1551940 # number of ReadReq hits +system.l2c.Writeback_hits::0 599118 # number of Writeback hits +system.l2c.Writeback_hits::total 599118 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 1040 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 1060 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2100 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 181 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 449 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 630 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 58369 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 39072 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 97441 # number of ReadExReq hits +system.l2c.demand_hits::0 798035 # number of demand (read+write) hits +system.l2c.demand_hits::1 668083 # number of demand (read+write) hits +system.l2c.demand_hits::2 183263 # number of demand (read+write) hits +system.l2c.demand_hits::total 1649381 # number of demand (read+write) hits +system.l2c.overall_hits::0 798035 # number of overall hits +system.l2c.overall_hits::1 668083 # number of overall hits +system.l2c.overall_hits::2 183263 # number of overall hits +system.l2c.overall_hits::total 1649381 # number of overall hits +system.l2c.ReadReq_misses::0 19689 # number of ReadReq misses +system.l2c.ReadReq_misses::1 20600 # number of ReadReq misses +system.l2c.ReadReq_misses::2 170 # number of ReadReq misses +system.l2c.ReadReq_misses::total 40459 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 7392 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 3836 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11228 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::0 864 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 461 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1325 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 98007 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 50222 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 148229 # number of ReadExReq misses +system.l2c.demand_misses::0 117696 # number of demand (read+write) misses +system.l2c.demand_misses::1 70822 # number of demand (read+write) misses +system.l2c.demand_misses::2 170 # number of demand (read+write) misses +system.l2c.demand_misses::total 188688 # number of demand (read+write) misses +system.l2c.overall_misses::0 117696 # number of overall misses +system.l2c.overall_misses::1 70822 # number of overall misses +system.l2c.overall_misses::2 170 # number of overall misses +system.l2c.overall_misses::total 188688 # number of overall misses +system.l2c.ReadReq_miss_latency 2113875000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 61547500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency 8091500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7780940999 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 9894815999 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 9894815999 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 759355 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 649611 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 183433 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1592399 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 599118 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 599118 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 8432 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 4896 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 13328 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 1045 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 910 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1955 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 156376 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 89294 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 245670 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 915731 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 738905 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 183433 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1838069 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 915731 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 738905 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 183433 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1838069 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.025929 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.031711 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.000927 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.058567 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.876660 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.783497 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.826794 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.506593 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.626739 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.562434 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.128527 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.095847 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.000927 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.225301 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.128527 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.095847 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.000927 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.225301 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 107363.248514 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 102615.291262 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 12434558.823529 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 12644537.363306 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 8326.231061 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 16044.708029 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 9588.541667 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 14757.515030 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::0 9365.162037 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 17552.060738 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 78478.000717 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 158260.105875 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 79391.686298 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 154930.926666 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 80902.257543 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 149234.274026 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 62026081.754717 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 62256218.286286 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 80902.257543 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 149234.274026 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 62026081.754717 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 62256218.286286 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 84070.962471 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 139713.874206 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 58204799.994118 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 58428584.830795 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 84070.962471 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 139713.874206 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 58204799.994118 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 58428584.830795 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -143,56 +143,56 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 111655 # number of writebacks -system.l2c.ReadReq_mshr_hits 99 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 99 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 99 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 39916 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 10307 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 1267 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 148131 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 188047 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 188047 # number of overall MSHR misses +system.l2c.writebacks 112853 # number of writebacks +system.l2c.ReadReq_mshr_hits 94 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits 94 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 94 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 40365 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 11228 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses 1325 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 148229 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 188594 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 188594 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 1599541500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 412620000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 50764500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5935595999 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 7535137499 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 7535137499 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 131969781000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 32516901535 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 164486682535 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.048291 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.068934 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 0.211989 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.329214 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 1.282125 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 2.408178 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 1617473000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 449580000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency 53034500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5939516999 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 7556989999 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 7556989999 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 131965465500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 32542103084 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 164507568584 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.053157 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.062137 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 0.220053 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.335347 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1.331594 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 2.293301 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.283688 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.490588 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.267943 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.456044 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.910724 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 1.714697 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.947901 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 1.660011 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.190095 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0.282592 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 0.998694 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.471381 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.190095 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0.282592 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 0.998694 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.471381 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40072.690149 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40032.987290 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40066.692976 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40069.911085 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40070.500986 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40070.500986 # average overall mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.205949 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0.255234 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 1.028136 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.489319 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.205949 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0.255234 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 1.028136 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.489319 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40071.175523 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40040.969006 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40026.037736 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40069.871611 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40070.150689 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40070.150689 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -207,27 +207,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 41192849 # DTB read hits -system.cpu0.dtb.read_misses 63693 # DTB read misses -system.cpu0.dtb.write_hits 7450240 # DTB write hits -system.cpu0.dtb.write_misses 14279 # DTB write misses +system.cpu0.dtb.read_hits 42414340 # DTB read hits +system.cpu0.dtb.read_misses 56223 # DTB read misses +system.cpu0.dtb.write_hits 6898086 # DTB write hits +system.cpu0.dtb.write_misses 11305 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2696 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 5912 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 640 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2713 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 11513 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 590 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 1671 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 41256542 # DTB read accesses -system.cpu0.dtb.write_accesses 7464519 # DTB write accesses +system.cpu0.dtb.perms_faults 1641 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 42470563 # DTB read accesses +system.cpu0.dtb.write_accesses 6909391 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 48643089 # DTB hits -system.cpu0.dtb.misses 77972 # DTB misses -system.cpu0.dtb.accesses 48721061 # DTB accesses -system.cpu0.itb.inst_hits 7154156 # ITB inst hits -system.cpu0.itb.inst_misses 18344 # ITB inst misses +system.cpu0.dtb.hits 49312426 # DTB hits +system.cpu0.dtb.misses 67528 # DTB misses +system.cpu0.dtb.accesses 49379954 # DTB accesses +system.cpu0.itb.inst_hits 6438737 # ITB inst hits +system.cpu0.itb.inst_misses 18334 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -236,520 +236,516 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1605 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1587 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 6284 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 6092 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 7172500 # ITB inst accesses -system.cpu0.itb.hits 7154156 # DTB hits -system.cpu0.itb.misses 18344 # DTB misses -system.cpu0.itb.accesses 7172500 # DTB accesses -system.cpu0.numCycles 357540967 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6457071 # ITB inst accesses +system.cpu0.itb.hits 6438737 # DTB hits +system.cpu0.itb.misses 18334 # DTB misses +system.cpu0.itb.accesses 6457071 # DTB accesses +system.cpu0.numCycles 352502516 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 9593725 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 7120843 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 688397 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 8086863 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5605356 # Number of BTB hits +system.cpu0.BPredUnit.lookups 8652992 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 6404778 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 637693 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 7363134 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5053345 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 917445 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 151480 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 18599757 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 50204356 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 9593725 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6522801 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12725278 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3026243 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 114823 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 80197472 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1938 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 119675 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 131982 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 222 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7147681 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 329179 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 9806 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 114004183 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.572281 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.836691 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 807352 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 136692 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 16884109 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 45966993 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 8652992 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5860697 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11522341 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2668103 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 112168 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 79167270 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 2014 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 119305 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 115037 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 246 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6432455 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 291981 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 9711 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 109779148 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.541337 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.795461 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 101298717 88.86% 88.86% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 1249230 1.10% 89.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1702654 1.49% 91.44% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1440887 1.26% 92.71% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1218688 1.07% 93.78% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 996216 0.87% 94.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 913152 0.80% 95.45% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 546684 0.48% 95.93% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4637955 4.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 98275003 89.52% 89.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 1141137 1.04% 90.56% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1489424 1.36% 91.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1304085 1.19% 93.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1112037 1.01% 94.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 879763 0.80% 94.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 783842 0.71% 95.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 505631 0.46% 96.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4288226 3.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 114004183 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.026833 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.140416 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 19798941 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 79925582 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 11493306 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 769981 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2016373 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1516743 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 98250 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62465027 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 321354 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 2016373 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 20942863 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 33418227 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 41890543 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 11135381 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4600796 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 59851687 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1820 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 622371 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 3206696 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 196 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 60092077 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 271645522 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 271595503 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 50019 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 44620651 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 15471425 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 873594 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 797183 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8821523 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 12757061 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 8422181 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1717649 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1992572 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 55833489 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1355727 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 82528607 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 169777 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11480759 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 26808481 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 257868 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 114004183 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.723909 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.428339 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 109779148 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.024547 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.130402 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 18050945 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 78849390 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10366657 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 743574 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1768582 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1352275 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 89418 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56923097 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 298418 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1768582 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 19113011 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 33326039 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 41047359 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10060323 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4463834 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 54560689 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1472 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 580904 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 3150021 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 227 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 54846534 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 247844774 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 247794895 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 49879 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 41443860 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13402673 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 827250 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 762254 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8494444 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 11787351 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 7696820 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1444181 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1562010 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 51022975 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1296408 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 80307756 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 139273 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9946263 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 22977035 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 252908 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 109779148 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.731539 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.440195 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 83031906 72.83% 72.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10859028 9.53% 82.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4622462 4.05% 86.41% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3473838 3.05% 89.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 9590269 8.41% 97.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1336341 1.17% 99.04% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 758222 0.67% 99.71% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 245908 0.22% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 86209 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 80155628 73.02% 73.02% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10112206 9.21% 82.23% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4137187 3.77% 86.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3171994 2.89% 88.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 9961890 9.07% 97.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1265964 1.15% 99.11% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 671041 0.61% 99.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 224336 0.20% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 78902 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 114004183 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 109779148 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 40984 0.54% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 430 0.01% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 7316558 95.62% 96.16% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 293687 3.84% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 37945 0.47% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 630 0.01% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 7705227 95.96% 96.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 285473 3.56% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 88545 0.11% 0.11% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 32461139 39.33% 39.44% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 66584 0.08% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 5 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1699 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 41999048 50.89% 90.41% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 7911577 9.59% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 88461 0.11% 0.11% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29747563 37.04% 37.15% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 62367 0.08% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 5 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 4 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1707 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 43146000 53.73% 90.96% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 7261641 9.04% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 82528607 # Type of FU issued -system.cpu0.iq.rate 0.230823 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 7651659 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.092715 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 286948190 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 68723133 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50664328 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11541 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 7288 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5232 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 90085763 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 5958 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 417346 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 80307756 # Type of FU issued +system.cpu0.iq.rate 0.227822 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 8029275 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.099981 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 278618763 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 62278383 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 46688761 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11606 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 7153 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5243 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 88242529 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6041 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 399833 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2922980 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 6316 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 61885 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1142353 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2542386 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 5153 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 20600 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1003035 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 30234184 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 13064 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 32220164 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 13264 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2016373 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 25967321 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 376582 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 57371840 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 294662 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 12757061 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 8422181 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 894783 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 65983 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 6042 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 61885 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 548006 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 156688 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 704694 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 81662256 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 41659868 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 866351 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1768582 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 25955516 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 355771 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 52493661 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 246498 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 11787351 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 7696820 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 864266 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 62537 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5227 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 20600 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 509776 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 136927 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 646703 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 79579333 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 42855337 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 728423 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 182624 # number of nop insts executed -system.cpu0.iew.exec_refs 49452351 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7085446 # Number of branches executed -system.cpu0.iew.exec_stores 7792483 # Number of stores executed -system.cpu0.iew.exec_rate 0.228400 # Inst execution rate -system.cpu0.iew.wb_sent 81169545 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 50669560 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26746507 # num instructions producing a value -system.cpu0.iew.wb_consumers 50218305 # num instructions consuming a value +system.cpu0.iew.exec_nop 174278 # number of nop insts executed +system.cpu0.iew.exec_refs 50025973 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6436853 # Number of branches executed +system.cpu0.iew.exec_stores 7170636 # Number of stores executed +system.cpu0.iew.exec_rate 0.225755 # Inst execution rate +system.cpu0.iew.wb_sent 79157088 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 46694004 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24804627 # num instructions producing a value +system.cpu0.iew.wb_consumers 46107956 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.141717 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.532605 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.132464 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.537968 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 45235360 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 11991795 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1097859 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 616755 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 112037138 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.403753 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.265449 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 41930270 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 10408005 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1043500 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 570177 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 108054182 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.388049 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.248702 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 93611832 83.55% 83.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 10012247 8.94% 92.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2707975 2.42% 94.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1499111 1.34% 96.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1132088 1.01% 97.26% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 700448 0.63% 97.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 719513 0.64% 98.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 269232 0.24% 98.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1384692 1.24% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 91026362 84.24% 84.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 9315133 8.62% 92.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2453841 2.27% 95.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1345650 1.25% 96.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1029771 0.95% 97.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 653477 0.60% 97.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 658529 0.61% 98.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 238490 0.22% 98.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1332929 1.23% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 112037138 # Number of insts commited each cycle -system.cpu0.commit.count 45235360 # Number of instructions committed +system.cpu0.commit.committed_per_cycle::total 108054182 # Number of insts commited each cycle +system.cpu0.commit.count 41930270 # Number of instructions committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 17113909 # Number of memory references committed -system.cpu0.commit.loads 9834081 # Number of loads committed -system.cpu0.commit.membars 304797 # Number of memory barriers committed -system.cpu0.commit.branches 6085015 # Number of branches committed -system.cpu0.commit.fp_insts 4916 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 40053285 # Number of committed integer instructions. -system.cpu0.commit.function_calls 683094 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1384692 # number cycles where commit BW limit reached +system.cpu0.commit.refs 15938750 # Number of memory references committed +system.cpu0.commit.loads 9244965 # Number of loads committed +system.cpu0.commit.membars 288660 # Number of memory barriers committed +system.cpu0.commit.branches 5543054 # Number of branches committed +system.cpu0.commit.fp_insts 4980 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 37176133 # Number of committed integer instructions. +system.cpu0.commit.function_calls 620334 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1332929 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 166715497 # The number of ROB reads -system.cpu0.rob.rob_writes 116483375 # The number of ROB writes -system.cpu0.timesIdled 1500698 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 243536784 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 45109533 # Number of Instructions Simulated -system.cpu0.committedInsts_total 45109533 # Number of Instructions Simulated -system.cpu0.cpi 7.926062 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.926062 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.126166 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.126166 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 365152407 # number of integer regfile reads -system.cpu0.int_regfile_writes 50032906 # number of integer regfile writes -system.cpu0.fp_regfile_reads 4200 # number of floating regfile reads +system.cpu0.rob.rob_reads 157975997 # The number of ROB reads +system.cpu0.rob.rob_writes 106454954 # The number of ROB writes +system.cpu0.timesIdled 1454281 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 242723368 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 41804443 # Number of Instructions Simulated +system.cpu0.committedInsts_total 41804443 # Number of Instructions Simulated +system.cpu0.cpi 8.432178 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.432178 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.118593 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.118593 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 354304839 # number of integer regfile reads +system.cpu0.int_regfile_writes 46156049 # number of integer regfile writes +system.cpu0.fp_regfile_reads 4230 # number of floating regfile reads system.cpu0.fp_regfile_writes 1342 # number of floating regfile writes -system.cpu0.misc_regfile_reads 71323581 # number of misc regfile reads -system.cpu0.misc_regfile_writes 671757 # number of misc regfile writes -system.cpu0.icache.replacements 594199 # number of replacements -system.cpu0.icache.tagsinuse 511.628418 # Cycle average of tags in use -system.cpu0.icache.total_refs 6500767 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 594711 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 10.930968 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6436890000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 511.628418 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.999274 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 6500767 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6500767 # number of ReadReq hits -system.cpu0.icache.demand_hits::0 6500767 # number of demand (read+write) hits +system.cpu0.misc_regfile_reads 65708495 # number of misc regfile reads +system.cpu0.misc_regfile_writes 636034 # number of misc regfile writes +system.cpu0.icache.replacements 540132 # number of replacements +system.cpu0.icache.tagsinuse 511.623908 # Cycle average of tags in use +system.cpu0.icache.total_refs 5846805 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 540644 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 10.814519 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 16020223000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::0 511.623908 # Average occupied blocks per context +system.cpu0.icache.occ_percent::0 0.999265 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::0 5846805 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5846805 # number of ReadReq hits +system.cpu0.icache.demand_hits::0 5846805 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6500767 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::0 6500767 # number of overall hits +system.cpu0.icache.demand_hits::total 5846805 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::0 5846805 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 6500767 # number of overall hits -system.cpu0.icache.ReadReq_misses::0 646785 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 646785 # number of ReadReq misses -system.cpu0.icache.demand_misses::0 646785 # number of demand (read+write) misses +system.cpu0.icache.overall_hits::total 5846805 # number of overall hits +system.cpu0.icache.ReadReq_misses::0 585522 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 585522 # number of ReadReq misses +system.cpu0.icache.demand_misses::0 585522 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 646785 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::0 646785 # number of overall misses +system.cpu0.icache.demand_misses::total 585522 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::0 585522 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 646785 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 9658555994 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 9658555994 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 9658555994 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::0 7147552 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7147552 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::0 7147552 # number of demand (read+write) accesses +system.cpu0.icache.overall_misses::total 585522 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency 8762208993 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency 8762208993 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency 8762208993 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::0 6432327 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6432327 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::0 6432327 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7147552 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::0 7147552 # number of overall (read+write) accesses +system.cpu0.icache.demand_accesses::total 6432327 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::0 6432327 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7147552 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::0 0.090490 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::0 0.090490 # miss rate for demand accesses +system.cpu0.icache.overall_accesses::total 6432327 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::0 0.091028 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::0 0.091028 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.090490 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::0 0.091028 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::0 14933.178713 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::0 14964.781841 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::0 14933.178713 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::0 14964.781841 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 14933.178713 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::0 14964.781841 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1667497 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 1480495 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 224 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 196 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 7444.183036 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 7553.545918 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 31555 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits 52053 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits 52053 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 52053 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 594732 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 594732 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 594732 # number of overall MSHR misses +system.cpu0.icache.writebacks 29912 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits 44859 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits 44859 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits 44859 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses 540663 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses 540663 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses 540663 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 7219185997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 7219185997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 7219185997 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency 6562850995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 6562850995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 6562850995 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency 6685500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency 6685500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.083208 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.084054 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::0 0.083208 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::0 0.084054 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::0 0.083208 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::0 0.084054 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12138.553158 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 12138.553158 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 12138.553158 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12138.524358 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 12138.524358 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12138.524358 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency inf # 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Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 49147000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 486.484981 # Average occupied blocks per context -system.cpu0.dcache.occ_blocks::1 -2.900311 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.950166 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::1 -0.005665 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::0 8695002 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 8695002 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::0 4786521 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4786521 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::0 223142 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 223142 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::0 209904 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 209904 # 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number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::0 9176331 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 9176331 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::0 6719933 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6719933 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::0 233370 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 233370 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::0 217289 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 217289 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::0 15896264 # number of demand (read+write) accesses +system.cpu0.dcache.overall_misses::total 2327028 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency 6461559500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency 70508741836 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency 120808500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency 88519000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency 76970301336 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency 76970301336 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::0 8432454 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8432454 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::0 6211805 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6211805 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::0 231294 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 231294 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::0 207540 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 207540 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::0 14644259 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15896264 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::0 15896264 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14644259 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::0 14644259 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15896264 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::0 0.052453 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.287713 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.043827 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.033987 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.151906 # miss rate for demand accesses +system.cpu0.dcache.overall_accesses::total 14644259 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::0 0.054957 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::0 0.300010 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.043071 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.037487 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::0 0.158904 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.151906 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::0 0.158904 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::0 14192.370499 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::0 13943.113527 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::0 37123.492735 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::0 37834.595763 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 12273.856081 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 12126.932343 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 11072.985782 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 11377.763496 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::0 32552.644708 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::0 33076.654572 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 32552.644708 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::0 33076.654572 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 7515481 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2368000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 844 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 131 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8904.598341 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 18076.335878 # average number of cycles each access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 6713488 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1808000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 859 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 123 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7815.469150 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 14699.186992 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 345751 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits 230083 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits 1750706 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits 435 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits 1980789 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 1980789 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 251246 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 182706 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses 9793 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses 7384 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 433952 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 433952 # number of overall MSHR misses +system.cpu0.dcache.writebacks 327128 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits 223214 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits 1685177 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits 329 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits 1908391 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits 1908391 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses 240209 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses 178428 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses 9633 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses 7778 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses 418637 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses 418637 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 3167466500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 6457872480 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 89563500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 59583000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 9625338980 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 9625338980 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 139101280000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1100636486 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 140201916486 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.027380 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency 2943893000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency 6377983487 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 86869500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 65155000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 9321876487 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 9321876487 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 138959490000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1038770484 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency 139998260484 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.028486 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.027189 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.028724 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.041963 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.041648 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.033982 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.037477 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::0 0.027299 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::0 0.028587 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0.027299 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::0 0.028587 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12607.032550 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 35345.705560 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 9145.665271 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 8069.203684 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 22180.653575 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 22180.653575 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12255.548293 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 35745.418247 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 9017.907194 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 8376.832091 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 22267.206403 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 22267.206403 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -758,27 +754,27 @@ system.cpu0.dcache.soft_prefetch_mshr_full 0 # system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 9398153 # DTB read hits -system.cpu1.dtb.read_misses 34944 # DTB read misses -system.cpu1.dtb.write_hits 4980209 # DTB write hits -system.cpu1.dtb.write_misses 12567 # DTB write misses +system.cpu1.dtb.read_hits 10576986 # DTB read hits +system.cpu1.dtb.read_misses 41991 # DTB read misses +system.cpu1.dtb.write_hits 5532460 # DTB write hits +system.cpu1.dtb.write_misses 15559 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1914 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 7467 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 271 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1928 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 5132 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 260 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 777 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 9433097 # DTB read accesses -system.cpu1.dtb.write_accesses 4992776 # DTB write accesses +system.cpu1.dtb.perms_faults 787 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10618977 # DTB read accesses +system.cpu1.dtb.write_accesses 5548019 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14378362 # DTB hits -system.cpu1.dtb.misses 47511 # DTB misses -system.cpu1.dtb.accesses 14425873 # DTB accesses -system.cpu1.itb.inst_hits 7673879 # ITB inst hits -system.cpu1.itb.inst_misses 3663 # ITB inst misses +system.cpu1.dtb.hits 16109446 # DTB hits +system.cpu1.dtb.misses 57550 # DTB misses +system.cpu1.dtb.accesses 16166996 # DTB accesses +system.cpu1.itb.inst_hits 8208666 # ITB inst hits +system.cpu1.itb.inst_misses 3757 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -787,520 +783,516 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1371 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1369 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 2297 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 2255 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7677542 # ITB inst accesses -system.cpu1.itb.hits 7673879 # DTB hits -system.cpu1.itb.misses 3663 # DTB misses -system.cpu1.itb.accesses 7677542 # DTB accesses -system.cpu1.numCycles 64448888 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8212423 # ITB inst accesses +system.cpu1.itb.hits 8208666 # DTB hits +system.cpu1.itb.misses 3757 # DTB misses +system.cpu1.itb.accesses 8212423 # DTB accesses +system.cpu1.numCycles 69081256 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 7492397 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 6087986 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 429995 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 6556371 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5183364 # Number of BTB hits +system.cpu1.BPredUnit.lookups 8330796 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 6738871 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 503522 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 7267639 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5704343 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 581252 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 90679 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 16050492 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 59173184 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7492397 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5764616 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 12912375 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4437648 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 50354 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 14454862 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 2217 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 33931 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 110303 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 194 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7671208 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 720838 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2326 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 46632146 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.521202 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.768696 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 683793 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 107847 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 17620797 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 62561411 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8330796 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6388136 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13917594 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4639299 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 49548 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 15790396 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 3022 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 34407 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 125274 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 237 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8206050 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 760093 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2394 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 50674659 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.494403 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.744832 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 33727851 72.33% 72.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 606934 1.30% 73.63% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1038343 2.23% 75.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2380602 5.11% 80.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1071399 2.30% 83.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 528430 1.13% 84.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1841086 3.95% 88.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 362782 0.78% 89.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5074719 10.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 36764920 72.55% 72.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 704096 1.39% 73.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1222881 2.41% 76.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2516311 4.97% 81.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1142608 2.25% 83.57% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 651052 1.28% 84.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1887369 3.72% 88.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 403735 0.80% 89.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5381687 10.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 46632146 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.116253 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.918141 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 17056644 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 14680691 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 11594841 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 352795 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2947175 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 935072 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 71695 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 65351582 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 230259 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2947175 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 18144332 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 3419554 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 9765064 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 10859095 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1496926 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 59649280 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2711 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 296113 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 846856 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 41886 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 64117293 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 277536206 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 277482920 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 53286 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 35880340 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 28236953 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 382644 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 338532 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 3807140 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 10355028 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6398549 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 758675 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 956516 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 52234406 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 583658 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 46076403 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 106678 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 17743407 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 51695034 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 121990 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 46632146 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.988082 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.605820 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 50674659 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.120594 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.905621 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 18672830 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 16053118 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12511393 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 382905 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3054413 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1082178 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 80433 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 69756936 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 260341 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3054413 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 19817710 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 3624621 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 10850261 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11740016 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1587638 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 63840108 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 3002 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 319994 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 862075 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 38212 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 68266339 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 296265404 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 296212618 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 52786 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 39108942 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 29157397 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 433648 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 381432 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 4194062 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 11085935 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7020391 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 635108 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 890373 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 56044948 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 651331 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 50360925 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 120514 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 18223761 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 52593424 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 131996 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 50674659 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.993809 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.617399 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 29554282 63.38% 63.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 5171149 11.09% 74.47% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3458614 7.42% 81.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3350013 7.18% 89.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2774412 5.95% 95.02% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1396410 2.99% 98.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 685832 1.47% 99.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 188175 0.40% 99.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 53259 0.11% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 32153473 63.45% 63.45% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 5526378 10.91% 74.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3775422 7.45% 81.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3611274 7.13% 88.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2989508 5.90% 94.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1557590 3.07% 97.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 784960 1.55% 99.46% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 214293 0.42% 99.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 61761 0.12% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 46632146 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 50674659 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 13884 1.72% 1.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 1004 0.12% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 591453 73.41% 75.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 199352 24.74% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 15522 1.51% 1.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 1191 0.12% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 749386 73.14% 74.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 258502 25.23% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 18555 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 30356671 65.88% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 45470 0.10% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 1 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 778 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 10369047 22.50% 88.53% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 5285878 11.47% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 18622 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 32758484 65.05% 65.08% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 50347 0.10% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 2 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 759 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 11614499 23.06% 88.25% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 5918207 11.75% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 46076403 # Type of FU issued -system.cpu1.iq.rate 0.714929 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 805693 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.017486 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 139732039 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 70588254 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 40690264 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 12584 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7193 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5833 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 46856971 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6570 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 234193 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 50360925 # Type of FU issued +system.cpu1.iq.rate 0.729010 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1024601 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020345 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 152586143 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 74924785 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 44270347 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 12757 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7087 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5824 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 51360226 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6678 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 266055 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3842003 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 5600 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 34715 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1441399 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3973405 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 7375 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 12287 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1481060 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 1340152 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1120623 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 1850150 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1139659 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2947175 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 2308626 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 70118 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 52866942 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 210917 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 10355028 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6398549 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 369018 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 28955 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3115 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 34715 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 320337 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 109623 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 429960 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 43402987 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 9638435 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2673416 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3054413 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2505400 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 71046 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 56747555 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 255776 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 11085935 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7020391 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 408110 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 28416 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3434 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 12287 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 384769 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 125659 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 510428 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 47569274 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 10848117 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2791651 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 48878 # number of nop insts executed -system.cpu1.iew.exec_refs 14847152 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5186837 # Number of branches executed -system.cpu1.iew.exec_stores 5208717 # Number of stores executed -system.cpu1.iew.exec_rate 0.673448 # Inst execution rate -system.cpu1.iew.wb_sent 42199254 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 40696097 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 22507628 # num instructions producing a value -system.cpu1.iew.wb_consumers 40593312 # num instructions consuming a value +system.cpu1.iew.exec_nop 51276 # number of nop insts executed +system.cpu1.iew.exec_refs 16673626 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5809146 # Number of branches executed +system.cpu1.iew.exec_stores 5825509 # Number of stores executed +system.cpu1.iew.exec_rate 0.688599 # Inst execution rate +system.cpu1.iew.wb_sent 46311223 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 44276171 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 24275566 # num instructions producing a value +system.cpu1.iew.wb_consumers 44463888 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.631448 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.554466 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.640929 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.545961 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 34749379 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 18015602 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 461668 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 380980 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 43720356 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.794810 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.823117 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 38087596 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 18562736 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 519335 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 450588 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 47661477 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.799127 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.835707 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 31867002 72.89% 72.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 5587415 12.78% 85.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1616564 3.70% 89.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 871952 1.99% 91.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 744460 1.70% 93.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 803606 1.84% 94.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 559765 1.28% 96.18% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 398216 0.91% 97.09% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1271376 2.91% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 34693281 72.79% 72.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6099066 12.80% 85.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1834262 3.85% 89.44% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 962147 2.02% 91.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 825706 1.73% 93.19% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 739217 1.55% 94.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 588574 1.23% 95.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 450580 0.95% 96.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1468644 3.08% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 43720356 # Number of insts commited each cycle -system.cpu1.commit.count 34749379 # Number of instructions committed +system.cpu1.commit.committed_per_cycle::total 47661477 # Number of insts commited each cycle +system.cpu1.commit.count 38087596 # Number of instructions committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 11470175 # Number of memory references committed -system.cpu1.commit.loads 6513025 # Number of loads committed -system.cpu1.commit.membars 132167 # Number of memory barriers committed -system.cpu1.commit.branches 4257777 # Number of branches committed +system.cpu1.commit.refs 12651861 # Number of memory references committed +system.cpu1.commit.loads 7112530 # Number of loads committed +system.cpu1.commit.membars 148745 # Number of memory barriers committed +system.cpu1.commit.branches 4804762 # Number of branches committed system.cpu1.commit.fp_insts 5744 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 31123411 # Number of committed integer instructions. -system.cpu1.commit.function_calls 369866 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1271376 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 34029989 # Number of committed integer instructions. +system.cpu1.commit.function_calls 433336 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1468644 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 94544262 # The number of ROB reads -system.cpu1.rob.rob_writes 108591524 # The number of ROB writes -system.cpu1.timesIdled 403013 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 17816742 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.committedInsts 34724825 # Number of Instructions Simulated -system.cpu1.committedInsts_total 34724825 # Number of Instructions Simulated -system.cpu1.cpi 1.855989 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.855989 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.538796 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.538796 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 204029035 # number of integer regfile reads -system.cpu1.int_regfile_writes 43806802 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4161 # number of floating regfile reads -system.cpu1.fp_regfile_writes 1800 # number of floating regfile writes -system.cpu1.misc_regfile_reads 72521776 # number of misc regfile reads -system.cpu1.misc_regfile_writes 283678 # number of misc regfile writes -system.cpu1.icache.replacements 430439 # number of replacements -system.cpu1.icache.tagsinuse 498.734431 # Cycle average of tags in use -system.cpu1.icache.total_refs 7202456 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 430951 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 16.712935 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74509623000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 498.734431 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.974091 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 7202456 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7202456 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 7202456 # number of demand (read+write) hits +system.cpu1.rob.rob_reads 102084600 # The number of ROB reads +system.cpu1.rob.rob_writes 116474424 # The number of ROB writes +system.cpu1.timesIdled 450576 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 18406597 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.committedInsts 38063042 # Number of Instructions Simulated +system.cpu1.committedInsts_total 38063042 # Number of Instructions Simulated +system.cpu1.cpi 1.814917 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.814917 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.550989 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.550989 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 222881114 # number of integer regfile reads +system.cpu1.int_regfile_writes 47167594 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4241 # number of floating regfile reads +system.cpu1.fp_regfile_writes 1808 # number of floating regfile writes +system.cpu1.misc_regfile_reads 77248425 # number of misc regfile reads +system.cpu1.misc_regfile_writes 323332 # number of misc regfile writes +system.cpu1.icache.replacements 486491 # number of replacements +system.cpu1.icache.tagsinuse 498.789046 # Cycle average of tags in use +system.cpu1.icache.total_refs 7677673 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 487003 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 15.765145 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74237229000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::0 498.789046 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.974197 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::0 7677673 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7677673 # number of ReadReq hits +system.cpu1.icache.demand_hits::0 7677673 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7202456 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 7202456 # number of overall hits +system.cpu1.icache.demand_hits::total 7677673 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::0 7677673 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 7202456 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 468704 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 468704 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 468704 # number of demand (read+write) misses +system.cpu1.icache.overall_hits::total 7677673 # number of overall hits +system.cpu1.icache.ReadReq_misses::0 528325 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 528325 # number of ReadReq misses +system.cpu1.icache.demand_misses::0 528325 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 468704 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 468704 # number of overall misses +system.cpu1.icache.demand_misses::total 528325 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::0 528325 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 468704 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 6861113492 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 6861113492 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 6861113492 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 7671160 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7671160 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 7671160 # number of demand (read+write) accesses +system.cpu1.icache.overall_misses::total 528325 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency 7771273996 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency 7771273996 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency 7771273996 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::0 8205998 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8205998 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::0 8205998 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7671160 # 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miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.061099 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::0 0.064383 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::0 14638.478639 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::0 14709.267962 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::0 14638.478639 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::0 14709.267962 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 14638.478639 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::0 14709.267962 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1040994 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 1184497 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 141 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 157 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7382.936170 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7544.566879 # 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number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits 41295 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses 487030 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses 487030 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses 487030 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 5122297994 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 5122297994 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 5122297994 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency 5811540497 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 5811540497 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 5811540497 # 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mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::0 0.059350 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11885.343950 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11885.343950 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11885.343950 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11932.612975 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11932.612975 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11932.612975 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency inf # 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number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::0 83694 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 83694 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::0 11819982 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 10694850 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 10694850 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::total 11819982 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::0 11819982 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 10694850 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.044179 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.316500 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.153755 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.140812 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.143612 # miss rate for demand accesses +system.cpu1.dcache.overall_accesses::total 11819982 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::0 0.043780 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::0 0.288715 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.144315 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.132578 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::0 0.135244 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.143612 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::0 0.135244 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::0 15485.619989 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::0 15622.029601 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::0 36568.819277 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::0 36292.942216 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11518.339768 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11662.716535 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 8286.411992 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 7963.455299 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::0 32451.229978 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::0 32100.258330 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 32451.229978 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::0 32100.258330 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 10791088 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5629500 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 2675 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 166 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4034.051589 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 33912.650602 # average number of cycles each access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 13378551 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5449500 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3082 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 157 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4340.866645 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 34710.191083 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 207215 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits 126705 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits 1124640 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits 1020 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits 1251345 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 1251345 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 173260 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 111299 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses 10894 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses 10338 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 284559 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 284559 # number of overall MSHR misses +system.cpu1.dcache.writebacks 223500 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits 134561 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits 1158019 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits 988 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits 1292580 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits 1292580 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses 189680 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses 116324 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses 11712 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses 11095 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses 306004 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses 306004 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 2232969500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 3340467088 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 89924500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 54610500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 5573436588 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 5573436588 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 8313873500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 41408758936 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 49722632436 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.025518 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_latency 2497244500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 3447430551 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 99180500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 55002000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 5944675051 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 5944675051 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 8455396000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 41503639517 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency 49959035517 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.025611 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.028502 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.026354 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.140591 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.133088 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.140785 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.132566 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::0 0.026607 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::0 0.025889 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0.026607 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::0 0.025889 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12887.968948 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 30013.451046 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8254.497889 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 5282.501451 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 19586.224959 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 19586.224959 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13165.565690 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 29636.451214 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8468.280396 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 4957.368184 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 19426.788705 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 19426.788705 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -1361,8 +1353,8 @@ system.iocache.overall_mshr_misses 0 # nu system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_uncacheable_latency 1308159015940 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency 1308159015940 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency 1308164389827 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency 1308164389827 # number of overall MSHR uncacheable cycles system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses @@ -1377,8 +1369,8 @@ system.iocache.mshr_cap_events 0 # nu system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 61327 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 55750 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 36142 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 41971 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 8cd80ba37..79ce98ed4 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -9,13 +9,13 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver boot_cpu_frequency=500 -boot_loader=/chips/pd/randd/dist/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -63,7 +63,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu] diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout index 44872c771..b45c8117b 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -3,11 +3,12 @@ Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 18 2011 19:13:50 -gem5 started Aug 18 2011 19:17:05 -gem5 executing on nadc-0330 +gem5 compiled Aug 20 2011 15:41:18 +gem5 started Aug 20 2011 15:46:02 +gem5 executing on zizzer command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux.arm +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2503824454500 because m5_exit instruction encountered +Exiting @ tick 2503587516500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index f5e789429..ae3ccdd2b 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,108 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.503824 # Number of seconds simulated -sim_ticks 2503824454500 # Number of ticks simulated +sim_seconds 2.503588 # Number of seconds simulated +sim_ticks 2503587516500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79718 # Simulator instruction rate (inst/s) -host_tick_rate 2598962996 # Simulator tick rate (ticks/s) -host_mem_usage 429452 # Number of bytes of host memory used -host_seconds 963.39 # Real time elapsed on the host -sim_insts 76800038 # Number of instructions simulated -system.l2c.replacements 119528 # number of replacements -system.l2c.tagsinuse 25937.630096 # Cycle average of tags in use -system.l2c.total_refs 1800987 # Total number of references to valid blocks. -system.l2c.sampled_refs 150361 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.977754 # Average number of references to valid blocks. +host_inst_rate 84198 # Simulator instruction rate (inst/s) +host_tick_rate 2745069755 # Simulator tick rate (ticks/s) +host_mem_usage 385208 # Number of bytes of host memory used +host_seconds 912.03 # Real time elapsed on the host +sim_insts 76790714 # Number of instructions simulated +system.l2c.replacements 119531 # number of replacements +system.l2c.tagsinuse 25929.939584 # Cycle average of tags in use +system.l2c.total_refs 1799445 # Total number of references to valid blocks. +system.l2c.sampled_refs 150368 # Sample count of references to valid blocks. +system.l2c.avg_refs 11.966941 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11548.723381 # Average occupied blocks per context -system.l2c.occ_blocks::1 14388.906715 # Average occupied blocks per context -system.l2c.occ_percent::0 0.176220 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.219557 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1352767 # number of ReadReq hits -system.l2c.ReadReq_hits::1 155574 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1508341 # number of ReadReq hits -system.l2c.Writeback_hits::0 630909 # number of Writeback hits -system.l2c.Writeback_hits::total 630909 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 49 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 49 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 19 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 19 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 105993 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 105993 # number of ReadExReq hits -system.l2c.demand_hits::0 1458760 # number of demand (read+write) hits -system.l2c.demand_hits::1 155574 # number of demand (read+write) hits -system.l2c.demand_hits::total 1614334 # number of demand (read+write) hits -system.l2c.overall_hits::0 1458760 # number of overall hits -system.l2c.overall_hits::1 155574 # number of overall hits -system.l2c.overall_hits::total 1614334 # number of overall hits -system.l2c.ReadReq_misses::0 36107 # number of ReadReq misses -system.l2c.ReadReq_misses::1 150 # number of ReadReq misses -system.l2c.ReadReq_misses::total 36257 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 3257 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3257 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::0 9 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 9 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 140403 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140403 # number of ReadExReq misses -system.l2c.demand_misses::0 176510 # number of demand (read+write) misses -system.l2c.demand_misses::1 150 # number of demand (read+write) misses -system.l2c.demand_misses::total 176660 # number of demand (read+write) misses -system.l2c.overall_misses::0 176510 # number of overall misses -system.l2c.overall_misses::1 150 # number of overall misses -system.l2c.overall_misses::total 176660 # number of overall misses -system.l2c.ReadReq_miss_latency 1897665500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 1154500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency 52000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7382579000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 9280244500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 9280244500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 1388874 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 155724 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1544598 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 630909 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 630909 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 3306 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3306 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 28 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 28 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 246396 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246396 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 1635270 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 155724 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1790994 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 1635270 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 155724 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1790994 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.025997 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000963 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.026961 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.985178 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.321429 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.569827 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.107939 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000963 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.108903 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.107939 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000963 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.108903 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52556.720304 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 12651103.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 12703660.053637 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 354.467301 # average UpgradeReq miss latency +system.l2c.occ_blocks::0 11550.967581 # Average occupied blocks per context +system.l2c.occ_blocks::1 14378.972003 # Average occupied blocks per context +system.l2c.occ_percent::0 0.176254 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.219406 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1351962 # number of ReadReq hits +system.l2c.ReadReq_hits::1 155464 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1507426 # number of ReadReq hits +system.l2c.Writeback_hits::0 630774 # number of Writeback hits +system.l2c.Writeback_hits::total 630774 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 42 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 17 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 17 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 105933 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 105933 # number of ReadExReq hits +system.l2c.demand_hits::0 1457895 # number of demand (read+write) hits +system.l2c.demand_hits::1 155464 # number of demand (read+write) hits +system.l2c.demand_hits::total 1613359 # number of demand (read+write) hits +system.l2c.overall_hits::0 1457895 # number of overall hits +system.l2c.overall_hits::1 155464 # number of overall hits +system.l2c.overall_hits::total 1613359 # number of overall hits +system.l2c.ReadReq_misses::0 36117 # number of ReadReq misses +system.l2c.ReadReq_misses::1 148 # number of ReadReq misses +system.l2c.ReadReq_misses::total 36265 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 3244 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3244 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::0 2 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 140419 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140419 # number of ReadExReq misses +system.l2c.demand_misses::0 176536 # number of demand (read+write) misses +system.l2c.demand_misses::1 148 # number of demand (read+write) misses +system.l2c.demand_misses::total 176684 # number of demand (read+write) misses +system.l2c.overall_misses::0 176536 # number of overall misses +system.l2c.overall_misses::1 148 # number of overall misses +system.l2c.overall_misses::total 176684 # number of overall misses +system.l2c.ReadReq_miss_latency 1896887000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 953000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7384203500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 9281090500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 9281090500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 1388079 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 155612 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1543691 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 630774 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 630774 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 3286 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3286 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 19 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 246352 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246352 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 1634431 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 155612 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1790043 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 1634431 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 155612 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1790043 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.026019 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000951 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.026970 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.987219 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.105263 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.569993 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.108011 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000951 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.108962 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.108011 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000951 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.108962 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52520.613561 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 12816804.054054 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 12869324.667616 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 293.773120 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 5777.777778 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52581.347977 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52586.925559 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52576.310124 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 61868296.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 61920872.976791 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52576.310124 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 61868296.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 61920872.976791 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52573.358975 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 62710070.945946 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 62762644.304921 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52573.358975 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 62710070.945946 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 62762644.304921 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -111,50 +107,50 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 102659 # number of writebacks -system.l2c.ReadReq_mshr_hits 99 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 99 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 99 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 36158 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3257 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 9 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 140403 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 176561 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 176561 # number of overall MSHR misses +system.l2c.writebacks 102665 # number of writebacks +system.l2c.ReadReq_mshr_hits 95 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits 95 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 95 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 36170 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3244 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses 2 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 140419 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 176589 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 176589 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 1452283500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 131732500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 360000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5638732500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 7091016000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 7091016000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 131768110500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 32345431294 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 164113541794 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.026034 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.232193 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.258227 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.985178 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 1451509500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 130965000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency 80000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5640198500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 7091708000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 7091708000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 131769561500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 32342663570 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 164112225070 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.026058 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.232437 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.258495 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.987219 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.321429 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.105263 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.569827 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.569993 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.107971 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.133807 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.241778 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.107971 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.133807 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.241778 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40164.928923 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40445.962542 # average UpgradeReq mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.108043 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.134803 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.242846 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.108043 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.134803 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.242846 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40130.204589 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40371.454994 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40161.054251 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40161.847747 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40161.847747 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40166.918295 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40159.398377 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40159.398377 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -169,27 +165,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51109554 # DTB read hits -system.cpu.dtb.read_misses 89772 # DTB read misses -system.cpu.dtb.write_hits 11994703 # DTB write hits -system.cpu.dtb.write_misses 25525 # DTB write misses +system.cpu.dtb.read_hits 52225825 # DTB read hits +system.cpu.dtb.read_misses 89986 # DTB read misses +system.cpu.dtb.write_hits 11975736 # DTB write hits +system.cpu.dtb.write_misses 26350 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 8382 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 661 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4338 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 8018 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 617 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 2390 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51199326 # DTB read accesses -system.cpu.dtb.write_accesses 12020228 # DTB write accesses +system.cpu.dtb.perms_faults 2450 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 52315811 # DTB read accesses +system.cpu.dtb.write_accesses 12002086 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63104257 # DTB hits -system.cpu.dtb.misses 115297 # DTB misses -system.cpu.dtb.accesses 63219554 # DTB accesses -system.cpu.itb.inst_hits 14358238 # ITB inst hits -system.cpu.itb.inst_misses 11476 # ITB inst misses +system.cpu.dtb.hits 64201561 # DTB hits +system.cpu.dtb.misses 116336 # DTB misses +system.cpu.dtb.accesses 64317897 # DTB accesses +system.cpu.itb.inst_hits 14135631 # ITB inst hits +system.cpu.itb.inst_misses 11185 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -198,516 +194,516 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2618 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2607 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8489 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8440 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 14369714 # ITB inst accesses -system.cpu.itb.hits 14358238 # DTB hits -system.cpu.itb.misses 11476 # DTB misses -system.cpu.itb.accesses 14369714 # DTB accesses -system.cpu.numCycles 416612538 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 14146816 # ITB inst accesses +system.cpu.itb.hits 14135631 # DTB hits +system.cpu.itb.misses 11185 # DTB misses +system.cpu.itb.accesses 14146816 # DTB accesses +system.cpu.numCycles 415920995 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16387222 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12668617 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1109677 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 14122008 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 10400042 # Number of BTB hits +system.cpu.BPredUnit.lookups 16219215 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12559944 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1110172 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 13927920 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 10224432 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1438387 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 228434 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33205064 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105935094 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16387222 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11838429 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24790129 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7281806 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 140399 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 92648607 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1264 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 149325 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 219222 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 315 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14348946 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1053874 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6421 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 156122024 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.843787 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.188312 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1424516 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 228409 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 32955891 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 104818490 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16219215 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11648948 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24471055 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 7079806 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 137198 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 92799321 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1248 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 151217 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 217200 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 351 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 14126420 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1047323 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6165 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 155547085 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.838560 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.184344 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131359328 84.14% 84.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1797067 1.15% 85.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2650142 1.70% 86.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3706376 2.37% 89.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2183779 1.40% 90.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1469088 0.94% 91.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2676851 1.71% 93.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 859477 0.55% 93.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9419916 6.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131101786 84.28% 84.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1736791 1.12% 85.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2601051 1.67% 87.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3653656 2.35% 89.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2169863 1.39% 90.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1434892 0.92% 91.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2627328 1.69% 93.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 855909 0.55% 93.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9365809 6.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 156122024 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.039334 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.254277 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35461706 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 92496954 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22296946 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1073972 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4792446 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2336165 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 178310 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 123347211 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 575607 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4792446 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37647350 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36719045 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 49837786 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21186830 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5938567 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 115130197 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4438 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 893530 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3968160 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 43280 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 119684467 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529404061 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 529305097 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 98964 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77501999 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 42182467 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1209283 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1098761 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12191274 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 22237858 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14288032 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2207613 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2740072 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 103897694 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1876028 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126150518 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 258491 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 28028723 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 75807996 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 377489 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 156122024 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.808025 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.494664 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 155547085 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.038996 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.252015 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35186802 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 92649693 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 21977926 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1094000 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4638664 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2316854 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 177884 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 122073457 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 575981 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4638664 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37340555 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36816085 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 49864787 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20912628 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5974366 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 113922984 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4414 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 914987 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3980816 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 42327 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 118460665 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 523781573 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 523685374 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 96199 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 77493785 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 40966879 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1201529 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1095575 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12285551 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 22000628 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14180796 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1905529 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2295702 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 102943309 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1872075 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126931651 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 252428 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27053062 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 73124308 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 373806 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 155547085 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.816034 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.505599 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 109310496 70.02% 70.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15452280 9.90% 79.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7704093 4.93% 84.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6547773 4.19% 89.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12500649 8.01% 97.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2674638 1.71% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1385356 0.89% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 415101 0.27% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 131638 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108904431 70.01% 70.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15118772 9.72% 79.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7542016 4.85% 84.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6525767 4.20% 88.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12768009 8.21% 96.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2736654 1.76% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1396269 0.90% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 422710 0.27% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 132457 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 156122024 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 155547085 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45842 0.53% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 8 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8169590 94.68% 95.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412814 4.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45562 0.51% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8415938 94.58% 95.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 436851 4.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60408589 47.89% 47.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 96901 0.08% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 3 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 3 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 3 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2257 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52851212 41.90% 89.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12685017 10.06% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60109955 47.36% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 96551 0.08% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 1 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 3 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 3 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2253 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53954328 42.51% 90.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12662017 9.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126150518 # Type of FU issued -system.cpu.iq.rate 0.302801 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8628254 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.068397 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 417401182 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 133881929 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87720713 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23251 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13846 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10518 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134660044 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12198 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 599778 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126931651 # Type of FU issued +system.cpu.iq.rate 0.305182 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8898356 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070104 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 418652883 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 131886553 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87334534 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23945 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13416 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10473 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 135710724 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12753 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 616189 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6553966 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11010 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 95494 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2507321 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6319666 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11234 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 32604 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2401616 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 32840687 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1141901 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34061863 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1153574 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4792446 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28191284 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 424606 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 105991714 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 477393 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 22237858 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14288032 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1227462 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 89856 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7011 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 95494 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 852380 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 256698 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1109078 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 122676478 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51808342 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3474040 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4638664 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28343669 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 418971 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 105030898 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 476967 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 22000628 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14180796 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1225085 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 85041 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7449 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 32604 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 851635 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 257956 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1109591 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 123477395 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52923959 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3454256 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 217992 # number of nop insts executed -system.cpu.iew.exec_refs 64319690 # number of memory reference insts executed -system.cpu.iew.exec_branches 11745709 # Number of branches executed -system.cpu.iew.exec_stores 12511348 # Number of stores executed -system.cpu.iew.exec_rate 0.294462 # Inst execution rate -system.cpu.iew.wb_sent 120986716 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87731231 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47245202 # num instructions producing a value -system.cpu.iew.wb_consumers 86878076 # num instructions consuming a value +system.cpu.iew.exec_nop 215514 # number of nop insts executed +system.cpu.iew.exec_refs 65415175 # number of memory reference insts executed +system.cpu.iew.exec_branches 11714146 # Number of branches executed +system.cpu.iew.exec_stores 12491216 # Number of stores executed +system.cpu.iew.exec_rate 0.296877 # Inst execution rate +system.cpu.iew.wb_sent 121817988 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87345007 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47064551 # num instructions producing a value +system.cpu.iew.wb_consumers 86684992 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.210582 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.543810 # average fanout of values written-back +system.cpu.iew.wb_rate 0.210004 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.542938 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 76950419 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 28805793 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1498539 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 978025 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151411950 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.508219 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.450093 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 76941095 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 27854412 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1498269 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 978817 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 150990773 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.509575 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.459429 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 122345277 80.80% 80.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 15024261 9.92% 90.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4072409 2.69% 93.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2238793 1.48% 94.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1805162 1.19% 96.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1472326 0.97% 97.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1253236 0.83% 97.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 640621 0.42% 98.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2559865 1.69% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 122133629 80.89% 80.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14849154 9.83% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4108732 2.72% 93.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2181203 1.44% 94.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1788420 1.18% 96.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1359682 0.90% 96.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1260703 0.83% 97.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 659440 0.44% 98.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2649810 1.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151411950 # Number of insts commited each cycle -system.cpu.commit.count 76950419 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 150990773 # Number of insts commited each cycle +system.cpu.commit.count 76941095 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27464603 # Number of memory references committed -system.cpu.commit.loads 15683892 # Number of loads committed -system.cpu.commit.membars 413156 # Number of memory barriers committed -system.cpu.commit.branches 9892324 # Number of branches committed +system.cpu.commit.refs 27460142 # Number of memory references committed +system.cpu.commit.loads 15680962 # Number of loads committed +system.cpu.commit.membars 413062 # Number of memory barriers committed +system.cpu.commit.branches 9891108 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68502645 # Number of committed integer instructions. -system.cpu.commit.function_calls 995827 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2559865 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68494112 # Number of committed integer instructions. +system.cpu.commit.function_calls 995603 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2649810 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 252851506 # The number of ROB reads -system.cpu.rob.rob_writes 216434899 # The number of ROB writes -system.cpu.timesIdled 1874952 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260490514 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 76800038 # Number of Instructions Simulated -system.cpu.committedInsts_total 76800038 # Number of Instructions Simulated -system.cpu.cpi 5.424640 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.424640 # CPI: Total CPI of All Threads -system.cpu.ipc 0.184344 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.184344 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 556945889 # number of integer regfile reads -system.cpu.int_regfile_writes 90207171 # number of integer regfile writes -system.cpu.fp_regfile_reads 8143 # number of floating regfile reads -system.cpu.fp_regfile_writes 2804 # number of floating regfile writes -system.cpu.misc_regfile_reads 138641891 # number of misc regfile reads -system.cpu.misc_regfile_writes 912464 # number of misc regfile writes -system.cpu.icache.replacements 993778 # number of replacements -system.cpu.icache.tagsinuse 511.609153 # Cycle average of tags in use -system.cpu.icache.total_refs 13263624 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 994290 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13.339794 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6449865000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 511.609153 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.999237 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 13263624 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13263624 # number of ReadReq hits -system.cpu.icache.demand_hits::0 13263624 # number of demand (read+write) hits +system.cpu.rob.rob_reads 251379971 # The number of ROB reads +system.cpu.rob.rob_writes 214361160 # The number of ROB writes +system.cpu.timesIdled 1877573 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 260373910 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 76790714 # Number of Instructions Simulated +system.cpu.committedInsts_total 76790714 # Number of Instructions Simulated +system.cpu.cpi 5.416293 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.416293 # CPI: Total CPI of All Threads +system.cpu.ipc 0.184628 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.184628 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 559837261 # number of integer regfile reads +system.cpu.int_regfile_writes 89743570 # number of integer regfile writes +system.cpu.fp_regfile_reads 8283 # number of floating regfile reads +system.cpu.fp_regfile_writes 2809 # number of floating regfile writes +system.cpu.misc_regfile_reads 137364406 # number of misc regfile reads +system.cpu.misc_regfile_writes 912286 # number of misc regfile writes +system.cpu.icache.replacements 993006 # number of replacements +system.cpu.icache.tagsinuse 511.614815 # Cycle average of tags in use +system.cpu.icache.total_refs 13045370 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 993518 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13.130482 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6445921000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 511.614815 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.999248 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 13045370 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13045370 # number of ReadReq hits +system.cpu.icache.demand_hits::0 13045370 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13263624 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 13263624 # number of overall hits +system.cpu.icache.demand_hits::total 13045370 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 13045370 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 13263624 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1085201 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1085201 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1085201 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 13045370 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1080929 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1080929 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1080929 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1085201 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1085201 # number of overall misses +system.cpu.icache.demand_misses::total 1080929 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1080929 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1085201 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15970611491 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15970611491 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15970611491 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 14348825 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14348825 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 14348825 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1080929 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15935046488 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15935046488 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15935046488 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 14126299 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14126299 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 14126299 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14348825 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 14348825 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 14126299 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 14126299 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14348825 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.075630 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.075630 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 14126299 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.076519 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.076519 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.075630 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.076519 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14716.731270 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14741.991831 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14716.731270 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14741.991831 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14716.731270 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14741.991831 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2367996 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 2385493 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 355 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 357 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 6670.411268 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 6682.053221 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 57801 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 90865 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 90865 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 90865 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 994336 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 994336 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 994336 # number of overall MSHR misses +system.cpu.icache.writebacks 57770 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 87373 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 87373 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 87373 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 993556 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 993556 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 993556 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 11881405996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 11881405996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 11881405996 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 11874405493 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 11874405493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 11874405493 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency 6359500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 6359500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.069297 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.070334 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.069297 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.070334 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.069297 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.070334 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11949.085617 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11949.085617 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11949.085617 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11951.420446 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11951.420446 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11951.420446 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 644301 # number of replacements -system.cpu.dcache.tagsinuse 511.991682 # Cycle average of tags in use -system.cpu.dcache.total_refs 22398030 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644813 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.735699 # Average number of references to valid blocks. +system.cpu.dcache.replacements 644346 # number of replacements +system.cpu.dcache.tagsinuse 511.991681 # Cycle average of tags in use +system.cpu.dcache.total_refs 22273031 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644858 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34.539435 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 48663000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.991682 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 511.991681 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 14543242 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 14543242 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 7265728 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7265728 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 300074 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 300074 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 285526 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285526 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 21808970 # number of demand (read+write) hits +system.cpu.dcache.ReadReq_hits::0 14419247 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 14419247 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 7264920 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7264920 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 299971 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 299971 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 285485 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285485 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 21684167 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21808970 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 21808970 # number of overall hits +system.cpu.dcache.demand_hits::total 21684167 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 21684167 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 21808970 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 725476 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 725476 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 2967115 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2967115 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 13509 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13509 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::0 29 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 29 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::0 3692591 # number of demand (read+write) misses +system.cpu.dcache.overall_hits::total 21684167 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 724263 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 724263 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 2966438 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2966438 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::0 13488 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13488 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::0 19 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::0 3690701 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3692591 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 3692591 # number of overall misses +system.cpu.dcache.demand_misses::total 3690701 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 3690701 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3692591 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 10888742000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 110296988750 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 219229500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency 779000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency 121185730750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 121185730750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 15268718 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 15268718 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 10232843 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10232843 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 313583 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 313583 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 285555 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285555 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 25501561 # number of demand (read+write) accesses +system.cpu.dcache.overall_misses::total 3690701 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 10889184500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 110353624242 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 218944000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency 357000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency 121242808742 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 121242808742 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 15143510 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 15143510 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 10231358 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10231358 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 313459 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 313459 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 285504 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285504 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 25374868 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 25501561 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 25501561 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 25374868 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 25374868 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 25501561 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.047514 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.289960 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.043080 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::0 0.000102 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::0 0.144799 # miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 25374868 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.047827 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.289936 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.043030 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::0 0.000067 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::0 0.145447 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.144799 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.145447 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 15009.100232 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 15034.848529 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 37173.142514 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 37200.718249 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16228.403287 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16232.502966 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 26862.068966 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 18789.473684 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 32818.617266 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 32850.888962 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 32818.617266 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 32850.888962 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16440438 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7572500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2965 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5544.835750 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 26757.950530 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 16719933 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7529000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2957 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 277 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5654.356781 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 27180.505415 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 573108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 338981 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 2717547 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 1453 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 3056528 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 3056528 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 386495 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 249568 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 12056 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses 29 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses 636063 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 636063 # number of overall MSHR misses +system.cpu.dcache.writebacks 573004 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 337704 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 2716896 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 1445 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 3054600 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 3054600 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 386559 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 249542 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 12043 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses 636101 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 636101 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5252112000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8923093438 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 161656000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency 684500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 14175205438 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 14175205438 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 147157433500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 42270831280 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 189428264780 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025313 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 5253783500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8925189433 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 161542500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency 293500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 14178972933 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 14178972933 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 147158793000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 42258212210 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 189417005210 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025526 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024389 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024390 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.038446 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.038420 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000102 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000067 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.024942 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.025068 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.024942 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.025068 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13589.081359 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35754.156935 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13408.759124 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 23603.448276 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22285.851304 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22285.851304 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13591.155555 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35766.281560 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13413.808852 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 15447.368421 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 22290.442765 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 22290.442765 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -768,8 +764,8 @@ system.iocache.overall_mshr_misses 0 # nu system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_uncacheable_latency 1308136733935 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency 1308136733935 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency 1307895610037 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency 1307895610037 # number of overall MSHR uncacheable cycles system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses @@ -784,6 +780,6 @@ system.iocache.mshr_cap_events 0 # nu system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88013 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 87985 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 23340838e..336a6fed4 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -15,7 +15,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/arm/scratch/sysexplr/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem @@ -1301,7 +1301,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/arm/scratch/sysexplr/dist/disks/linux-x86.img +image_file=/dist/m5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1321,7 +1321,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/arm/scratch/sysexplr/dist/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index c0ff48d52..96389038f 100755 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 19:14:00 -gem5 started Aug 17 2011 19:16:38 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 15:40:58 +gem5 started Aug 20 2011 15:42:13 +gem5 executing on zizzer command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/scratch/sysexplr/dist/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5139621012500 because m5_exit instruction encountered +Exiting @ tick 5147601271500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 74858b319..e13689c4a 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,97 +1,97 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.139621 # Number of seconds simulated -sim_ticks 5139621012500 # Number of ticks simulated +sim_seconds 5.147601 # Number of seconds simulated +sim_ticks 5147601271500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 264330 # Simulator instruction rate (inst/s) -host_tick_rate 1617420466 # Simulator tick rate (ticks/s) -host_mem_usage 409996 # Number of bytes of host memory used -host_seconds 3177.67 # Real time elapsed on the host -sim_insts 839951837 # Number of instructions simulated -system.l2c.replacements 170440 # number of replacements -system.l2c.tagsinuse 38394.915319 # Cycle average of tags in use -system.l2c.total_refs 3798996 # Total number of references to valid blocks. -system.l2c.sampled_refs 206462 # Sample count of references to valid blocks. -system.l2c.avg_refs 18.400461 # Average number of references to valid blocks. +host_inst_rate 290249 # Simulator instruction rate (inst/s) +host_tick_rate 1780077210 # Simulator tick rate (ticks/s) +host_mem_usage 361700 # Number of bytes of host memory used +host_seconds 2891.79 # Real time elapsed on the host +sim_insts 839336586 # Number of instructions simulated +system.l2c.replacements 169225 # number of replacements +system.l2c.tagsinuse 38391.632338 # Cycle average of tags in use +system.l2c.total_refs 3787611 # Total number of references to valid blocks. +system.l2c.sampled_refs 204461 # Sample count of references to valid blocks. +system.l2c.avg_refs 18.524858 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11966.871938 # Average occupied blocks per context -system.l2c.occ_blocks::1 26428.043381 # Average occupied blocks per context -system.l2c.occ_percent::0 0.182600 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.403260 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 2331798 # number of ReadReq hits -system.l2c.ReadReq_hits::1 145238 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2477036 # number of ReadReq hits -system.l2c.Writeback_hits::0 1588821 # number of Writeback hits -system.l2c.Writeback_hits::total 1588821 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 321 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 321 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 149873 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 149873 # number of ReadExReq hits -system.l2c.demand_hits::0 2481671 # number of demand (read+write) hits -system.l2c.demand_hits::1 145238 # number of demand (read+write) hits -system.l2c.demand_hits::total 2626909 # number of demand (read+write) hits -system.l2c.overall_hits::0 2481671 # number of overall hits -system.l2c.overall_hits::1 145238 # number of overall hits -system.l2c.overall_hits::total 2626909 # number of overall hits -system.l2c.ReadReq_misses::0 68032 # number of ReadReq misses -system.l2c.ReadReq_misses::1 90 # number of ReadReq misses -system.l2c.ReadReq_misses::total 68122 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 3926 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3926 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 142738 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 142738 # number of ReadExReq misses -system.l2c.demand_misses::0 210770 # number of demand (read+write) misses -system.l2c.demand_misses::1 90 # number of demand (read+write) misses -system.l2c.demand_misses::total 210860 # number of demand (read+write) misses -system.l2c.overall_misses::0 210770 # number of overall misses -system.l2c.overall_misses::1 90 # number of overall misses -system.l2c.overall_misses::total 210860 # number of overall misses -system.l2c.ReadReq_miss_latency 3572833000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 39364500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7469371500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 11042204500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 11042204500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2399830 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 145328 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2545158 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 1588821 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1588821 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 4247 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4247 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 292611 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 292611 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2692441 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 145328 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2837769 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2692441 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 145328 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2837769 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.028349 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000619 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.028968 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.924417 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.487808 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.078282 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000619 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.078901 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.078282 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000619 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.078901 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52516.947907 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 39698144.444444 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 39750661.392351 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 10026.617422 # average UpgradeReq miss latency +system.l2c.occ_blocks::0 12004.760540 # Average occupied blocks per context +system.l2c.occ_blocks::1 26386.871797 # Average occupied blocks per context +system.l2c.occ_percent::0 0.183178 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.402632 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 2307522 # number of ReadReq hits +system.l2c.ReadReq_hits::1 137003 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2444525 # number of ReadReq hits +system.l2c.Writeback_hits::0 1590016 # number of Writeback hits +system.l2c.Writeback_hits::total 1590016 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 326 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 326 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::0 147596 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 147596 # number of ReadExReq hits +system.l2c.demand_hits::0 2455118 # number of demand (read+write) hits +system.l2c.demand_hits::1 137003 # number of demand (read+write) hits +system.l2c.demand_hits::total 2592121 # number of demand (read+write) hits +system.l2c.overall_hits::0 2455118 # number of overall hits +system.l2c.overall_hits::1 137003 # number of overall hits +system.l2c.overall_hits::total 2592121 # number of overall hits +system.l2c.ReadReq_misses::0 66466 # number of ReadReq misses +system.l2c.ReadReq_misses::1 86 # number of ReadReq misses +system.l2c.ReadReq_misses::total 66552 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 3784 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3784 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 142440 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 142440 # number of ReadExReq misses +system.l2c.demand_misses::0 208906 # number of demand (read+write) misses +system.l2c.demand_misses::1 86 # number of demand (read+write) misses +system.l2c.demand_misses::total 208992 # number of demand (read+write) misses +system.l2c.overall_misses::0 208906 # number of overall misses +system.l2c.overall_misses::1 86 # number of overall misses +system.l2c.overall_misses::total 208992 # number of overall misses +system.l2c.ReadReq_miss_latency 3490673000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 33240000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7454154500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 10944827500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 10944827500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2373988 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 137089 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2511077 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 1590016 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1590016 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 4110 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4110 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 290036 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 290036 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2664024 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 137089 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2801113 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2664024 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 137089 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2801113 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.027998 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000627 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.028625 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.920681 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.491111 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.078417 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000627 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.079045 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.078417 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000627 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.079045 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52518.174706 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 40589220.930233 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 40641739.104938 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 8784.355180 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52329.243089 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52331.890621 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52389.830147 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 122691161.111111 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 122743550.941258 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52389.830147 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 122691161.111111 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 122743550.941258 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52391.159182 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 127265436.046512 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 127317827.205693 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52391.159182 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 127265436.046512 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 127317827.205693 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -100,88 +100,88 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 142383 # number of writebacks +system.l2c.writebacks 142484 # number of writebacks system.l2c.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits 2 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 68120 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3926 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 142738 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 210858 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 210858 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 66550 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3784 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 142440 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 208990 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 208990 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 2742078500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 157403500 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5729564000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 8471642500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 8471642500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 61532429500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1222286000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 62754715500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.028385 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.468733 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.497118 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.924417 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 2679045000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 151709500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5718096500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 8397141500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 8397141500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 61568859000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1235122000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 62803981000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.028033 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.485451 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.513484 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.920681 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.487808 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.491111 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.078315 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.450911 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.529226 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.078315 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.450911 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.529226 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40253.647974 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40092.587876 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40140.425115 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40177.003007 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40177.003007 # average overall mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.078449 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.524484 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.602933 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.078449 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.524484 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.602933 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40256.123216 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40092.362579 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40143.895675 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40179.632997 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40179.632997 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47570 # number of replacements -system.iocache.tagsinuse 0.129176 # Cycle average of tags in use +system.iocache.replacements 47520 # number of replacements +system.iocache.tagsinuse 0.153992 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47586 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47536 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994509673000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.129176 # Average occupied blocks per context -system.iocache.occ_percent::1 0.008073 # Average percentage of cache occupancy +system.iocache.warmup_cycle 4994510016000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.153992 # Average occupied blocks per context +system.iocache.occ_percent::1 0.009624 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 905 # number of ReadReq misses -system.iocache.ReadReq_misses::total 905 # number of ReadReq misses -system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses -system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses +system.iocache.ReadReq_misses::1 870 # number of ReadReq misses +system.iocache.ReadReq_misses::total 870 # number of ReadReq misses +system.iocache.WriteReq_misses::1 46704 # number of WriteReq misses +system.iocache.WriteReq_misses::total 46704 # number of WriteReq misses system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 47625 # number of demand (read+write) misses -system.iocache.demand_misses::total 47625 # number of demand (read+write) misses +system.iocache.demand_misses::1 47574 # number of demand (read+write) misses +system.iocache.demand_misses::total 47574 # number of demand (read+write) misses system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 47625 # number of overall misses -system.iocache.overall_misses::total 47625 # number of overall misses -system.iocache.ReadReq_miss_latency 113496932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 6374731160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 6488228092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 6488228092 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 905 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) +system.iocache.overall_misses::1 47574 # number of overall misses +system.iocache.overall_misses::total 47574 # number of overall misses +system.iocache.ReadReq_miss_latency 108834936 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 6370051162 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 6478886098 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 6478886098 # number of overall miss cycles +system.iocache.ReadReq_accesses::1 870 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 870 # number of ReadReq accesses(hits+misses) +system.iocache.WriteReq_accesses::1 46704 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 46704 # number of WriteReq accesses(hits+misses) system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 47625 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 47574 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47574 # number of demand (read+write) accesses system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 47625 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 47574 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47574 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses @@ -191,37 +191,37 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 125410.974586 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 125097.627586 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 136445.444349 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 136391.982742 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 136235.760462 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 136185.439484 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 136235.760462 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 136185.439484 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 68743556 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 68653524 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 11268 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6100.777068 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6092.787007 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 46667 # number of writebacks +system.iocache.writebacks 46652 # number of writebacks system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.ReadReq_mshr_misses 905 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses 47625 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 47625 # number of overall MSHR misses +system.iocache.ReadReq_mshr_misses 870 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses 46704 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses 47574 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses 47574 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 66413982 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3944974906 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 4011388888 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 4011388888 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 63576976 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3941129874 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 4004706850 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 4004706850 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -235,435 +235,434 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 73385.615470 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 84438.675214 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 84228.638068 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 84228.638068 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 73076.983908 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 84385.274794 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 84178.476689 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 84178.476689 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. +system.pc.south_bridge.ide.disks0.dma_write_bytes 2984960 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_txs 811 # Number of DMA write transactions. system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 449087853 # number of cpu cycles simulated +system.cpu.numCycles 447857914 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 91217869 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 91217869 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1248400 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 89951778 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 83914735 # Number of BTB hits +system.cpu.BPredUnit.lookups 90944358 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 90944358 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1226473 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 89599267 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 83628993 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28382208 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 451447456 # Number of instructions fetch has processed -system.cpu.fetch.Branches 91217869 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83914735 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 171329150 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6161718 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 187674 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 82029365 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36833 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 58090 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 319 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9909586 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 559902 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3975 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 286820350 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.091965 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.403436 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27835932 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 449937499 # Number of instructions fetch has processed +system.cpu.fetch.Branches 90944358 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 83628993 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170885862 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5925894 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 181270 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 82341776 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36741 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 58576 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 302 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9686350 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 533599 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3672 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 285953148 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.092624 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.403694 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 116059602 40.46% 40.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1498115 0.52% 40.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72812872 25.39% 66.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1272717 0.44% 66.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2053780 0.72% 67.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3977163 1.39% 68.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1588647 0.55% 69.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2196057 0.77% 70.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 85361397 29.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 115559786 40.41% 40.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1486948 0.52% 40.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72839284 25.47% 66.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1399836 0.49% 66.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1849088 0.65% 67.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3956894 1.38% 68.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1519974 0.53% 69.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2050817 0.72% 70.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85290521 29.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 286820350 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.203118 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.005254 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 33356268 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 78574400 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 165851521 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4241450 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4796711 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 882885518 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 285953148 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.203065 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.004643 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32848686 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 78733964 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 165420335 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4337474 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4612689 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 880519790 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 603 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4796711 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37592669 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 52283630 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10046208 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 165609505 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 16491627 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 878188662 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 14524 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 11489749 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2124384 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 6 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 880584292 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1724975571 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1724975011 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 560 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 843343914 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37240371 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 491374 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 493473 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42595982 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19743931 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10730204 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1270430 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1078815 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 870972067 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 898477 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 866458351 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 218010 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 31071842 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 45598434 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 144784 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 286820350 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.020910 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.373009 # Number of insts issued each cycle +system.cpu.rename.SquashCycles 4612689 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37008244 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 52433742 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9987311 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 165318823 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 16592339 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 876077378 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 14259 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 11608934 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2117422 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 878323292 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1719903468 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1719903124 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 344 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 842717831 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 35605454 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 480050 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 481410 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42986896 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19404127 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10589665 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1106439 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 977378 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 869234759 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 887302 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 865293083 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 172874 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 29947401 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 43606928 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 139213 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 285953148 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.025996 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.373161 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 82323990 28.70% 28.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22353891 7.79% 36.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 14123864 4.92% 41.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 9769344 3.41% 44.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 79473928 27.71% 72.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4992964 1.74% 74.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72968378 25.44% 99.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 634028 0.22% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 179963 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 81963860 28.66% 28.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22232412 7.77% 36.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 13907684 4.86% 41.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 9593533 3.35% 44.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 79512028 27.81% 72.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4973941 1.74% 74.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72992433 25.53% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 625767 0.22% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 151490 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 286820350 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 285953148 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 195550 8.86% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1820080 82.44% 91.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 192012 8.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 192405 8.66% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1837790 82.69% 91.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 192432 8.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 302678 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 830926438 95.90% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25678898 2.96% 98.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9550337 1.10% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 296605 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 830140846 95.94% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25417132 2.94% 98.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9438500 1.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 866458351 # Type of FU issued -system.cpu.iq.rate 1.929374 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2207642 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002548 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2022315315 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 902983728 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 855563326 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 258 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 55 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 868363218 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1360799 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 865293083 # Type of FU issued +system.cpu.iq.rate 1.932071 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2222627 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002569 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2019084567 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 900079448 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 854502226 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 147 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 154 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 42 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 867219037 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 68 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1353310 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4398376 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 17098 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 43182 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2298641 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4224491 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17341 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 10951 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2251290 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7817204 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 161145 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7817207 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 160453 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4796711 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 33445550 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6029017 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 871870544 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 303715 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19743931 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10730246 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 897675 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5516781 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 26023 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 43182 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 896575 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 530355 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1426930 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 864313806 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25191099 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2144544 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4612689 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 33472492 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6015693 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 870122061 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 301987 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19404127 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10589719 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 886500 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5552993 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 26264 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 10951 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 883301 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 519788 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1403089 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 863190269 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24933733 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2102813 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 34501157 # number of memory reference insts executed -system.cpu.iew.exec_branches 86709322 # Number of branches executed -system.cpu.iew.exec_stores 9310058 # Number of stores executed -system.cpu.iew.exec_rate 1.924598 # Inst execution rate -system.cpu.iew.wb_sent 863645103 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 855563381 # cumulative count of insts written-back -system.cpu.iew.wb_producers 671472669 # num instructions producing a value -system.cpu.iew.wb_consumers 1171866734 # num instructions consuming a value +system.cpu.iew.exec_refs 34134363 # number of memory reference insts executed +system.cpu.iew.exec_branches 86606805 # Number of branches executed +system.cpu.iew.exec_stores 9200630 # Number of stores executed +system.cpu.iew.exec_rate 1.927375 # Inst execution rate +system.cpu.iew.wb_sent 862563162 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 854502268 # cumulative count of insts written-back +system.cpu.iew.wb_producers 670839861 # num instructions producing a value +system.cpu.iew.wb_consumers 1171063083 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.905114 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.572994 # average fanout of values written-back +system.cpu.iew.wb_rate 1.907976 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.572847 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 839951837 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 31810372 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 753691 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1255440 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 282039656 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.978134 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.864065 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 839336586 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 30675414 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 748087 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1233611 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 281355498 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.983189 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.864496 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 102542445 36.36% 36.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 12533027 4.44% 40.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4681692 1.66% 42.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 76967359 27.29% 69.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4010237 1.42% 71.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1852910 0.66% 71.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1082027 0.38% 72.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71603983 25.39% 97.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6765976 2.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 102129547 36.30% 36.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 12394321 4.41% 40.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4610399 1.64% 42.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 76952670 27.35% 69.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4007315 1.42% 71.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1836126 0.65% 71.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1044804 0.37% 72.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71657785 25.47% 97.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6722531 2.39% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 282039656 # Number of insts commited each cycle -system.cpu.commit.count 839951837 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 281355498 # Number of insts commited each cycle +system.cpu.commit.count 839336586 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 23777157 # Number of memory references committed -system.cpu.commit.loads 15345552 # Number of loads committed +system.cpu.commit.refs 23518062 # Number of memory references committed +system.cpu.commit.loads 15179633 # Number of loads committed system.cpu.commit.membars 801 # Number of memory barriers committed -system.cpu.commit.branches 85535847 # Number of branches committed +system.cpu.commit.branches 85448275 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 768568499 # Number of committed integer instructions. +system.cpu.commit.int_insts 767896653 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6765976 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6722531 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1146952939 # The number of ROB reads -system.cpu.rob.rob_writes 1748336346 # The number of ROB writes -system.cpu.timesIdled 3079654 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 162267503 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 839951837 # Number of Instructions Simulated -system.cpu.committedInsts_total 839951837 # Number of Instructions Simulated -system.cpu.cpi 0.534659 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.534659 # CPI: Total CPI of All Threads -system.cpu.ipc 1.870351 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.870351 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1407338355 # number of integer regfile reads -system.cpu.int_regfile_writes 857621513 # number of integer regfile writes -system.cpu.fp_regfile_reads 55 # number of floating regfile reads -system.cpu.misc_regfile_reads 282388563 # number of misc regfile reads -system.cpu.misc_regfile_writes 410581 # number of misc regfile writes -system.cpu.icache.replacements 1030220 # number of replacements -system.cpu.icache.tagsinuse 510.462524 # Cycle average of tags in use -system.cpu.icache.total_refs 8809167 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1030732 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8.546515 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 54553868000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 510.462524 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.996997 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 8809167 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8809167 # number of ReadReq hits -system.cpu.icache.demand_hits::0 8809167 # number of demand (read+write) hits +system.cpu.rob.rob_reads 1144564074 # The number of ROB reads +system.cpu.rob.rob_writes 1744648535 # The number of ROB writes +system.cpu.timesIdled 3067742 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 161904766 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 839336586 # Number of Instructions Simulated +system.cpu.committedInsts_total 839336586 # Number of Instructions Simulated +system.cpu.cpi 0.533586 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.533586 # CPI: Total CPI of All Threads +system.cpu.ipc 1.874114 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.874114 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1405583914 # number of integer regfile reads +system.cpu.int_regfile_writes 856547410 # number of integer regfile writes +system.cpu.fp_regfile_reads 42 # number of floating regfile reads +system.cpu.misc_regfile_reads 281786405 # number of misc regfile reads +system.cpu.misc_regfile_writes 403681 # number of misc regfile writes +system.cpu.icache.replacements 1011974 # number of replacements +system.cpu.icache.tagsinuse 510.480374 # Cycle average of tags in use +system.cpu.icache.total_refs 8606970 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1012486 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8.500829 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 54553287000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 510.480374 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.997032 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 8606970 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8606970 # number of ReadReq hits +system.cpu.icache.demand_hits::0 8606970 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8809167 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 8809167 # number of overall hits +system.cpu.icache.demand_hits::total 8606970 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 8606970 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 8809167 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1100416 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1100416 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1100416 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 8606970 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1079377 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1079377 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1079377 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1100416 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1100416 # number of overall misses +system.cpu.icache.demand_misses::total 1079377 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1079377 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1100416 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 16477170489 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 16477170489 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 16477170489 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 9909583 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9909583 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 9909583 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1079377 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 16165039489 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 16165039489 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 16165039489 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 9686347 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9686347 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 9686347 # 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miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.111046 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.111433 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14973.583162 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14976.268245 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14973.583162 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14976.268245 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14973.583162 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14976.268245 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2487991 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 2584490 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 243 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 245 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10238.646091 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 10548.938776 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 1561 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 67148 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 67148 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 67148 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1033268 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1033268 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1033268 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12263411490 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12263411490 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.104270 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.104791 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.104270 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.104791 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.104270 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.104791 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12088.363804 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12088.363804 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12088.363804 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12081.678876 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12081.678876 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12081.678876 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # 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number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::1 13090 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 13090 # number of ReadReq misses system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::1 14318 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 14318 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::1 13090 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 13090 # number of demand (read+write) misses system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::1 14318 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 14318 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency 183495000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency 183495000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency 183495000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::1 42893 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 42893 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.overall_misses::1 13090 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 13090 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency 170458000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency 170458000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency 170458000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::1 40652 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 40652 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::1 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::1 42896 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 42896 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::1 40655 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 40655 # number of demand (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::1 42896 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 42896 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.333807 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.overall_accesses::1 40655 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 40655 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.322001 # miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::1 0.333784 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::1 0.321978 # miss rate for demand accesses system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::1 0.333784 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::1 0.321978 # miss rate for overall accesses system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12815.686548 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 13022.001528 # average ReadReq miss latency system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12815.686548 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::1 13022.001528 # average overall miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12815.686548 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::1 13022.001528 # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -673,83 +672,83 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks 2322 # number of writebacks +system.cpu.itb_walker_cache.writebacks 2568 # number of writebacks system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.itb_walker_cache.ReadReq_mshr_misses 14318 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses 14318 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses 14318 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses 13090 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses 13090 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses 13090 # number of overall MSHR misses system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 140154000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency 140154000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency 140154000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 130828500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency 130828500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency 130828500 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.333807 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.322001 # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.333784 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.321978 # mshr miss rate for demand accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.333784 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.321978 # mshr miss rate for overall accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9788.657634 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9788.657634 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9788.657634 # average overall mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9994.537815 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9994.537815 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9994.537815 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 143345 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 13.852844 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 148404 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 143358 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.035199 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5098934943000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::1 13.852844 # Average occupied blocks per context -system.cpu.dtb_walker_cache.occ_percent::1 0.865803 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::1 148429 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 148429 # number of ReadReq hits +system.cpu.dtb_walker_cache.replacements 134574 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 13.858456 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 145276 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 134589 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.079405 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5098934716000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::1 13.858456 # Average occupied blocks per context +system.cpu.dtb_walker_cache.occ_percent::1 0.866154 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::1 145328 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 145328 # number of ReadReq hits system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::1 148429 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 148429 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::1 145328 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 145328 # number of demand (read+write) hits system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::1 148429 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 148429 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::1 144294 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 144294 # number of ReadReq misses +system.cpu.dtb_walker_cache.overall_hits::1 145328 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 145328 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::1 135405 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 135405 # number of ReadReq misses system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::1 144294 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 144294 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::1 135405 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 135405 # number of demand (read+write) misses system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::1 144294 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 144294 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency 1999592000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency 1999592000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency 1999592000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::1 292723 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 292723 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.overall_misses::1 135405 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 135405 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency 1884318500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency 1884318500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency 1884318500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::1 280733 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 280733 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::1 292723 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 292723 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::1 280733 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 280733 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::1 292723 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 292723 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.492937 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.overall_accesses::1 280733 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 280733 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.482327 # miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::1 0.492937 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::1 0.482327 # miss rate for demand accesses system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::1 0.492937 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::1 0.482327 # miss rate for overall accesses system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13857.762624 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13916.166316 # average ReadReq miss latency system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13857.762624 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13916.166316 # average overall miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13857.762624 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13916.166316 # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -759,136 +758,136 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks 36787 # number of writebacks +system.cpu.dtb_walker_cache.writebacks 43317 # number of writebacks system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dtb_walker_cache.ReadReq_mshr_misses 144294 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses 144294 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses 144294 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses 135405 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses 135405 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses 135405 # number of overall MSHR misses system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1562734500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1562734500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1562734500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1474266000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1474266000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1474266000 # number of overall MSHR miss cycles system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.492937 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.482327 # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.492937 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.482327 # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.492937 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.482327 # mshr miss rate for overall accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10830.211235 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10830.211235 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10830.211235 # average overall mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10887.825413 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10887.825413 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10887.825413 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1661784 # number of replacements -system.cpu.dcache.tagsinuse 511.998465 # Cycle average of tags in use -system.cpu.dcache.total_refs 18023326 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1662296 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.842429 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1651577 # number of replacements +system.cpu.dcache.tagsinuse 511.998478 # Cycle average of tags in use +system.cpu.dcache.total_refs 17702284 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1652089 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.715091 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 13135000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.998465 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 511.998478 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999997 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 11452816 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11452816 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 6548488 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6548488 # number of WriteReq hits -system.cpu.dcache.demand_hits::0 18001304 # number of demand (read+write) hits +system.cpu.dcache.ReadReq_hits::0 11207304 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11207304 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 6473053 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6473053 # number of WriteReq hits +system.cpu.dcache.demand_hits::0 17680357 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18001304 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 18001304 # number of overall hits +system.cpu.dcache.demand_hits::total 17680357 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 17680357 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 18001304 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 2480783 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2480783 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 1873809 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1873809 # number of WriteReq misses -system.cpu.dcache.demand_misses::0 4354592 # number of demand (read+write) misses +system.cpu.dcache.overall_hits::total 17680357 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 2476228 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2476228 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 1855910 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1855910 # number of WriteReq misses +system.cpu.dcache.demand_misses::0 4332138 # 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number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 8422297 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8422297 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 22355896 # number of demand (read+write) accesses +system.cpu.dcache.overall_misses::total 4332138 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 37330141500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 63200421145 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 100530562645 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 100530562645 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 13683532 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13683532 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 8328963 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8328963 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 22012495 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 22355896 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 22355896 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 22012495 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 22012495 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 22355896 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.178043 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.222482 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::0 0.194785 # miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 22012495 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.180964 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.222826 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::0 0.196804 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.194785 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.196804 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 15093.125840 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 15075.405617 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 33889.510531 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 34053.602354 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 23181.331302 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 23205.761831 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 23181.331302 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 23205.761831 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1084772653 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6673000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 73247 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 392 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14809.789520 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 17022.959184 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 1081837152 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5932000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 72874 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 266 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14845.310426 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22300.751880 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1548151 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1110544 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1577040 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2687584 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2687584 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1370239 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 296769 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1667008 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1667008 # number of overall MSHR misses +system.cpu.dcache.writebacks 1542574 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1113618 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1561886 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2675504 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2675504 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1362610 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 294024 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1656634 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1656634 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 18185435000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 9767723153 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 27953158153 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 27953158153 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 86946921000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1385819000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 88332740000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098341 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 18053047500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 9720000152 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 27773047652 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 27773047652 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 86987590000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1400743000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 88388333000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.099580 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035236 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035301 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.074567 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.075259 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.074567 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.075259 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13271.724860 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32913.556177 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 16768.460711 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 16768.460711 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13248.873485 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 33058.526352 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 16764.745654 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 16764.745654 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini index d17aac738..9bd7bf3ba 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -500,9 +500,9 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/arm/linux/mcf +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/arm/scratch/sysexplr/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout index eb9dd7dcf..67dc34515 100755 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 19:27:45 -gem5 started Aug 17 2011 21:36:25 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 12:27:58 +gem5 started Aug 20 2011 12:28:18 +gem5 executing on zizzer command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -25,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 34005216000 because target called exit() +Exiting @ tick 33049447500 because target called exit() diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt index c921edf2f..acf1a3733 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.034005 # Number of seconds simulated -sim_ticks 34005216000 # Number of ticks simulated +sim_seconds 0.033049 # Number of seconds simulated +sim_ticks 33049447500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105088 # Simulator instruction rate (inst/s) -host_tick_rate 39162055 # Simulator tick rate (ticks/s) -host_mem_usage 396412 # Number of bytes of host memory used -host_seconds 868.32 # Real time elapsed on the host -sim_insts 91249660 # Number of instructions simulated +host_inst_rate 142392 # Simulator instruction rate (inst/s) +host_tick_rate 51572715 # Simulator tick rate (ticks/s) +host_mem_usage 349636 # Number of bytes of host memory used +host_seconds 640.83 # Real time elapsed on the host +sim_insts 91249665 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,300 +51,300 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 68010433 # number of cpu cycles simulated +system.cpu.numCycles 66098896 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 28218889 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22621042 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1414269 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 25157948 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 24123842 # Number of BTB hits +system.cpu.BPredUnit.lookups 27480852 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 21948199 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1405962 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 24356195 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 23358870 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 112560 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 12935 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15977103 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 135154938 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28218889 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24236402 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 33504566 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5937953 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 14110938 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 118630 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 12953 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15359689 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 131196018 # Number of instructions fetch has processed +system.cpu.fetch.Branches 27480852 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23477500 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 32529765 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5482056 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 14124387 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 185 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 15277206 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 405179 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 67980048 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.009106 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.742708 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 126 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14730221 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 368829 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 66068188 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.007516 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.747063 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 34529861 50.79% 50.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6742939 9.92% 60.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5949333 8.75% 69.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5005104 7.36% 76.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2886229 4.25% 81.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1784892 2.63% 83.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1586062 2.33% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3028551 4.46% 90.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6467077 9.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 33589573 50.84% 50.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6678757 10.11% 60.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5691945 8.62% 69.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4809462 7.28% 76.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2791705 4.23% 81.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1680164 2.54% 83.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1554358 2.35% 85.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2929699 4.43% 90.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6342525 9.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 67980048 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.414920 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.987268 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 18656916 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 12586941 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31365316 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1012619 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4358256 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4495895 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 29408 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 132644868 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 31349 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4358256 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 20449450 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1113784 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8328298 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 30545374 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3184886 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 128012570 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 287918 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1870803 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 19 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 149350454 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 557406814 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 557400643 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6171 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107429079 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 41921370 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 670708 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 672640 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 7503691 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29849221 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6023274 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1356342 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 647782 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 119728179 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 639242 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107493963 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 101688 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 28653338 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 69345788 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 84885 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 67980048 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.581258 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.754962 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 66068188 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.415754 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.984844 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17938862 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 12617377 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 30503596 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 985227 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4023126 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4444811 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 31491 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 129102519 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 31918 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4023126 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 19654279 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1111044 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8373205 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 29732459 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3174075 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 125001528 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 255212 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1879877 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 11 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 145677643 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 544340805 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 544335582 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5223 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107429087 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 38248551 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 647769 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 649953 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 7510284 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29313185 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5861466 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1226589 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 648810 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 117406606 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 634842 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 106217024 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 74725 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26332148 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 63315965 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 80484 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 66068188 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.607688 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.762772 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 25411198 37.38% 37.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14672249 21.58% 58.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10091036 14.84% 73.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 8117515 11.94% 85.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4245876 6.25% 91.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2261871 3.33% 95.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2477690 3.64% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 492806 0.72% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 209807 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24256842 36.71% 36.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14242052 21.56% 58.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9853567 14.91% 73.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 8048166 12.18% 85.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4234412 6.41% 91.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2296375 3.48% 95.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2457048 3.72% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 476279 0.72% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 203447 0.31% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 67980048 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 66068188 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 55128 10.57% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.01% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 195567 37.49% 48.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 270861 51.93% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 53590 10.28% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.01% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.28% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 193594 37.13% 47.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 274209 52.59% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 75624393 70.35% 70.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11037 0.01% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 142 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 216 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26489525 24.64% 95.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5368647 4.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74732015 70.36% 70.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10984 0.01% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 117 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 183 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26127838 24.60% 94.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5345884 5.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107493963 # Type of FU issued -system.cpu.iq.rate 1.580551 # Inst issue rate -system.cpu.iq.fu_busy_cnt 521583 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.004852 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 283590457 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 149134912 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 103313429 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 788 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1184 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 356 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 108015155 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 391 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 359898 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 106217024 # Type of FU issued +system.cpu.iq.rate 1.606941 # Inst issue rate +system.cpu.iq.fu_busy_cnt 521420 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.004909 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 279097712 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144373136 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102515328 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 669 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1008 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 309 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 106738111 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 333 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 366236 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7273393 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 45135 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 115664 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1276570 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6737356 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 42339 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 715 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1114761 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 30487 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 30343 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4358256 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 193721 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 31151 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 120406197 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 800153 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29849221 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6023274 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 634379 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 11264 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1216 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 115664 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1297109 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 208567 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1505676 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 105540592 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 26056532 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1953371 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4023126 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 183340 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 29024 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118080266 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 812187 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29313185 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5861466 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 629989 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 9572 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1070 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 715 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1280450 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 209997 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1490447 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104523417 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25726566 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1693607 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 38776 # number of nop insts executed -system.cpu.iew.exec_refs 31276826 # number of memory reference insts executed -system.cpu.iew.exec_branches 21265794 # Number of branches executed -system.cpu.iew.exec_stores 5220294 # Number of stores executed -system.cpu.iew.exec_rate 1.551829 # Inst execution rate -system.cpu.iew.wb_sent 103749789 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 103313785 # cumulative count of insts written-back -system.cpu.iew.wb_producers 60697927 # num instructions producing a value -system.cpu.iew.wb_consumers 97489409 # num instructions consuming a value +system.cpu.iew.exec_nop 38818 # number of nop insts executed +system.cpu.iew.exec_refs 30937872 # number of memory reference insts executed +system.cpu.iew.exec_branches 21209374 # Number of branches executed +system.cpu.iew.exec_stores 5211306 # Number of stores executed +system.cpu.iew.exec_rate 1.581319 # Inst execution rate +system.cpu.iew.wb_sent 102947388 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102515637 # cumulative count of insts written-back +system.cpu.iew.wb_producers 60320212 # num instructions producing a value +system.cpu.iew.wb_consumers 97098710 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.519087 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.622610 # average fanout of values written-back +system.cpu.iew.wb_rate 1.550943 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.621226 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 91262269 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 29143453 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 554357 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1398047 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 63621793 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.434450 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.199830 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 91262274 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26817270 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 554358 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1387669 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 62045063 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.470903 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.226778 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 29598088 46.52% 46.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16825513 26.45% 72.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5309975 8.35% 81.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3950826 6.21% 87.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2115946 3.33% 90.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 645775 1.02% 91.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 466588 0.73% 92.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 200515 0.32% 92.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4508567 7.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 28329843 45.66% 45.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16548650 26.67% 72.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5280214 8.51% 80.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3902195 6.29% 87.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2034976 3.28% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 672623 1.08% 91.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 530029 0.85% 92.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 208846 0.34% 92.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4537687 7.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 63621793 # Number of insts commited each cycle -system.cpu.commit.count 91262269 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 62045063 # Number of insts commited each cycle +system.cpu.commit.count 91262274 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27322531 # Number of memory references committed -system.cpu.commit.loads 22575827 # Number of loads committed +system.cpu.commit.refs 27322533 # Number of memory references committed +system.cpu.commit.loads 22575828 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18722421 # Number of branches committed +system.cpu.commit.branches 18722422 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72533122 # Number of committed integer instructions. +system.cpu.commit.int_insts 72533126 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4508567 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4537687 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 179513214 # The number of ROB reads -system.cpu.rob.rob_writes 245183550 # The number of ROB writes -system.cpu.timesIdled 1513 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30385 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 91249660 # Number of Instructions Simulated -system.cpu.committedInsts_total 91249660 # Number of Instructions Simulated -system.cpu.cpi 0.745323 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.745323 # CPI: Total CPI of All Threads -system.cpu.ipc 1.341701 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.341701 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 501285464 # number of integer regfile reads -system.cpu.int_regfile_writes 121975389 # number of integer regfile writes -system.cpu.fp_regfile_reads 172 # number of floating regfile reads -system.cpu.fp_regfile_writes 453 # number of floating regfile writes -system.cpu.misc_regfile_reads 189360420 # number of misc regfile reads -system.cpu.misc_regfile_writes 11504 # number of misc regfile writes -system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 610.965414 # Cycle average of tags in use -system.cpu.icache.total_refs 15276277 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 724 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 21099.830110 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 175581186 # The number of ROB reads +system.cpu.rob.rob_writes 240196081 # The number of ROB writes +system.cpu.timesIdled 1543 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30708 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 91249665 # Number of Instructions Simulated +system.cpu.committedInsts_total 91249665 # Number of Instructions Simulated +system.cpu.cpi 0.724374 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.724374 # CPI: Total CPI of All Threads +system.cpu.ipc 1.380502 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.380502 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 496839540 # number of integer regfile reads +system.cpu.int_regfile_writes 120902305 # number of integer regfile writes +system.cpu.fp_regfile_reads 158 # number of floating regfile reads +system.cpu.fp_regfile_writes 392 # number of floating regfile writes +system.cpu.misc_regfile_reads 184716876 # number of misc regfile reads +system.cpu.misc_regfile_writes 11506 # number of misc regfile writes +system.cpu.icache.replacements 2 # number of replacements +system.cpu.icache.tagsinuse 613.066905 # Cycle average of tags in use +system.cpu.icache.total_refs 14729300 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 718 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 20514.345404 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 610.965414 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.298323 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 15276277 # number of ReadReq hits -system.cpu.icache.demand_hits 15276277 # number of demand (read+write) hits -system.cpu.icache.overall_hits 15276277 # number of overall hits -system.cpu.icache.ReadReq_misses 929 # number of ReadReq misses -system.cpu.icache.demand_misses 929 # number of demand (read+write) misses -system.cpu.icache.overall_misses 929 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 32705500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 32705500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 32705500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 15277206 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 15277206 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 15277206 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000061 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000061 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000061 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35205.059203 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35205.059203 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35205.059203 # average overall miss latency +system.cpu.icache.occ_blocks::0 613.066905 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.299349 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 14729300 # number of ReadReq hits +system.cpu.icache.demand_hits 14729300 # number of demand (read+write) hits +system.cpu.icache.overall_hits 14729300 # number of overall hits +system.cpu.icache.ReadReq_misses 921 # number of ReadReq misses +system.cpu.icache.demand_misses 921 # number of demand (read+write) misses +system.cpu.icache.overall_misses 921 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 32465000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 32465000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 32465000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 14730221 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 14730221 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 14730221 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35249.728556 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35249.728556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35249.728556 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,139 +354,139 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 205 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 205 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 205 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 724 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 724 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 724 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 203 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 203 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 203 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 718 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 718 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 718 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 24957500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 24957500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 24957500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 24779500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 24779500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 24779500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000047 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000047 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000047 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34471.685083 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34471.685083 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34471.685083 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000049 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000049 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000049 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34511.838440 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34511.838440 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34511.838440 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943463 # number of replacements -system.cpu.dcache.tagsinuse 3549.969044 # Cycle average of tags in use -system.cpu.dcache.total_refs 29157181 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947559 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 30.770834 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12923369000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3549.969044 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.866692 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 24585710 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 4558997 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 6727 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 5747 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 29144707 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 29144707 # number of overall hits -system.cpu.dcache.ReadReq_misses 969494 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 175984 # number of WriteReq misses +system.cpu.dcache.replacements 943500 # number of replacements +system.cpu.dcache.tagsinuse 3561.430485 # Cycle average of tags in use +system.cpu.dcache.total_refs 28801207 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947596 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 30.393973 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12279149000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 3561.430485 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.869490 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 24229442 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 4559293 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 6724 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 5748 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 28788735 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 28788735 # number of overall hits +system.cpu.dcache.ReadReq_misses 990132 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 175688 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1145478 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1145478 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5401004500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 4496326950 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 126500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 9897331450 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 9897331450 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 25555204 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 1165820 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1165820 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5482674500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4505328405 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 124500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 9988002905 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 9988002905 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 25219574 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 6734 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 5747 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 30290185 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 30290185 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.037937 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.037167 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_accesses 6731 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 5748 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 29954555 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 29954555 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.039260 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.037104 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate 0.001040 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.037817 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.037817 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 5570.951961 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 25549.634910 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 18071.428571 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 8640.350535 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 8640.350535 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23178020 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate 0.038920 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.038920 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 5537.316742 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 25643.916517 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 17785.714286 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 8567.362805 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 8567.362805 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23285977 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 8098 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8139 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2862.190664 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2861.036614 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 942900 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 67979 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 129940 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 942954 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 87074 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 131149 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 197919 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 197919 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 901515 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 46044 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 947559 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 947559 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 218223 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 218223 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 903058 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 44539 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 947597 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 947597 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2251061000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1080314076 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 3331375076 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 3331375076 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2256691000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1081795530 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3338486530 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3338486530 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.035277 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009724 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.031283 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.031283 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2496.975647 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23462.646078 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3515.744219 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3515.744219 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.035808 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.031634 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.031634 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2498.943589 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24288.725162 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3523.107956 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3523.107956 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 745 # number of replacements -system.cpu.l2cache.tagsinuse 9143.143652 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1595891 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15573 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 102.478071 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 742 # number of replacements +system.cpu.l2cache.tagsinuse 9256.207068 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1596737 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 15558 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 102.631251 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 398.185089 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 8744.958563 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.012152 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.266875 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 901164 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 942900 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 31521 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 932685 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 932685 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1058 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::0 391.956879 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 8864.250189 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.011962 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.270515 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 901452 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 942954 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 31278 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 932730 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 932730 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1045 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 14540 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 15598 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 15598 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 36283000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 498900000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 535183000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 535183000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 902222 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 942900 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 46061 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 948283 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 948283 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.001173 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.315668 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.016449 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.016449 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34293.950851 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34312.242091 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34311.001410 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34311.001410 # average overall miss latency +system.cpu.l2cache.demand_misses 15585 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 15585 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 35800500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 498909000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 534709500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 534709500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 902497 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 942954 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 45818 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 948315 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 948315 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.001158 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.317343 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.016434 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.016434 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34258.851675 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34312.861073 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34309.239654 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34309.239654 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -499,24 +499,24 @@ system.cpu.l2cache.writebacks 32 # nu system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1048 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 1035 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 14540 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 15588 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 15588 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 15575 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 15575 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 32620500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 451750500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 484371000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 484371000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 32188500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 451730000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 483918500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 483918500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001162 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.315668 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.016438 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.016438 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31126.431298 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.497937 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31073.325635 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31073.325635 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001147 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317343 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.016424 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.016424 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31100 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31068.088033 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31070.208668 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31070.208668 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini index aaea60ae0..df2fb6f73 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -500,9 +500,9 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/x86/linux/mcf +executable=/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/arm/scratch/sysexplr/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout index 796b5db5e..d1aeffbca 100755 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 17:25:41 -gem5 started Aug 17 2011 17:30:37 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 13:24:14 +gem5 started Aug 20 2011 13:24:28 +gem5 executing on zizzer command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -25,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 71354418000 because target called exit() +Exiting @ tick 70374234500 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt index 542fef85a..f17fe7434 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,251 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.071354 # Number of seconds simulated -sim_ticks 71354418000 # Number of ticks simulated +sim_seconds 0.070374 # Number of seconds simulated +sim_ticks 70374234500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 121216 # Simulator instruction rate (inst/s) -host_tick_rate 31091054 # Simulator tick rate (ticks/s) -host_mem_usage 393776 # Number of bytes of host memory used -host_seconds 2295.01 # Real time elapsed on the host +host_inst_rate 169063 # Simulator instruction rate (inst/s) +host_tick_rate 42767879 # Simulator tick rate (ticks/s) +host_mem_usage 346452 # Number of bytes of host memory used +host_seconds 1645.49 # Real time elapsed on the host sim_insts 278192519 # Number of instructions simulated system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 142708837 # number of cpu cycles simulated +system.cpu.numCycles 140748470 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 38713050 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 38713050 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1277784 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 34149959 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 33632947 # Number of BTB hits +system.cpu.BPredUnit.lookups 37906853 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 37906853 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1330176 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 33468761 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 32955372 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29563972 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 207959070 # Number of instructions fetch has processed -system.cpu.fetch.Branches 38713050 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33632947 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 64671203 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11251281 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37585887 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 29094074 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 203757407 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37906853 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32955372 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 63225813 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 10352620 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 38317432 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 97 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 28742973 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 228078 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 141556039 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.590408 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.296325 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 28270666 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 203655 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 139622279 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.575042 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.293353 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 79448784 56.13% 56.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3733414 2.64% 58.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2922001 2.06% 60.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4489594 3.17% 64.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6936058 4.90% 68.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5469177 3.86% 72.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 7685058 5.43% 78.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4534397 3.20% 81.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 26337556 18.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 78878326 56.49% 56.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3468234 2.48% 58.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2811542 2.01% 60.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4524513 3.24% 64.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6755323 4.84% 69.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5317016 3.81% 72.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 7687744 5.51% 78.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4301095 3.08% 81.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 25878486 18.53% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 141556039 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.271273 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.457226 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 42383946 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 28100231 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 53949523 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7387481 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9734858 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 362029152 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 9734858 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 49345988 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4251907 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6895 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 54198746 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24017645 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 357077595 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 112284 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20035490 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 320906324 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 879462898 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 879458894 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4004 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 139622279 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.269323 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.447670 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 41959628 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 28656621 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 52572729 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7448460 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8984841 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 355072137 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 8984841 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 48879402 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4457870 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6893 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 52910993 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24382280 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 350563031 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 104227 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20384891 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 314779048 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 862154595 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 862151489 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3106 # Number of floating rename lookups system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 72562132 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 66434856 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 479 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 472 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 56213524 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 115636696 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 38304742 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 48747327 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8476101 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 349796606 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 465 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 319480009 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 127874 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 71460780 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 105775967 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 141556039 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.256915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.760467 # Number of insts issued each cycle +system.cpu.rename.skidInsts 56483579 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 112824537 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 37669092 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 48262856 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8162457 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343955075 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 466 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 316373550 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 98329 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 65563048 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 93813941 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 20 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 139622279 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.265925 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.753143 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 32928700 23.26% 23.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 18859354 13.32% 36.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25409770 17.95% 54.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 30153045 21.30% 75.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18699176 13.21% 89.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 10380312 7.33% 96.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3284045 2.32% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1793650 1.27% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 47987 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 31939796 22.88% 22.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 18447556 13.21% 36.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25584563 18.32% 54.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 29944678 21.45% 75.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18447649 13.21% 89.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 10291416 7.37% 96.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3138355 2.25% 98.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1781100 1.28% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 47166 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 141556039 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 139622279 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 25871 1.36% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1792047 94.50% 95.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78518 4.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 26426 1.39% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1802884 94.84% 96.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 71697 3.77% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 16711 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 181286722 56.74% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 231 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103851207 32.51% 89.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34325138 10.74% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 180370396 57.01% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 163 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101485830 32.08% 89.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34500450 10.90% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 319480009 # Type of FU issued -system.cpu.iq.rate 2.238684 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1896436 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005936 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 782539275 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 421630860 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 314706696 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1092 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2558 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 444 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 321359193 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 541 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 45621060 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 316373550 # Type of FU issued +system.cpu.iq.rate 2.247794 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1901007 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006009 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 774367858 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 409550255 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 312670753 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 857 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1937 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 344 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 318257421 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 425 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 45906074 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 24857308 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 124101 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 396603 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6864991 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 22045149 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 125133 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34222 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6229341 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2744 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 15359 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2799 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 15405 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9734858 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 919734 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 96297 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 349797071 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 26061 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 115636696 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 38304742 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6174 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 48786 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 396603 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1201294 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 194628 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1395922 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 317091801 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 103103021 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2388208 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8984841 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 901233 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 88686 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343955541 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 25713 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 112824537 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 37669092 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 466 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1563 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 48845 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34222 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1237215 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 226162 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1463377 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 314277739 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100905928 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2095811 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 137049691 # number of memory reference insts executed -system.cpu.iew.exec_branches 31753831 # Number of branches executed -system.cpu.iew.exec_stores 33946670 # Number of stores executed -system.cpu.iew.exec_rate 2.221949 # Inst execution rate -system.cpu.iew.wb_sent 315540216 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 314707140 # cumulative count of insts written-back -system.cpu.iew.wb_producers 234790765 # num instructions producing a value -system.cpu.iew.wb_consumers 320680424 # num instructions consuming a value +system.cpu.iew.exec_refs 134999174 # number of memory reference insts executed +system.cpu.iew.exec_branches 31825957 # Number of branches executed +system.cpu.iew.exec_stores 34093246 # Number of stores executed +system.cpu.iew.exec_rate 2.232903 # Inst execution rate +system.cpu.iew.wb_sent 313326251 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 312671097 # cumulative count of insts written-back +system.cpu.iew.wb_producers 232527981 # num instructions producing a value +system.cpu.iew.wb_consumers 318649991 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.205239 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.732164 # average fanout of values written-back +system.cpu.iew.wb_rate 2.221488 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.729729 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 71609181 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 65767670 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1277798 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 131821181 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.110378 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.644254 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1330190 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 130637438 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.129501 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.662910 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 51293193 38.91% 38.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 24103484 18.28% 57.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 17099155 12.97% 70.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12472180 9.46% 79.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3629365 2.75% 82.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3499755 2.65% 85.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3079633 2.34% 87.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1175176 0.89% 88.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15469240 11.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 50443323 38.61% 38.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 24364180 18.65% 57.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 16505841 12.63% 69.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12375620 9.47% 79.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3710115 2.84% 82.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3458000 2.65% 84.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2751645 2.11% 86.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1180245 0.90% 87.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15848469 12.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 131821181 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 130637438 # Number of insts commited each cycle system.cpu.commit.count 278192519 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 122219139 # Number of memory references committed @@ -255,49 +255,49 @@ system.cpu.commit.branches 29309710 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186227 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15469240 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15848469 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 466153641 # The number of ROB reads -system.cpu.rob.rob_writes 709355946 # The number of ROB writes -system.cpu.timesIdled 34118 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1152798 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 458749158 # The number of ROB reads +system.cpu.rob.rob_writes 696922141 # The number of ROB writes +system.cpu.timesIdled 33627 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1126191 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 278192519 # Number of Instructions Simulated system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated -system.cpu.cpi 0.512986 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.512986 # CPI: Total CPI of All Threads -system.cpu.ipc 1.949371 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.949371 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 558552760 # number of integer regfile reads -system.cpu.int_regfile_writes 282337727 # number of integer regfile writes -system.cpu.fp_regfile_reads 537 # number of floating regfile reads -system.cpu.fp_regfile_writes 378 # number of floating regfile writes -system.cpu.misc_regfile_reads 203729290 # number of misc regfile reads -system.cpu.icache.replacements 67 # number of replacements -system.cpu.icache.tagsinuse 827.771382 # Cycle average of tags in use -system.cpu.icache.total_refs 28741656 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1030 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 27904.520388 # Average number of references to valid blocks. +system.cpu.cpi 0.505939 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.505939 # CPI: Total CPI of All Threads +system.cpu.ipc 1.976523 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.976523 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 555004477 # number of integer regfile reads +system.cpu.int_regfile_writes 279973081 # number of integer regfile writes +system.cpu.fp_regfile_reads 378 # number of floating regfile reads +system.cpu.fp_regfile_writes 284 # number of floating regfile writes +system.cpu.misc_regfile_reads 201255053 # number of misc regfile reads +system.cpu.icache.replacements 68 # number of replacements +system.cpu.icache.tagsinuse 824.627975 # Cycle average of tags in use +system.cpu.icache.total_refs 28269362 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1028 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 27499.379377 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 827.771382 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.404185 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 28741656 # number of ReadReq hits -system.cpu.icache.demand_hits 28741656 # number of demand (read+write) hits -system.cpu.icache.overall_hits 28741656 # number of overall hits -system.cpu.icache.ReadReq_misses 1317 # number of ReadReq misses -system.cpu.icache.demand_misses 1317 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1317 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 47419000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 47419000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 47419000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 28742973 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 28742973 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 28742973 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 824.627975 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.402650 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 28269362 # number of ReadReq hits +system.cpu.icache.demand_hits 28269362 # number of demand (read+write) hits +system.cpu.icache.overall_hits 28269362 # number of overall hits +system.cpu.icache.ReadReq_misses 1304 # number of ReadReq misses +system.cpu.icache.demand_misses 1304 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1304 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 47096500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 47096500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 47096500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 28270666 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 28270666 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 28270666 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000046 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000046 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000046 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36005.315110 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36005.315110 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36005.315110 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 36116.947853 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36116.947853 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36116.947853 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -307,166 +307,166 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 286 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 286 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 286 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1031 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1031 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1031 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 275 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 275 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 275 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1029 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1029 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1029 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 36294500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 36294500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 36294500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 36215000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 36215000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 36215000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000036 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35203.200776 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35203.200776 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35203.200776 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35194.363460 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35194.363460 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35194.363460 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2073043 # number of replacements -system.cpu.dcache.tagsinuse 4075.910712 # Cycle average of tags in use -system.cpu.dcache.total_refs 86335085 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2077139 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 41.564423 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 24475195000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4075.910712 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995095 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 55138633 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 31196443 # number of WriteReq hits -system.cpu.dcache.demand_hits 86335076 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 86335076 # number of overall hits -system.cpu.dcache.ReadReq_misses 2261245 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 243308 # number of WriteReq misses -system.cpu.dcache.demand_misses 2504553 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2504553 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 14586168500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 4411412645 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 18997581145 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 18997581145 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 57399878 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2073072 # number of replacements +system.cpu.dcache.tagsinuse 4076.002534 # Cycle average of tags in use +system.cpu.dcache.total_refs 83850634 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2077168 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 40.367767 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 23897616000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4076.002534 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995118 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 52653882 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 31196743 # number of WriteReq hits +system.cpu.dcache.demand_hits 83850625 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 83850625 # number of overall hits +system.cpu.dcache.ReadReq_misses 2263157 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 243008 # number of WriteReq misses +system.cpu.dcache.demand_misses 2506165 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2506165 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 14623728000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4401886592 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 19025614592 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 19025614592 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 54917039 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 88839629 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 88839629 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.039395 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.007739 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.028192 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.028192 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 6450.503373 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 18130.980671 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 7585.218259 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 7585.218259 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 284500 # number of cycles access was blocked +system.cpu.dcache.demand_accesses 86356790 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 86356790 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.041210 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.007729 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.029021 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.029021 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 6461.649810 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 18114.163287 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 7591.525136 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 7591.525136 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 296000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 87 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 93 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3270.114943 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3182.795699 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1447109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 289614 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 137796 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 427410 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 427410 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1971631 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 105512 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2077143 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2077143 # number of overall MSHR misses +system.cpu.dcache.writebacks 1447092 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 291450 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 137543 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 428993 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 428993 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1971707 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 105465 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2077172 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2077172 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5604635500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1879175645 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7483811145 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7483811145 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 5599733000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1876757592 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7476490592 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7476490592 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.034349 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003356 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.023381 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.023381 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2842.639165 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17810.065632 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3602.934966 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3602.934966 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.035903 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.003355 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.024053 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.024053 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2840.043171 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17795.075068 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3599.360377 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3599.360377 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 49075 # number of replacements -system.cpu.l2cache.tagsinuse 18765.136445 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3317892 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 77084 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 43.042551 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 49070 # number of replacements +system.cpu.l2cache.tagsinuse 18849.812777 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3318008 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 77081 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 43.045731 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 6711.152997 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 12053.983448 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.204808 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.367858 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1938063 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1447109 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 63578 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 2001641 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2001641 # number of overall hits -system.cpu.l2cache.ReadReq_misses 34491 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::0 6745.826593 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 12103.986183 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.205866 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.369384 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1938133 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 1447092 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 63539 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 2001672 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2001672 # number of overall hits +system.cpu.l2cache.ReadReq_misses 34492 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 42040 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 76531 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 76531 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1179737500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1440022500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 2619760000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 2619760000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1972554 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 1447109 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses 42035 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 76527 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 76527 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1179607000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1438839000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 2618446000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 2618446000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1972625 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 1447092 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 105618 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 2078172 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 2078172 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses 105574 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2078199 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2078199 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate 0.017485 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.398038 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.036826 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.036826 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34204.212693 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34253.627498 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34231.357228 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34231.357228 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_miss_rate 0.398157 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.036824 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.036824 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34199.437551 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34229.546806 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34215.976061 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34215.976061 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 39000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2884.615385 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2785.714286 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 29187 # number of writebacks +system.cpu.l2cache.writebacks 29193 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 34491 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 34492 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 42040 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 76531 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 76531 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 42035 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 76527 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 76527 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1069946000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1069993000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1307849500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2377795500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2377795500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1307215500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2377208500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2377208500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017485 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.398038 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.036826 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.036826 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.019976 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.398157 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.036824 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.036824 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.483242 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31109.645576 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31069.703780 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31069.703780 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31098.263352 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31063.657271 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31063.657271 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini index 0b5a9f54e..e653f0d44 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini @@ -500,9 +500,9 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/arm/linux/parser +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser gid=100 -input=/arm/scratch/sysexplr/dist/cpu2000/data/parser/mdred/input/parser.in +input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/20.parser/ref/arm/linux/o3-timing/simout index 76519111d..11517aaea 100755 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 19:27:45 -gem5 started Aug 17 2011 19:29:05 -gem5 executing on nadc-0388 +gem5 compiled Sep 11 2011 21:12:14 +gem5 started Sep 11 2011 22:42:17 +gem5 executing on u200439-lin.austin.arm.com command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -69,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 279789017500 because target called exit() +Exiting @ tick 277977002000 because target called exit() diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt index ce0258252..a35c3c833 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.279789 # Number of seconds simulated -sim_ticks 279789017500 # Number of ticks simulated +sim_seconds 0.277977 # Number of seconds simulated +sim_ticks 277977002000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 82238 # Simulator instruction rate (inst/s) -host_tick_rate 40132128 # Simulator tick rate (ticks/s) -host_mem_usage 268396 # Number of bytes of host memory used -host_seconds 6971.70 # Real time elapsed on the host -sim_insts 573340737 # Number of instructions simulated +host_inst_rate 50801 # Simulator instruction rate (inst/s) +host_tick_rate 24630434 # Simulator tick rate (ticks/s) +host_mem_usage 268512 # Number of bytes of host memory used +host_seconds 11285.92 # Real time elapsed on the host +sim_insts 573340817 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,299 +51,299 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 559578036 # number of cpu cycles simulated +system.cpu.numCycles 555954005 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 229313741 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 182941703 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18381450 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 193404656 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 160578997 # Number of BTB hits +system.cpu.BPredUnit.lookups 228168556 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 182073516 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 18360369 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 192570670 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 159873716 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 11881056 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2583910 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 158920845 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1008979483 # Number of instructions fetch has processed -system.cpu.fetch.Branches 229313741 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 172460053 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 261292498 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 78073694 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 78434846 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 11766939 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2589198 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 157542477 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1002347382 # Number of instructions fetch has processed +system.cpu.fetch.Branches 228168556 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 171640655 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 259558013 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 76911240 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 78784930 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 86 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 74310 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 146143180 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4810109 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 555823153 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.154722 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.836930 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 75608 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 144858558 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4692724 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 552173964 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.153531 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.835452 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 294542931 52.99% 52.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24434943 4.40% 57.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 41500058 7.47% 64.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 40458286 7.28% 72.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 42543437 7.65% 79.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15388331 2.77% 82.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 18846128 3.39% 85.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 16230001 2.92% 88.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 61879038 11.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 292628171 53.00% 53.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24182032 4.38% 57.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 41208027 7.46% 64.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 40287755 7.30% 72.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 42593934 7.71% 79.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15362741 2.78% 82.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 18471004 3.35% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 15875720 2.88% 88.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 61564580 11.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 555823153 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.409798 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.803108 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 176155270 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 73642136 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 243542004 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5471546 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 57012197 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33378674 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 103333 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1139235628 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 221531 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 57012197 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 192762447 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6395244 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52127193 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 232252715 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15273357 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1073234487 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1226 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2982497 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8850274 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 56 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1193556306 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4743331903 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4743328950 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2953 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 672198616 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 521357685 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2768330 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2768349 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 48304499 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 196270626 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 121806649 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 17302899 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 13929275 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 937590667 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4537458 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 765577672 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3452362 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 365845767 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1020513301 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 659897 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 555823153 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.377376 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.646867 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 552173964 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.410409 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.802932 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 174643217 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 74003655 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 241825434 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5575388 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 56126270 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33116303 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 100775 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1131397141 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 219753 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 56126270 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 191113879 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6444669 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52172693 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 230777280 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15539173 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1066388511 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1227 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2971665 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 9137935 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 123 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1187101757 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4711515581 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4711512464 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3117 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 672198744 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 514903008 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2758299 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2758344 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 48904017 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 194788235 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 120640917 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 16446877 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 13823038 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 932596874 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4516730 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 763493806 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3302626 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 360793671 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1004885077 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 639153 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 552173964 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.382705 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.650964 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 247650578 44.56% 44.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 96155335 17.30% 61.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 83204777 14.97% 76.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 61794788 11.12% 87.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 37799799 6.80% 94.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16279306 2.93% 97.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7068984 1.27% 98.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4337899 0.78% 99.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1531687 0.28% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 245578205 44.47% 44.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 95260536 17.25% 61.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 82729163 14.98% 76.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 61462148 11.13% 87.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 37755177 6.84% 94.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16395168 2.97% 97.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7099577 1.29% 98.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4357430 0.79% 99.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1536560 0.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 555823153 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 552173964 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 140807 1.12% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6799143 54.23% 55.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5597920 44.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 144550 1.16% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6747694 54.11% 55.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5577677 44.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 513475935 67.07% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 381036 0.05% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 132 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 171848719 22.45% 89.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79871847 10.43% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 512546383 67.13% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 380050 0.05% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 132 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 170906603 22.38% 89.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79660635 10.43% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 765577672 # Type of FU issued -system.cpu.iq.rate 1.368134 # Inst issue rate -system.cpu.iq.fu_busy_cnt 12537870 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016377 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2102968429 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1308573624 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 707132694 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 763493806 # Type of FU issued +system.cpu.iq.rate 1.373304 # Inst issue rate +system.cpu.iq.fu_busy_cnt 12469921 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016333 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2094933823 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1297974964 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 705382252 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 300 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 418 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 456 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 778115390 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 775963575 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 152 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8455252 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 8509313 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 69497780 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 53390 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 614044 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 64202883 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 68015373 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 52063 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 72908 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 63037135 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 28348 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 333 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 28343 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 323 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 57012197 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2686334 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 121984 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 951489929 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 12656652 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 196270626 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 121806649 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2752356 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 48623 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7315 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 614044 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 18618092 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6141777 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 24759869 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 733934042 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 162731362 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 31643630 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 56126270 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2680601 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 121752 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 946450192 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 12430419 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 194788235 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 120640917 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2741935 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 45812 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7404 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 72908 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 18589508 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6131708 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 24721216 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 732040071 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 161905826 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 31453735 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9361804 # number of nop insts executed -system.cpu.iew.exec_refs 234660567 # number of memory reference insts executed -system.cpu.iew.exec_branches 147664615 # Number of branches executed -system.cpu.iew.exec_stores 71929205 # Number of stores executed -system.cpu.iew.exec_rate 1.311585 # Inst execution rate -system.cpu.iew.wb_sent 721950956 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 707132710 # cumulative count of insts written-back -system.cpu.iew.wb_producers 399859111 # num instructions producing a value -system.cpu.iew.wb_consumers 707515910 # num instructions consuming a value +system.cpu.iew.exec_nop 9336588 # number of nop insts executed +system.cpu.iew.exec_refs 233639604 # number of memory reference insts executed +system.cpu.iew.exec_branches 147368049 # Number of branches executed +system.cpu.iew.exec_stores 71733778 # Number of stores executed +system.cpu.iew.exec_rate 1.316728 # Inst execution rate +system.cpu.iew.wb_sent 720193208 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 705382268 # cumulative count of insts written-back +system.cpu.iew.wb_producers 398990171 # num instructions producing a value +system.cpu.iew.wb_consumers 706117751 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.263689 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.565159 # average fanout of values written-back +system.cpu.iew.wb_rate 1.268778 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.565048 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 574684621 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 376818510 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3877561 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 20574438 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 498810957 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.152109 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.870885 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 574684701 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 371780538 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3877577 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 20554122 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 496047695 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.158527 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.880172 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 264965751 53.12% 53.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 115315817 23.12% 76.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 44565199 8.93% 85.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 20246779 4.06% 89.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19896261 3.99% 93.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7328254 1.47% 94.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7611881 1.53% 96.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3447651 0.69% 96.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15433364 3.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 262785164 52.98% 52.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 115198259 23.22% 76.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 44158877 8.90% 85.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 20159823 4.06% 89.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19759049 3.98% 93.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7211981 1.45% 94.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7550461 1.52% 96.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3502296 0.71% 96.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15721785 3.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 498810957 # Number of insts commited each cycle -system.cpu.commit.count 574684621 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 496047695 # Number of insts commited each cycle +system.cpu.commit.count 574684701 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 184376611 # Number of memory references committed -system.cpu.commit.loads 126772845 # Number of loads committed +system.cpu.commit.refs 184376643 # Number of memory references committed +system.cpu.commit.loads 126772861 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 120192030 # Number of branches committed +system.cpu.commit.branches 120192046 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 473700857 # Number of committed integer instructions. +system.cpu.commit.int_insts 473700921 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15433364 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15721785 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1434873586 # The number of ROB reads -system.cpu.rob.rob_writes 1960359919 # The number of ROB writes -system.cpu.timesIdled 94610 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3754883 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 573340737 # Number of Instructions Simulated -system.cpu.committedInsts_total 573340737 # Number of Instructions Simulated -system.cpu.cpi 0.975996 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.975996 # CPI: Total CPI of All Threads -system.cpu.ipc 1.024595 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.024595 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3384956860 # number of integer regfile reads -system.cpu.int_regfile_writes 820192225 # number of integer regfile writes +system.cpu.rob.rob_reads 1426784011 # The number of ROB reads +system.cpu.rob.rob_writes 1949388350 # The number of ROB writes +system.cpu.timesIdled 93530 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3780041 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 573340817 # Number of Instructions Simulated +system.cpu.committedInsts_total 573340817 # Number of Instructions Simulated +system.cpu.cpi 0.969675 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.969675 # CPI: Total CPI of All Threads +system.cpu.ipc 1.031274 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.031274 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3375374322 # number of integer regfile reads +system.cpu.int_regfile_writes 818576050 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 1253867001 # number of misc regfile reads -system.cpu.misc_regfile_writes 4463662 # number of misc regfile writes -system.cpu.icache.replacements 12859 # number of replacements -system.cpu.icache.tagsinuse 1069.062929 # Cycle average of tags in use -system.cpu.icache.total_refs 146126711 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 14705 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 9937.212581 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 1246383424 # number of misc regfile reads +system.cpu.misc_regfile_writes 4463694 # number of misc regfile writes +system.cpu.icache.replacements 12953 # number of replacements +system.cpu.icache.tagsinuse 1066.011172 # Cycle average of tags in use +system.cpu.icache.total_refs 144842026 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 14796 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 9789.269127 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1069.062929 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.522003 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 146126714 # number of ReadReq hits -system.cpu.icache.demand_hits 146126714 # number of demand (read+write) hits -system.cpu.icache.overall_hits 146126714 # number of overall hits -system.cpu.icache.ReadReq_misses 16466 # number of ReadReq misses -system.cpu.icache.demand_misses 16466 # number of demand (read+write) misses -system.cpu.icache.overall_misses 16466 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 235996000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 235996000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 235996000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 146143180 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 146143180 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 146143180 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000113 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000113 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000113 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 14332.321147 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 14332.321147 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 14332.321147 # average overall miss latency +system.cpu.icache.occ_blocks::0 1066.011172 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.520513 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 144842026 # number of ReadReq hits +system.cpu.icache.demand_hits 144842026 # number of demand (read+write) hits +system.cpu.icache.overall_hits 144842026 # number of overall hits +system.cpu.icache.ReadReq_misses 16532 # number of ReadReq misses +system.cpu.icache.demand_misses 16532 # number of demand (read+write) misses +system.cpu.icache.overall_misses 16532 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 236127500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 236127500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 236127500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 144858558 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 144858558 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 144858558 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000114 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000114 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000114 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 14283.057101 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 14283.057101 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 14283.057101 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -352,146 +352,146 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1664 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1664 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1664 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 14802 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 14802 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 14802 # number of overall MSHR misses +system.cpu.icache.writebacks 3 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 1595 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1595 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1595 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 14937 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 14937 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 14937 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 154077500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 154077500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 154077500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 154963500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 154963500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 154963500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000101 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000101 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000101 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 10409.235238 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 10409.235238 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 10409.235238 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000103 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000103 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000103 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 10374.472786 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 10374.472786 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 10374.472786 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1212005 # number of replacements -system.cpu.dcache.tagsinuse 4056.899454 # Cycle average of tags in use -system.cpu.dcache.total_refs 205223733 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1216101 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 168.755501 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5990497000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4056.899454 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.990454 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 147671766 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 52787083 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 2532910 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 2231830 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 200458849 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 200458849 # number of overall hits -system.cpu.dcache.ReadReq_misses 1234695 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1452223 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 55 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 2686918 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2686918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 14259178500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 25049559493 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 501000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 39308737993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 39308737993 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 148906461 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1212304 # number of replacements +system.cpu.dcache.tagsinuse 4056.655033 # Cycle average of tags in use +system.cpu.dcache.total_refs 204333275 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1216400 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 167.981976 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5992651000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4056.655033 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.990394 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 146799577 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 52779397 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 2522240 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 2231846 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 199578974 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 199578974 # number of overall hits +system.cpu.dcache.ReadReq_misses 1241463 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1459909 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 57 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 2701372 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2701372 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 14210039000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 24949440994 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 510000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 39159479994 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 39159479994 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 148041040 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 2532965 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 2231830 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 203145767 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 203145767 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.008292 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.026774 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000022 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.013227 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.013227 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 11548.745642 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 17249.113596 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 9109.090909 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 14629.675335 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 14629.675335 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses 2522297 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 2231846 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 202280346 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 202280346 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.008386 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.026916 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.000023 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.013355 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.013355 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 11446.204196 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 17089.723396 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 8947.368421 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 14496.144920 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 14496.144920 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 493000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 416000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 60 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 55 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8216.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7563.636364 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1079434 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 358298 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1112430 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 55 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1470728 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1470728 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 876397 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 339793 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1216190 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1216190 # number of overall MSHR misses +system.cpu.dcache.writebacks 1079589 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 365099 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1119740 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 57 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1484839 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1484839 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 876364 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 340169 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1216533 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1216533 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 6322149500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 4329896000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 10652045500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 10652045500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 6322701500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4343796500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10666498000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10666498000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005886 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006265 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.005987 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.005987 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7213.796373 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12742.746319 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8758.537317 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8758.537317 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005920 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006272 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.006014 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.006014 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7214.697888 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12769.524854 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8767.947931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8767.947931 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 218713 # number of replacements -system.cpu.l2cache.tagsinuse 21078.689035 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1567898 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 239082 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.557993 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 207809197000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 7685.698304 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13392.990732 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.234549 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.408722 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 760512 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1079434 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 60 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 232403 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 992915 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 992915 # number of overall hits -system.cpu.l2cache.ReadReq_misses 130232 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 107668 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 237900 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 237900 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 4454609000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency 68500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3687681000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 8142290000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 8142290000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 890744 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 1079434 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 88 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 340071 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 1230815 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 1230815 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.146206 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.318182 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.316604 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.193287 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.193287 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34205.179986 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency 2446.428571 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34250.482966 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34225.683060 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34225.683060 # average overall miss latency +system.cpu.l2cache.replacements 218992 # number of replacements +system.cpu.l2cache.tagsinuse 21041.730576 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1568543 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 239349 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 6.553372 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 207293372000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 7594.160868 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13447.569709 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.231755 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.410387 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 760588 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 1079592 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 93 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 232455 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 993043 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 993043 # number of overall hits +system.cpu.l2cache.ReadReq_misses 130191 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 36 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 107958 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 238149 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 238149 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 4453286000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 204500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3697103500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 8150389500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 8150389500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 890779 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 1079592 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 129 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 340413 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 1231192 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 1231192 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.146154 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.279070 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.317138 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.193430 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.193430 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34205.789955 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 5680.555556 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34245.757609 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34223.908142 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34223.908142 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -500,32 +500,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 171082 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 22 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 130210 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 28 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 107668 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 237878 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 237878 # number of overall MSHR misses +system.cpu.l2cache.writebacks 171216 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 21 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 21 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 21 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 130170 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 36 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 107958 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 238128 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 238128 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4042910500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 868000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3338293500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 7381204000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 7381204000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4041635000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1116000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3347575000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 7389210000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 7389210000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146181 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.318182 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.316604 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.193269 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.193269 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31049.155211 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146131 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.279070 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317138 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.193413 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.193413 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31048.897595 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.438013 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31029.367995 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31029.367995 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31008.123530 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.412215 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.412215 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini index 6b22d733c..71df37b56 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini @@ -500,9 +500,9 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/x86/linux/parser +executable=/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/arm/scratch/sysexplr/dist/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/20.parser/ref/x86/linux/o3-timing/simout index 434d3b8ec..bc2d966a5 100755 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 18 2011 15:15:16 -gem5 started Aug 18 2011 16:17:29 -gem5 executing on nadc-0330 +gem5 compiled Aug 20 2011 13:24:14 +gem5 started Aug 20 2011 13:24:28 +gem5 executing on zizzer command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -42,14 +42,6 @@ info: Increasing stack size by one page. * we're thinking about going to a movie this theater * which dog you said you chased - also invited to the meeting were several prominent scientists -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. - he ran home so quickly that his mother could hardly believe he had called from school - so many people attended that they spilled over into several neighboring fields - voting in favor of the bill were 36 Republicans and 4 moderate Democrats @@ -76,9 +68,17 @@ info: Increasing stack size by one page. this is not the man we know and love info: Increasing stack size by one page. info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. we like to eat at restaurants , usually on weekends what did John say he thought you should do about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 510840039000 because target called exit() +Exiting @ tick 493847859500 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt index 4d5ea332a..d93a5470f 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,253 +1,253 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.510840 # Number of seconds simulated -sim_ticks 510840039000 # Number of ticks simulated +sim_seconds 0.493848 # Number of seconds simulated +sim_ticks 493847859500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116825 # Simulator instruction rate (inst/s) -host_tick_rate 39031538 # Simulator tick rate (ticks/s) -host_mem_usage 298988 # Number of bytes of host memory used -host_seconds 13087.88 # Real time elapsed on the host +host_inst_rate 141014 # Simulator instruction rate (inst/s) +host_tick_rate 45545926 # Simulator tick rate (ticks/s) +host_mem_usage 250808 # Number of bytes of host memory used +host_seconds 10842.85 # Real time elapsed on the host sim_insts 1528988756 # Number of instructions simulated system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 1021680079 # number of cpu cycles simulated +system.cpu.numCycles 987695720 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 254384753 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 254384753 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16610206 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 245027639 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 226325163 # Number of BTB hits +system.cpu.BPredUnit.lookups 245701836 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 245701836 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16595687 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 236380847 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 218346080 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 212335544 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1381273626 # Number of instructions fetch has processed -system.cpu.fetch.Branches 254384753 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 226325163 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 450902590 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 138126597 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 215756908 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33583 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 289533 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 200218324 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4741066 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 997472030 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.589458 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.314325 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 205619767 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1343825400 # Number of instructions fetch has processed +system.cpu.fetch.Branches 245701836 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 218346080 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 436746169 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 120030037 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 218211728 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32810 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 394519 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 194794908 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4074174 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 964173518 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.600326 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.317708 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 550645930 55.20% 55.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 34157576 3.42% 58.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 40518639 4.06% 62.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34398845 3.45% 66.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 21947419 2.20% 68.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 37358347 3.75% 72.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 49115154 4.92% 77.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 39392814 3.95% 80.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 189937306 19.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 531478687 55.12% 55.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 32400706 3.36% 58.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38829894 4.03% 62.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 32544605 3.38% 65.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21858974 2.27% 68.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 36433886 3.78% 71.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 49094534 5.09% 77.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 36959436 3.83% 80.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 184572796 19.14% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 997472030 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.248987 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.351963 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 271753192 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 172636288 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 387288931 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 47639747 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 118153872 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2516467041 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 4 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 118153872 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 307936660 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40922084 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10158 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 396952867 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 133496389 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2461579733 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3274 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26456916 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 89651322 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 11 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2291378441 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5783213965 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5782968371 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 245594 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 964173518 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.248763 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.360566 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 264598468 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 174292947 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 373121057 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 48992521 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 103168525 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2446276906 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 103168525 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 301836329 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39995204 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12425 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 383530410 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 135630625 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2393744264 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2638 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 25354791 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 92046607 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 28 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2227310497 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5630161832 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5629928430 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 233402 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 864079414 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1434 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1388 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 310156167 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 591477986 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 228734468 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 236858488 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 68220241 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2345816058 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 6894 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1946813655 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1738463 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 808263725 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1297300959 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 6341 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 997472030 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.951748 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.794233 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 800011470 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1318 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1303 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 319166295 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 577919050 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 226606684 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 227271329 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 66051723 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2286915029 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 6159 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1922683409 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1316831 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 755416366 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1189575311 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 5606 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 964173518 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.994126 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.811461 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 296825004 29.76% 29.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 173205263 17.36% 47.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 166698765 16.71% 63.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 150564381 15.09% 78.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 111664021 11.19% 90.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60204229 6.04% 96.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 28392427 2.85% 99.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 8857592 0.89% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1060348 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 282941420 29.35% 29.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 159777972 16.57% 45.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 162985907 16.90% 62.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 148632114 15.42% 78.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 109327758 11.34% 89.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 60035944 6.23% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 30803018 3.19% 99.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8626659 0.89% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1042726 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 997472030 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 964173518 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2217543 14.62% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 10152332 66.93% 81.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2799030 18.45% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2258663 14.74% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9960479 65.00% 79.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3103804 20.26% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2499313 0.13% 0.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1291834730 66.36% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 7 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 471566042 24.22% 90.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 180913563 9.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2419995 0.13% 0.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1274972987 66.31% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 9 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 463702844 24.12% 90.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 181587574 9.44% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1946813655 # Type of FU issued -system.cpu.iq.rate 1.905502 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15168905 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007792 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4908001946 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3157548057 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1893221239 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4762 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 79762 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 141 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1959481671 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1576 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 155754534 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1922683409 # Type of FU issued +system.cpu.iq.rate 1.946635 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15322946 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007970 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4826174769 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3042532180 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1874952899 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5344 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 78632 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 143 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1935584605 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1755 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 158265730 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 207375826 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 336925 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 3565166 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 79574659 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 193816890 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 368616 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 283851 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 77446847 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2286 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2334 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 118153872 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9207603 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1436064 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2345822952 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1077995 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 591477986 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 228734844 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6894 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1048509 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 24437 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 3565166 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15650863 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2406220 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18057083 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1908274747 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 461721448 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 38538908 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 103168525 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9000117 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1434115 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2286921188 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1114031 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 577919050 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 226607032 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6159 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1032728 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29962 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 283851 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15679501 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2385329 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18064830 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1889474492 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 454765570 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 33208917 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 635666266 # number of memory reference insts executed -system.cpu.iew.exec_branches 176848258 # Number of branches executed -system.cpu.iew.exec_stores 173944818 # Number of stores executed -system.cpu.iew.exec_rate 1.867781 # Inst execution rate -system.cpu.iew.wb_sent 1900894756 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1893221380 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1455907032 # num instructions producing a value -system.cpu.iew.wb_consumers 2156045862 # num instructions consuming a value +system.cpu.iew.exec_refs 629342688 # number of memory reference insts executed +system.cpu.iew.exec_branches 176743901 # Number of branches executed +system.cpu.iew.exec_stores 174577118 # Number of stores executed +system.cpu.iew.exec_rate 1.913013 # Inst execution rate +system.cpu.iew.wb_sent 1882825411 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1874953042 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1440779649 # num instructions producing a value +system.cpu.iew.wb_consumers 2134933130 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.853047 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.675267 # average fanout of values written-back +system.cpu.iew.wb_rate 1.898310 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.674859 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 816844403 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 757942908 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16638462 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 879318158 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.738835 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.275232 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16623561 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 861004993 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.775819 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.288206 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 352136515 40.05% 40.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 212867347 24.21% 64.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 82048632 9.33% 73.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 90555710 10.30% 83.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 33314803 3.79% 87.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25793757 2.93% 90.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15202497 1.73% 92.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12277140 1.40% 93.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 55121757 6.27% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 338275347 39.29% 39.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 210593488 24.46% 63.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 75171542 8.73% 72.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92637359 10.76% 83.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34049472 3.95% 87.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27973994 3.25% 90.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16051033 1.86% 92.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12256013 1.42% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 53996745 6.27% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 879318158 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 861004993 # Number of insts commited each cycle system.cpu.commit.count 1528988756 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 533262345 # Number of memory references committed @@ -257,49 +257,49 @@ system.cpu.commit.branches 149758588 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 55121757 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 53996745 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3170029560 # The number of ROB reads -system.cpu.rob.rob_writes 4810732530 # The number of ROB writes -system.cpu.timesIdled 614029 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24208049 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3093939912 # The number of ROB reads +system.cpu.rob.rob_writes 4677211584 # The number of ROB writes +system.cpu.timesIdled 604649 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 23522202 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1528988756 # Number of Instructions Simulated system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated -system.cpu.cpi 0.668206 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.668206 # CPI: Total CPI of All Threads -system.cpu.ipc 1.496544 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.496544 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3193160283 # number of integer regfile reads -system.cpu.int_regfile_writes 1761637277 # number of integer regfile writes -system.cpu.fp_regfile_reads 154 # number of floating regfile reads -system.cpu.fp_regfile_writes 7 # number of floating regfile writes -system.cpu.misc_regfile_reads 1050196665 # number of misc regfile reads -system.cpu.icache.replacements 10211 # number of replacements -system.cpu.icache.tagsinuse 970.164405 # Cycle average of tags in use -system.cpu.icache.total_refs 199977093 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 11716 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 17068.717395 # Average number of references to valid blocks. +system.cpu.cpi 0.645980 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.645980 # CPI: Total CPI of All Threads +system.cpu.ipc 1.548036 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.548036 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3179615221 # number of integer regfile reads +system.cpu.int_regfile_writes 1745014633 # number of integer regfile writes +system.cpu.fp_regfile_reads 160 # number of floating regfile reads +system.cpu.fp_regfile_writes 9 # number of floating regfile writes +system.cpu.misc_regfile_reads 1039384818 # number of misc regfile reads +system.cpu.icache.replacements 9994 # number of replacements +system.cpu.icache.tagsinuse 979.138170 # Cycle average of tags in use +system.cpu.icache.total_refs 194574782 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 11491 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 16932.798016 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 970.164405 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.473713 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 199983553 # number of ReadReq hits -system.cpu.icache.demand_hits 199983553 # number of demand (read+write) hits -system.cpu.icache.overall_hits 199983553 # number of overall hits -system.cpu.icache.ReadReq_misses 234771 # number of ReadReq misses -system.cpu.icache.demand_misses 234771 # number of demand (read+write) misses -system.cpu.icache.overall_misses 234771 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 1605945000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 1605945000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 1605945000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 200218324 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 200218324 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 200218324 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.001173 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.001173 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.001173 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 6840.474335 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 6840.474335 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 6840.474335 # average overall miss latency +system.cpu.icache.occ_blocks::0 979.138170 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.478095 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 194581368 # number of ReadReq hits +system.cpu.icache.demand_hits 194581368 # number of demand (read+write) hits +system.cpu.icache.overall_hits 194581368 # number of overall hits +system.cpu.icache.ReadReq_misses 213540 # number of ReadReq misses +system.cpu.icache.demand_misses 213540 # number of demand (read+write) misses +system.cpu.icache.overall_misses 213540 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 1483328000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 1483328000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 1483328000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 194794908 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 194794908 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 194794908 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.001096 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.001096 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.001096 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 6946.370703 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 6946.370703 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 6946.370703 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -309,136 +309,136 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 7 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 2045 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 2045 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 2045 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 232726 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 232726 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 232726 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 2095 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 2095 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 2095 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 211445 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 211445 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 211445 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 856837000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 856837000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 856837000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 798407000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 798407000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 798407000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.001162 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.001162 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.001162 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3681.741619 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3681.741619 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3681.741619 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.001085 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.001085 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.001085 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3775.955922 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3775.955922 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3775.955922 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2528466 # number of replacements -system.cpu.dcache.tagsinuse 4087.809380 # Cycle average of tags in use -system.cpu.dcache.total_refs 450171258 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2532562 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 177.753302 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 2146317000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4087.809380 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.998000 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 301389470 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 147508711 # number of WriteReq hits -system.cpu.dcache.demand_hits 448898181 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 448898181 # number of overall hits -system.cpu.dcache.ReadReq_misses 3181552 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1651490 # number of WriteReq misses -system.cpu.dcache.demand_misses 4833042 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 4833042 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 53701118000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 39968131000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 93669249000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 93669249000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 304571022 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2527816 # number of replacements +system.cpu.dcache.tagsinuse 4087.589623 # Cycle average of tags in use +system.cpu.dcache.total_refs 440722661 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2531912 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 174.067132 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 2123837000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4087.589623 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997947 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 291994352 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 147612028 # number of WriteReq hits +system.cpu.dcache.demand_hits 439606380 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 439606380 # number of overall hits +system.cpu.dcache.ReadReq_misses 3097887 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1548173 # number of WriteReq misses +system.cpu.dcache.demand_misses 4646060 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 4646060 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 51505231500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 36276487000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 87781718500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 87781718500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 295092239 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 453731223 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 453731223 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.010446 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.011072 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.010652 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.010652 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 16878.906270 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 24201.255230 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 19381.012828 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 19381.012828 # average overall miss latency +system.cpu.dcache.demand_accesses 444252440 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 444252440 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.010498 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.010379 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.010458 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.010458 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 16625.923250 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 23431.804456 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 18893.797863 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 18893.797863 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 23000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 11500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 2229597 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1420514 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 666840 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2087354 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2087354 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1761038 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 984650 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2745688 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2745688 # number of overall MSHR misses +system.cpu.dcache.writebacks 2229445 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1337511 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 584931 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1922442 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1922442 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1760376 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 963242 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2723618 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2723618 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14931886500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 17549642500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 32481529000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 32481529000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 14910828500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 16810626500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 31721455000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 31721455000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005782 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006601 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.006051 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.006051 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8479.025722 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17823.229066 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 11830.014554 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 11830.014554 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005966 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006458 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.006131 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.006131 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8470.252094 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17452.131967 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11646.807665 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11646.807665 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 575462 # number of replacements -system.cpu.l2cache.tagsinuse 21596.870084 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3194136 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 594624 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.371690 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 286599678000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 7777.126789 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13819.743295 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.237339 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.421745 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1433421 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 2229604 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 1236 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 524443 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1957864 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1957864 # number of overall hits -system.cpu.l2cache.ReadReq_misses 339163 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 219734 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 247117 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 586280 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 586280 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 11583073000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency 9821500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 8475872500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 20058945500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 20058945500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1772584 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 2229604 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 220970 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 771560 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 2544144 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 2544144 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.191338 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.994406 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.320282 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.230443 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.230443 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34151.935795 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency 44.697225 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34299.026372 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34213.934468 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34213.934468 # average overall miss latency +system.cpu.l2cache.replacements 574929 # number of replacements +system.cpu.l2cache.tagsinuse 21600.538558 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3193840 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 594089 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.376030 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 271573746000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 7800.784816 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13799.753742 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.238061 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.421135 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1433037 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 2229452 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 1223 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 524485 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 1957522 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1957522 # number of overall hits +system.cpu.l2cache.ReadReq_misses 338639 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 198705 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 247104 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 585743 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 585743 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 11565729500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 9755500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 8475498500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 20041228000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 20041228000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1771676 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 2229452 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 199928 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 771589 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2543265 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2543265 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.191140 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.993883 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.320253 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.230311 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.230311 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34153.566187 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 49.095393 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34299.317292 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34215.053360 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34215.053360 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,31 +447,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 411447 # number of writebacks +system.cpu.l2cache.writebacks 411255 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 339163 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 219734 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 247117 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 586280 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 586280 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 338639 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 198705 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 247104 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 585743 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 585743 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10521035500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6812324500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 7664755500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 18185791000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 18185791000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 10504876500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6160011500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 7664207000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 18169083500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 18169083500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191338 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994406 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320282 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.230443 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.230443 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31020.587446 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31002.596321 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31016.706661 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31018.951695 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31018.951695 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191140 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.993883 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320253 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.230311 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.230311 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31020.870307 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.787600 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31016.118719 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31018.865782 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31018.865782 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index 9f597bc96..01d03e5c5 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/alpha/tru64/eon +executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout index cbdf9cdc6..46133d214 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 14:47:20 -gem5 started Aug 17 2011 15:37:38 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 16:10:02 +gem5 started Aug 20 2011 16:10:09 +gem5 executing on zizzer command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -13,4 +13,4 @@ info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.083333 -Exiting @ tick 90005685500 because target called exit() +Exiting @ tick 89480174500 because target called exit() diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 17e0eeb5a..f27e3deec 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.090006 # Number of seconds simulated -sim_ticks 90005685500 # Number of ticks simulated +sim_seconds 0.089480 # Number of seconds simulated +sim_ticks 89480174500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147306 # Simulator instruction rate (inst/s) -host_tick_rate 35301564 # Simulator tick rate (ticks/s) -host_mem_usage 258568 # Number of bytes of host memory used -host_seconds 2549.62 # Real time elapsed on the host +host_inst_rate 168732 # Simulator instruction rate (inst/s) +host_tick_rate 40200085 # Simulator tick rate (ticks/s) +host_mem_usage 211620 # Number of bytes of host memory used +host_seconds 2225.87 # Real time elapsed on the host sim_insts 375574794 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 105557144 # DTB read hits -system.cpu.dtb.read_misses 98530 # DTB read misses +system.cpu.dtb.read_hits 105444914 # DTB read hits +system.cpu.dtb.read_misses 94699 # DTB read misses system.cpu.dtb.read_acv 48617 # DTB read access violations -system.cpu.dtb.read_accesses 105655674 # DTB read accesses -system.cpu.dtb.write_hits 79803143 # DTB write hits -system.cpu.dtb.write_misses 1575 # DTB write misses +system.cpu.dtb.read_accesses 105539613 # DTB read accesses +system.cpu.dtb.write_hits 79763652 # DTB write hits +system.cpu.dtb.write_misses 1536 # DTB write misses system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 79804718 # DTB write accesses -system.cpu.dtb.data_hits 185360287 # DTB hits -system.cpu.dtb.data_misses 100105 # DTB misses +system.cpu.dtb.write_accesses 79765188 # DTB write accesses +system.cpu.dtb.data_hits 185208566 # DTB hits +system.cpu.dtb.data_misses 96235 # DTB misses system.cpu.dtb.data_acv 48618 # DTB access violations -system.cpu.dtb.data_accesses 185460392 # DTB accesses -system.cpu.itb.fetch_hits 58034543 # ITB hits -system.cpu.itb.fetch_misses 355 # ITB misses +system.cpu.dtb.data_accesses 185304801 # DTB accesses +system.cpu.itb.fetch_hits 57904086 # ITB hits +system.cpu.itb.fetch_misses 346 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 58034898 # ITB accesses +system.cpu.itb.fetch_accesses 57904432 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,246 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 180011373 # number of cpu cycles simulated +system.cpu.numCycles 178960351 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 56898591 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 33211966 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3574908 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 40524300 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 31971911 # Number of BTB hits +system.cpu.BPredUnit.lookups 56765606 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 33143039 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3552012 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 40427205 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 32022628 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 10712923 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1454 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 60019462 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 503879026 # Number of instructions fetch has processed -system.cpu.fetch.Branches 56898591 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42684834 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 93650208 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12840667 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 16998273 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7695 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 58034543 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1110351 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 179889864 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.801042 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.244247 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 10686505 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1330 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 59866357 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 502938652 # Number of instructions fetch has processed +system.cpu.fetch.Branches 56765606 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42709133 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 93526616 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12701088 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 16326839 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 180 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7643 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 57904086 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1110763 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 178838548 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.812250 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.245901 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 86239656 47.94% 47.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 7968101 4.43% 52.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9837104 5.47% 57.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6455150 3.59% 61.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 13616411 7.57% 69.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9477434 5.27% 74.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5920004 3.29% 77.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3509603 1.95% 79.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36866401 20.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 85311932 47.70% 47.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8035871 4.49% 52.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9868460 5.52% 57.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6372149 3.56% 61.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 13508487 7.55% 68.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9517347 5.32% 74.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5905302 3.30% 77.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3555081 1.99% 79.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36763919 20.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 179889864 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316083 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.799151 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 66046381 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 13163939 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 87675814 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3794037 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9209693 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 10269415 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4478 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 492179347 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12338 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9209693 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 70508732 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4469526 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 393246 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 86965796 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8342871 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 478964918 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 37494 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 6850524 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 311020883 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 627865578 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 331628214 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 296237364 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 178838548 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.317197 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.810336 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 65738845 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 12641259 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 87702735 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3649079 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9106630 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 10252982 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4580 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 491283130 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12139 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9106630 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 70077435 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4396073 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 392991 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 87026850 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 7838569 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 478183111 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 34338 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 6474620 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 310467420 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 626927534 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 331115388 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 295812146 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 51488564 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 38437 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 301 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 23116949 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 110811715 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 85594435 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 10526782 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6196399 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 433477285 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 262 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 418941176 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1867414 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 56505676 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 32298658 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 179889864 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.328876 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.003011 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 50935101 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 38371 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 296 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 21811876 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 110641644 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 85552281 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8662202 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5906832 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 433013718 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 258 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 418626838 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2003473 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 56038444 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 32198216 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 43 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 178838548 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.340809 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.008173 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 44759242 24.88% 24.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 29396949 16.34% 41.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 28140071 15.64% 56.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 26088939 14.50% 71.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 22436504 12.47% 83.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15753855 8.76% 92.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8086358 4.50% 97.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3859739 2.15% 99.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1368207 0.76% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 44336411 24.79% 24.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 29007268 16.22% 41.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 27775406 15.53% 56.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 26238037 14.67% 71.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 22251353 12.44% 83.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15664112 8.76% 92.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8263195 4.62% 97.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3972623 2.22% 99.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1330143 0.74% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 179889864 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 178838548 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 136828 1.12% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 42966 0.35% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 1217 0.01% 1.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 10365 0.09% 1.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1870140 15.36% 16.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1752756 14.40% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5345662 43.91% 75.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3013374 24.75% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 135690 1.14% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 41926 0.35% 1.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 2442 0.02% 1.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 8992 0.08% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1877041 15.76% 17.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1762283 14.79% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5120089 42.98% 75.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2964035 24.88% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 164274346 39.21% 39.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126487 0.51% 39.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33733978 8.05% 47.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7896269 1.88% 49.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2902886 0.69% 50.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16725004 3.99% 54.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1576072 0.38% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 108193841 25.83% 80.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 81478712 19.45% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 164031789 39.18% 39.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126165 0.51% 39.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33716465 8.05% 47.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7893369 1.89% 49.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2899949 0.69% 50.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16711518 3.99% 54.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1573138 0.38% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 108174365 25.84% 80.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 81466499 19.46% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 418941176 # Type of FU issued -system.cpu.iq.rate 2.327304 # Inst issue rate -system.cpu.iq.fu_busy_cnt 12173308 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029057 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 682905692 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 289620140 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 241865929 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 348907246 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 200439541 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 164655906 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 252869699 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 178211204 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 14135279 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 418626838 # Type of FU issued +system.cpu.iq.rate 2.339216 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11912498 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028456 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 681277012 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 289109429 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 241633599 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 348731183 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 199993522 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 164553982 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 252486483 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 178019272 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 13980098 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 16057229 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 148927 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 77022 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12073707 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 15887158 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 143607 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 50570 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12031553 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 215342 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 233419 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9209693 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2342336 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 345962 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 459173536 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2310367 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 110811715 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 85594435 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 262 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 272 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 9106630 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2382208 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 372749 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 458676643 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2278358 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 110641644 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 85552281 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 258 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 129 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 14 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 77022 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3457252 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 554336 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4011588 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 410317513 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 105704327 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 8623663 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 50570 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3441219 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 544657 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3985876 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 409944817 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 105588265 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 8682021 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 25695989 # number of nop insts executed -system.cpu.iew.exec_refs 185509104 # number of memory reference insts executed -system.cpu.iew.exec_branches 48173918 # Number of branches executed -system.cpu.iew.exec_stores 79804777 # Number of stores executed -system.cpu.iew.exec_rate 2.279398 # Inst execution rate -system.cpu.iew.wb_sent 407775826 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 406521835 # cumulative count of insts written-back -system.cpu.iew.wb_producers 197958297 # num instructions producing a value -system.cpu.iew.wb_consumers 277706216 # num instructions consuming a value +system.cpu.iew.exec_nop 25662667 # number of nop insts executed +system.cpu.iew.exec_refs 185353481 # number of memory reference insts executed +system.cpu.iew.exec_branches 48120403 # Number of branches executed +system.cpu.iew.exec_stores 79765216 # Number of stores executed +system.cpu.iew.exec_rate 2.290702 # Inst execution rate +system.cpu.iew.wb_sent 407421919 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 406187581 # cumulative count of insts written-back +system.cpu.iew.wb_producers 197894075 # num instructions producing a value +system.cpu.iew.wb_consumers 277422150 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.258312 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.712834 # average fanout of values written-back +system.cpu.iew.wb_rate 2.269707 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.713332 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 398664569 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 60526277 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 60016815 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3570557 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 170680171 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.335740 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.860101 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3547729 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 169731918 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.348790 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.858024 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 71080695 41.65% 41.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 25597473 15.00% 56.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15025586 8.80% 65.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12350485 7.24% 72.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8728325 5.11% 77.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 6123095 3.59% 81.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5311766 3.11% 84.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3136870 1.84% 86.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23325876 13.67% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 70140218 41.32% 41.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 25651558 15.11% 56.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14667534 8.64% 65.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12267165 7.23% 72.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 9098146 5.36% 77.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 6161287 3.63% 81.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5543706 3.27% 84.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3203239 1.89% 86.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22999065 13.55% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 170680171 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 169731918 # Number of insts commited each cycle system.cpu.commit.count 398664569 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 168275214 # Number of memory references committed @@ -290,50 +290,50 @@ system.cpu.commit.branches 44587530 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365825 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 23325876 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22999065 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 606542164 # The number of ROB reads -system.cpu.rob.rob_writes 927610224 # The number of ROB writes -system.cpu.timesIdled 2703 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 121509 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 605411260 # The number of ROB reads +system.cpu.rob.rob_writes 926487800 # The number of ROB writes +system.cpu.timesIdled 2712 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 121803 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574794 # Number of Instructions Simulated system.cpu.committedInsts_total 375574794 # Number of Instructions Simulated -system.cpu.cpi 0.479296 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.479296 # CPI: Total CPI of All Threads -system.cpu.ipc 2.086395 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.086395 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 410036032 # number of integer regfile reads -system.cpu.int_regfile_writes 175891320 # number of integer regfile writes -system.cpu.fp_regfile_reads 159397664 # number of floating regfile reads -system.cpu.fp_regfile_writes 105955330 # number of floating regfile writes +system.cpu.cpi 0.476497 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.476497 # CPI: Total CPI of All Threads +system.cpu.ipc 2.098648 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.098648 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 409675274 # number of integer regfile reads +system.cpu.int_regfile_writes 175727060 # number of integer regfile writes +system.cpu.fp_regfile_reads 159328411 # number of floating regfile reads +system.cpu.fp_regfile_writes 105866122 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 2104 # number of replacements -system.cpu.icache.tagsinuse 1835.532395 # Cycle average of tags in use -system.cpu.icache.total_refs 58029268 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4030 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14399.322084 # Average number of references to valid blocks. +system.cpu.icache.replacements 2110 # number of replacements +system.cpu.icache.tagsinuse 1834.326922 # Cycle average of tags in use +system.cpu.icache.total_refs 57898804 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4037 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 14342.037156 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1835.532395 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.896256 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 58029268 # number of ReadReq hits -system.cpu.icache.demand_hits 58029268 # number of demand (read+write) hits -system.cpu.icache.overall_hits 58029268 # number of overall hits -system.cpu.icache.ReadReq_misses 5275 # number of ReadReq misses -system.cpu.icache.demand_misses 5275 # number of demand (read+write) misses -system.cpu.icache.overall_misses 5275 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 167800500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 167800500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 167800500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 58034543 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 58034543 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 58034543 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 1834.326922 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.895667 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 57898804 # number of ReadReq hits +system.cpu.icache.demand_hits 57898804 # number of demand (read+write) hits +system.cpu.icache.overall_hits 57898804 # number of overall hits +system.cpu.icache.ReadReq_misses 5282 # number of ReadReq misses +system.cpu.icache.demand_misses 5282 # number of demand (read+write) misses +system.cpu.icache.overall_misses 5282 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 167914000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 167914000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 167914000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 57904086 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 57904086 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 57904086 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000091 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000091 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000091 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 31810.521327 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 31810.521327 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 31810.521327 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 31789.852329 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 31789.852329 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 31789.852329 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -346,158 +346,158 @@ system.cpu.icache.writebacks 0 # nu system.cpu.icache.ReadReq_mshr_hits 1245 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits 1245 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits 1245 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 4030 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 4030 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 4030 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_misses 4037 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 4037 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 4037 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 123364000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 123364000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 123364000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 123459000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 123459000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 123459000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000069 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000069 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000069 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 30611.414392 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 30611.414392 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 30611.414392 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000070 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000070 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000070 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 30581.867724 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 30581.867724 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 30581.867724 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 783 # number of replacements -system.cpu.dcache.tagsinuse 3295.270928 # Cycle average of tags in use -system.cpu.dcache.total_refs 164706127 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 39384.535390 # Average number of references to valid blocks. +system.cpu.dcache.replacements 793 # number of replacements +system.cpu.dcache.tagsinuse 3296.196945 # Cycle average of tags in use +system.cpu.dcache.total_refs 164730953 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4193 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 39287.134033 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3295.270928 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.804510 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 91204849 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 73501271 # number of WriteReq hits +system.cpu.dcache.occ_blocks::0 3296.196945 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.804736 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 91229707 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 73501239 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 164706120 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 164706120 # number of overall hits -system.cpu.dcache.ReadReq_misses 1662 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 19457 # number of WriteReq misses -system.cpu.dcache.demand_misses 21119 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 21119 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 55598500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 568882000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 624480500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 624480500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 91206511 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits 164730946 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 164730946 # number of overall hits +system.cpu.dcache.ReadReq_misses 1678 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 19489 # number of WriteReq misses +system.cpu.dcache.demand_misses 21167 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 21167 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 55919500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 568883000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 624802500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 624802500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 91231385 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 73520728 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 164727239 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 164727239 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses 164752113 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 164752113 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.000265 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate 0.000128 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.000128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33452.767750 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 29237.909236 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 29569.605568 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 29569.605568 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency 33325.089392 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 29189.953307 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 29517.763500 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 29517.763500 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3875 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2600 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 661 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 671 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 16266 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 16937 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 16937 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 991 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 3191 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 4182 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 4182 # number of overall MSHR misses +system.cpu.dcache.writebacks 671 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 680 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 16294 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 16974 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 16974 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 998 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 3195 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 4193 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 4193 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 31558000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 113135500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 144693500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 144693500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 31703500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 113133500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 144837000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 144837000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31844.601413 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35454.559699 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34599.115256 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34599.115256 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31767.034068 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35409.546166 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34542.570952 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34542.570952 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 9 # number of replacements -system.cpu.l2cache.tagsinuse 4001.784111 # Cycle average of tags in use -system.cpu.l2cache.total_refs 795 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4839 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.164290 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 10 # number of replacements +system.cpu.l2cache.tagsinuse 4007.455925 # Cycle average of tags in use +system.cpu.l2cache.total_refs 810 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4847 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.167114 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3624.039188 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 377.744922 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.110597 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.011528 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 722 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 661 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 60 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 782 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 782 # number of overall hits -system.cpu.l2cache.ReadReq_misses 4299 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 3131 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 7430 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 7430 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 147966000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 108412500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 256378500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 256378500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 5021 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 661 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 3191 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 8212 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 8212 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.856204 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.981197 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.904774 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.904774 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34418.702024 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34625.519004 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34505.854643 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34505.854643 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 3000 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::0 3629.785283 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 377.670641 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.110772 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.011526 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 730 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 671 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 65 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 795 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 795 # number of overall hits +system.cpu.l2cache.ReadReq_misses 4305 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 3130 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 7435 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 7435 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 148163500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 108392000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 256555500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 256555500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 5035 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 671 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 3195 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 8230 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 8230 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.855015 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.979656 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.903402 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.903402 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34416.608595 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34630.031949 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34506.455952 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34506.455952 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 4299 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 3131 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 7430 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 7430 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 4305 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 3130 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 7435 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 7435 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 134126000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 98548000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 232674000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 232674000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 134314000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 98534000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 232848000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 232848000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.856204 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.981197 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.904774 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.904774 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31199.348686 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31474.928138 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31315.477793 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31315.477793 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.855015 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.979656 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.903402 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.903402 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31199.535424 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31480.511182 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31317.821116 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31317.821116 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini index 9a16b9fb5..538eb23e4 100644 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/arm/linux/eon +executable=/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/30.eon/ref/arm/linux/o3-timing/simout index 9b6003954..afdbb2fca 100755 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 19:27:45 -gem5 started Aug 17 2011 20:29:21 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 12:27:58 +gem5 started Aug 20 2011 12:28:18 +gem5 executing on zizzer command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -15,4 +15,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.100000 -Exiting @ tick 105165052500 because target called exit() +Exiting @ tick 104473822000 because target called exit() diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt index e1fef621a..f346fce3e 100644 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.105165 # Number of seconds simulated -sim_ticks 105165052500 # Number of ticks simulated +sim_seconds 0.104474 # Number of seconds simulated +sim_ticks 104473822000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98655 # Simulator instruction rate (inst/s) -host_tick_rate 29722313 # Simulator tick rate (ticks/s) -host_mem_usage 272452 # Number of bytes of host memory used -host_seconds 3538.25 # Real time elapsed on the host +host_inst_rate 153431 # Simulator instruction rate (inst/s) +host_tick_rate 45921219 # Simulator tick rate (ticks/s) +host_mem_usage 225932 # Number of bytes of host memory used +host_seconds 2275.07 # Real time elapsed on the host sim_insts 349066014 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses @@ -51,105 +51,105 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 210330106 # number of cpu cycles simulated +system.cpu.numCycles 208947645 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 38627930 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 21275864 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3257223 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 27645633 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 21400607 # Number of BTB hits +system.cpu.BPredUnit.lookups 38329680 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 21105904 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3259287 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 27325340 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 21186794 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 7694267 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 65033 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 44094135 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 341080803 # Number of instructions fetch has processed -system.cpu.fetch.Branches 38627930 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 29094874 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 79585948 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11338001 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 78589152 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 192 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 41622030 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 918575 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 210218055 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.123854 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.194738 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 7687582 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 64950 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 43658765 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 338491573 # Number of instructions fetch has processed +system.cpu.fetch.Branches 38329680 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 28874376 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 79000452 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11006616 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 78476147 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 177 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 41256182 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 909033 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 208834894 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.121215 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.193825 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131312097 62.46% 62.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 9414467 4.48% 66.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6051481 2.88% 69.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6791526 3.23% 73.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 5430399 2.58% 75.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4963864 2.36% 78.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3858971 1.84% 79.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4276288 2.03% 81.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 38118962 18.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130486470 62.48% 62.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 9432998 4.52% 67.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6020581 2.88% 69.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6715952 3.22% 73.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5392715 2.58% 75.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4860169 2.33% 78.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3823300 1.83% 79.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4271417 2.05% 81.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 37831292 18.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 210218055 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.183654 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.621645 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 51714033 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 73744287 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 72994348 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3887626 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 7877761 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7589058 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 71126 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 434888611 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 197240 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 7877761 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 59389931 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1170243 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 57751426 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 69399524 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14629170 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 419355645 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 21743 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8031956 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 92 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 459021692 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2465031741 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1360499222 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1104532519 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 208834894 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.183442 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.619983 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 51226737 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 73595547 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 72551850 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3832247 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7628513 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7466092 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 71093 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 431841645 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 197934 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 7628513 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 58855206 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1197679 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 57579508 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 68948533 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14625455 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 416807689 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 21628 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8007310 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 88 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 455449785 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2447349864 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1352895692 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1094454172 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384568567 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 74453120 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3990661 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4048076 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 47737584 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 109099510 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 93607240 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 6092384 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2874940 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 396088689 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3868258 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 378790544 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2203147 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 48219539 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 157035108 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 312812 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 210218055 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.801893 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.982792 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 70881213 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3981353 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4038094 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 48179191 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 108793088 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 93182345 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3369455 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2301817 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 394396503 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3860146 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 379227630 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1821640 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 46525332 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 143742588 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 304700 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 208834894 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.815921 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.996738 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 82551519 39.27% 39.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 35288638 16.79% 56.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24974853 11.88% 67.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18906763 8.99% 76.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21633905 10.29% 87.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15100886 7.18% 94.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8378665 3.99% 98.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2542737 1.21% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 840089 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 82039971 39.28% 39.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 34743122 16.64% 55.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24446026 11.71% 67.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18532815 8.87% 76.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21777610 10.43% 86.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15334879 7.34% 94.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8388297 4.02% 98.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2697998 1.29% 99.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 874176 0.42% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 210218055 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 208834894 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2335 0.01% 0.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2499 0.01% 0.01% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 5043 0.03% 0.04% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.04% # attempts to use FU when none available @@ -169,128 +169,128 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.04% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 47491 0.28% 0.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 2600 0.02% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 370 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 62973 0.37% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 771 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 174751 1.02% 1.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9256583 54.09% 55.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7559769 44.18% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 10462 0.06% 0.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 2799 0.02% 0.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 391 0.00% 0.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 64669 0.37% 0.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 798 0.00% 0.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 177194 1.02% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9656371 55.60% 57.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7448588 42.88% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 129785467 34.26% 34.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2147242 0.57% 34.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 19 0.00% 34.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6801299 1.80% 36.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8678326 2.29% 38.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3497449 0.92% 39.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1584673 0.42% 40.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21181771 5.59% 45.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7250646 1.91% 47.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7280640 1.92% 49.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175288 0.05% 49.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103263582 27.26% 76.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 87144142 23.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 129667439 34.19% 34.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2147217 0.57% 34.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 12 0.00% 34.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6745597 1.78% 36.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8690395 2.29% 38.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3497824 0.92% 39.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1584668 0.42% 40.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21149446 5.58% 45.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7187375 1.90% 47.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7146329 1.88% 49.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175288 0.05% 49.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103745248 27.36% 76.93% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 87490792 23.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 378790544 # Type of FU issued -system.cpu.iq.rate 1.800934 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17112689 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.045177 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 735684674 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 312839753 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 251076312 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 251430305 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 135519502 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118553768 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266787824 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 129115409 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5590978 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 379227630 # Type of FU issued +system.cpu.iq.rate 1.814941 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17368817 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.045801 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 735557028 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 310975021 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 251585005 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 250923583 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 133814979 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118291748 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 267725333 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128871114 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 7296411 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14450513 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33283 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 183129 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11231413 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14144091 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 112652 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 8375 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10806518 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 279 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 269 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 7877761 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 19485 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 447 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 400004247 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2635197 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 109099510 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 93607240 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3857036 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 57 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 197 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 183129 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3190070 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 310107 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3500177 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 372762431 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101699346 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6028113 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 7628513 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 19213 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 427 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 398303949 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2640938 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 108793088 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 93182345 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3848920 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 48 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 191 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 8375 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3190408 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 311351 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3501759 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 373094213 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 102121029 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6133417 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 47300 # number of nop insts executed -system.cpu.iew.exec_refs 187402554 # number of memory reference insts executed -system.cpu.iew.exec_branches 32194166 # Number of branches executed -system.cpu.iew.exec_stores 85703208 # Number of stores executed -system.cpu.iew.exec_rate 1.772273 # Inst execution rate -system.cpu.iew.wb_sent 370566710 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 369630080 # cumulative count of insts written-back -system.cpu.iew.wb_producers 175670846 # num instructions producing a value -system.cpu.iew.wb_consumers 345667025 # num instructions consuming a value +system.cpu.iew.exec_refs 188086624 # number of memory reference insts executed +system.cpu.iew.exec_branches 32219112 # Number of branches executed +system.cpu.iew.exec_stores 85965595 # Number of stores executed +system.cpu.iew.exec_rate 1.785587 # Inst execution rate +system.cpu.iew.wb_sent 370884944 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 369876753 # cumulative count of insts written-back +system.cpu.iew.wb_producers 175641589 # num instructions producing a value +system.cpu.iew.wb_consumers 345778200 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.757381 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.508208 # average fanout of values written-back +system.cpu.iew.wb_rate 1.770189 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.507960 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 349066626 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 50932905 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 49232556 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 3555446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3228207 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 202340295 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.725146 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.308674 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3230297 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 201206382 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.734869 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.321510 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 90698081 44.82% 44.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 39477240 19.51% 64.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 17960460 8.88% 73.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13374711 6.61% 79.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 15019988 7.42% 87.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7480519 3.70% 90.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3574486 1.77% 92.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3423610 1.69% 94.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11331200 5.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 89873367 44.67% 44.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 39509516 19.64% 64.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 17955811 8.92% 73.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13150988 6.54% 79.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 14566158 7.24% 87.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7624448 3.79% 90.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3491536 1.74% 92.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3420028 1.70% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11614530 5.77% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 202340295 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 201206382 # Number of insts commited each cycle system.cpu.commit.count 349066626 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 177024823 # Number of memory references committed @@ -300,50 +300,50 @@ system.cpu.commit.branches 30521875 # Nu system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279585913 # Number of committed integer instructions. system.cpu.commit.function_calls 6225114 # Number of function calls committed. -system.cpu.commit.bw_lim_events 11331200 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 11614530 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 591006103 # The number of ROB reads -system.cpu.rob.rob_writes 807880090 # The number of ROB writes -system.cpu.timesIdled 2572 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 112051 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 587888511 # The number of ROB reads +system.cpu.rob.rob_writes 804230779 # The number of ROB writes +system.cpu.timesIdled 2579 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 112751 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 349066014 # Number of Instructions Simulated system.cpu.committedInsts_total 349066014 # Number of Instructions Simulated -system.cpu.cpi 0.602551 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.602551 # CPI: Total CPI of All Threads -system.cpu.ipc 1.659610 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.659610 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1778945060 # number of integer regfile reads -system.cpu.int_regfile_writes 235524211 # number of integer regfile writes -system.cpu.fp_regfile_reads 190068131 # number of floating regfile reads -system.cpu.fp_regfile_writes 134456133 # number of floating regfile writes -system.cpu.misc_regfile_reads 1007398689 # number of misc regfile reads +system.cpu.cpi 0.598591 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.598591 # CPI: Total CPI of All Threads +system.cpu.ipc 1.670591 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.670591 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1782159085 # number of integer regfile reads +system.cpu.int_regfile_writes 235889793 # number of integer regfile writes +system.cpu.fp_regfile_reads 188830050 # number of floating regfile reads +system.cpu.fp_regfile_writes 133876834 # number of floating regfile writes +system.cpu.misc_regfile_reads 1003607247 # number of misc regfile reads system.cpu.misc_regfile_writes 34422185 # number of misc regfile writes -system.cpu.icache.replacements 14113 # number of replacements -system.cpu.icache.tagsinuse 1843.325990 # Cycle average of tags in use -system.cpu.icache.total_refs 41605379 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15990 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2601.962414 # Average number of references to valid blocks. +system.cpu.icache.replacements 14102 # number of replacements +system.cpu.icache.tagsinuse 1840.385487 # Cycle average of tags in use +system.cpu.icache.total_refs 41239547 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15979 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2580.859065 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1843.325990 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.900062 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 41605379 # number of ReadReq hits -system.cpu.icache.demand_hits 41605379 # number of demand (read+write) hits -system.cpu.icache.overall_hits 41605379 # number of overall hits -system.cpu.icache.ReadReq_misses 16651 # number of ReadReq misses -system.cpu.icache.demand_misses 16651 # number of demand (read+write) misses -system.cpu.icache.overall_misses 16651 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 201600500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 201600500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 201600500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 41622030 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 41622030 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 41622030 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000400 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000400 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000400 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 12107.410966 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 12107.410966 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 12107.410966 # average overall miss latency +system.cpu.icache.occ_blocks::0 1840.385487 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.898626 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 41239547 # number of ReadReq hits +system.cpu.icache.demand_hits 41239547 # number of demand (read+write) hits +system.cpu.icache.overall_hits 41239547 # number of overall hits +system.cpu.icache.ReadReq_misses 16635 # number of ReadReq misses +system.cpu.icache.demand_misses 16635 # number of demand (read+write) misses +system.cpu.icache.overall_misses 16635 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 200891500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 200891500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 200891500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 41256182 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 41256182 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 41256182 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000403 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000403 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000403 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 12076.435227 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 12076.435227 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 12076.435227 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,67 +353,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 658 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 658 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 658 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 15993 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 15993 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 15993 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 640 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 640 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 640 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 15995 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 15995 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 15995 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 136019500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 136019500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 136019500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 135868500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 135868500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 135868500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000384 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000384 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000384 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 8504.939661 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 8504.939661 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 8504.939661 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000388 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000388 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000388 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 8494.435761 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 8494.435761 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 8494.435761 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1412 # number of replacements -system.cpu.dcache.tagsinuse 3102.801650 # Cycle average of tags in use -system.cpu.dcache.total_refs 177884115 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4603 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 38645.256355 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1418 # number of replacements +system.cpu.dcache.tagsinuse 3101.734429 # Cycle average of tags in use +system.cpu.dcache.total_refs 176600871 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4608 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 38324.841797 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3102.801650 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.757520 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 95828379 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 82033251 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 11362 # number of LoadLockedReq hits +system.cpu.dcache.occ_blocks::0 3101.734429 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.757259 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 94544101 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 82033265 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 12379 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits 11110 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 177861630 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 177861630 # number of overall hits -system.cpu.dcache.ReadReq_misses 3434 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 19443 # number of WriteReq misses +system.cpu.dcache.demand_hits 176577366 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 176577366 # number of overall hits +system.cpu.dcache.ReadReq_misses 3426 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 19429 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 22877 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 22877 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 113492500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 646306000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 22855 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 22855 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 112688000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 648331000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 76000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 759798500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 759798500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 95831813 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 761019000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 761019000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 94547527 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 82052694 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 11364 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses 12381 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses 11110 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 177884507 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 177884507 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses 176600221 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 176600221 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.000036 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.000237 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000176 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.000162 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate 0.000129 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33049.650553 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33241.063622 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 32892.002335 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33369.241855 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33212.331162 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33212.331162 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 33297.702910 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33297.702910 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 307000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,73 +422,73 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 27909.090909 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1031 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1669 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 16602 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 1035 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1659 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 16572 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 18271 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 18271 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1765 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 2841 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 4606 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 4606 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 18231 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 18231 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1767 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 2857 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 4624 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 4624 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 53909000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 100913500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 154822500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 154822500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 53837000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 101449500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 155286500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 155286500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30543.342776 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35520.415347 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33613.221884 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33613.221884 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30468.024901 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35509.100455 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 33582.720588 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 33582.720588 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 60 # number of replacements -system.cpu.l2cache.tagsinuse 3910.737339 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13339 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 5367 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.485374 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 59 # number of replacements +system.cpu.l2cache.tagsinuse 3910.433469 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13338 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 5362 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.487505 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3534.138059 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 376.599280 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.107853 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.011493 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 13255 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1031 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 18 # number of ReadExReq hits +system.cpu.l2cache.occ_blocks::0 3528.791205 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 381.642264 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.107690 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.011647 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 13254 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 1035 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 19 # number of ReadExReq hits system.cpu.l2cache.demand_hits 13273 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 13273 # number of overall hits -system.cpu.l2cache.ReadReq_misses 4498 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 3 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 2821 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 7319 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 7319 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 154344500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 97273500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 251618000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 251618000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 17753 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 1031 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 3 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 2839 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 20592 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 20592 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.253366 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4491 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 16 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 2823 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 7314 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 7314 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 154072000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 97347500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 251419500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 251419500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 17745 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 1035 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 16 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 2842 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 20587 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 20587 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.253085 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.993660 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.355429 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.355429 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34314.028457 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34481.921305 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34378.740265 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34378.740265 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate 0.993315 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.355273 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.355273 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34306.835894 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34483.705278 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34375.102543 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34375.102543 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -498,31 +498,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets no_value system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 55 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 55 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 55 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 4443 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 3 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 2821 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 7264 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 7264 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 56 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 4435 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 16 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 2823 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 7258 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 7258 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 138429500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 93000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 88249000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 226678500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 226678500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 138176000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 497000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 88317500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 226493500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 226493500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250268 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.249930 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.993660 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.352758 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.352758 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31156.763448 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31282.878412 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31205.740639 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31205.740639 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.993315 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.352553 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.352553 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31155.806088 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31062.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31284.980517 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31206.048498 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31206.048498 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index dafa0fb4e..7c1b2f7e5 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/alpha/tru64/perlbmk +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout index fd41e0859..ec96cb05b 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 14:47:20 -gem5 started Aug 17 2011 14:48:53 -gem5 executing on nadc-0388 -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing +gem5 compiled Aug 20 2011 16:10:02 +gem5 started Aug 20 2011 21:33:28 +gem5 executing on zizzer +command line: ./build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -1387,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 643202937500 because target called exit() +Exiting @ tick 643030478500 because target called exit() diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 4a7021e39..c68641234 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.643203 # Number of seconds simulated -sim_ticks 643202937500 # Number of ticks simulated +sim_seconds 0.643030 # Number of seconds simulated +sim_ticks 643030478500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118321 # Simulator instruction rate (inst/s) -host_tick_rate 41745715 # Simulator tick rate (ticks/s) -host_mem_usage 258992 # Number of bytes of host memory used -host_seconds 15407.64 # Real time elapsed on the host +host_inst_rate 153773 # Simulator instruction rate (inst/s) +host_tick_rate 54239400 # Simulator tick rate (ticks/s) +host_mem_usage 218648 # Number of bytes of host memory used +host_seconds 11855.41 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 521221532 # DTB read hits -system.cpu.dtb.read_misses 658922 # DTB read misses +system.cpu.dtb.read_hits 520282071 # DTB read hits +system.cpu.dtb.read_misses 658976 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 521880454 # DTB read accesses -system.cpu.dtb.write_hits 283840599 # DTB write hits -system.cpu.dtb.write_misses 53844 # DTB write misses +system.cpu.dtb.read_accesses 520941047 # DTB read accesses +system.cpu.dtb.write_hits 283837075 # DTB write hits +system.cpu.dtb.write_misses 53680 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 283894443 # DTB write accesses -system.cpu.dtb.data_hits 805062131 # DTB hits -system.cpu.dtb.data_misses 712766 # DTB misses +system.cpu.dtb.write_accesses 283890755 # DTB write accesses +system.cpu.dtb.data_hits 804119146 # DTB hits +system.cpu.dtb.data_misses 712656 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 805774897 # DTB accesses -system.cpu.itb.fetch_hits 397823764 # ITB hits -system.cpu.itb.fetch_misses 725 # ITB misses +system.cpu.dtb.data_accesses 804831802 # DTB accesses +system.cpu.itb.fetch_hits 398310361 # ITB hits +system.cpu.itb.fetch_misses 225 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 397824489 # ITB accesses +system.cpu.itb.fetch_accesses 398310586 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,105 +41,105 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1286405876 # number of cpu cycles simulated +system.cpu.numCycles 1286060958 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 405275257 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 268833866 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 28893642 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 333881027 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 271480389 # Number of BTB hits +system.cpu.BPredUnit.lookups 402586298 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 267183275 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 28898117 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 333702913 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 271687015 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 61000600 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 7280 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 414544439 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3356501340 # Number of instructions fetch has processed -system.cpu.fetch.Branches 405275257 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 332480989 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 645561828 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 165819576 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 89727975 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 144 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8688 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 397823764 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11262885 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1286279412 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.609465 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.137305 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 60998120 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 7269 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 415096525 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3352093116 # Number of instructions fetch has processed +system.cpu.fetch.Branches 402586298 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 332685135 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 645195661 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 165271358 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 89752324 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 146 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 4176 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 398310361 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11197226 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1285935042 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.606736 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.132660 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 640717584 49.81% 49.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 58299040 4.53% 54.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 45001912 3.50% 57.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 73771739 5.74% 63.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 133047831 10.34% 73.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 43938688 3.42% 77.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 44398585 3.45% 80.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8225279 0.64% 81.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 238878754 18.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 640739381 49.83% 49.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 57260959 4.45% 54.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 45174683 3.51% 57.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 73956325 5.75% 63.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 134643957 10.47% 74.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 43704830 3.40% 77.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 44948525 3.50% 80.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8228368 0.64% 81.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 237278014 18.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1286279412 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.315045 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.609209 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 450708217 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 71469346 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 618883502 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8794467 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 136423880 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 31952374 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12567 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3256988723 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46034 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 136423880 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 480780652 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 28986921 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 25443 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 596262671 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 43799845 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3155534506 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 361 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 750713 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 36610303 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2106671791 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3701604314 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3589409458 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 112194856 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1285935042 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.313038 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.606481 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 451176980 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 71498937 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 618592802 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8792068 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 135874255 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 30910962 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12070 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3252787569 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 45959 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 135874255 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 481268394 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 29024257 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 25510 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 595950971 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 43791655 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3151351284 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 355 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 750555 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 36590752 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2105050619 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3698513195 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3586317765 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 112195430 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 721702721 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 720081549 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4177 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 80 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 124087461 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 734648354 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 345535584 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 65345430 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8881163 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2648024906 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 73 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2157432904 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17936053 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 824509507 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 785295716 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 34 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1286279412 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.677266 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.768750 # Number of insts issued each cycle +system.cpu.rename.tempSerializingInsts 82 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 124172087 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 732020123 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 345520616 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 66357929 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8901879 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2642218507 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 75 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2155449111 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17941201 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 818701684 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 780988431 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 36 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1285935042 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.676173 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.767949 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 465105327 36.16% 36.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 230071053 17.89% 54.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 242758793 18.87% 72.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 128578664 10.00% 82.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 105900340 8.23% 91.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 71932968 5.59% 96.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 23608439 1.84% 98.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15399185 1.20% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2924643 0.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 465245543 36.18% 36.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 229606292 17.86% 54.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 242969112 18.89% 72.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 129449912 10.07% 83.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 105111994 8.17% 91.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 71454382 5.56% 96.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 23774402 1.85% 98.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15398679 1.20% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2924726 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1286279412 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1285935042 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 19331 0.06% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 19151 0.06% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.06% # attempts to use FU when none available @@ -168,119 +168,119 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.06% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 21353871 65.69% 65.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 11133961 34.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 21356146 65.69% 65.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 11134345 34.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1239877099 57.47% 57.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 16703 0.00% 57.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27850919 1.29% 58.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254688 0.38% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204646 0.33% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 584763483 27.10% 86.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 289462610 13.42% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1238361266 57.45% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 16703 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27850917 1.29% 58.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254688 0.38% 59.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204646 0.33% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 584304865 27.11% 86.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 289453270 13.43% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2157432904 # Type of FU issued -system.cpu.iq.rate 1.677101 # Inst issue rate -system.cpu.iq.fu_busy_cnt 32507163 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015068 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5503111685 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3393642997 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1992487598 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 148476751 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 78968549 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 72622879 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2114296007 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 75641308 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 68640915 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2155449111 # Type of FU issued +system.cpu.iq.rate 1.676009 # Inst issue rate +system.cpu.iq.fu_busy_cnt 32509642 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015083 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5498808910 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3382020905 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1990959088 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 148475197 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 78969876 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 72622847 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2112315501 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 75640500 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 67702370 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 223578328 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1131278 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 78241 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 134740688 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 220950097 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 171000 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 71734 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 134725720 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4435 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 4434 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 136423880 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3817759 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 203214 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3011242942 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2752328 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 734648354 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 345535584 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 73 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 131783 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4925 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 78241 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 30717052 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 905851 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 31622903 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2068736315 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 521880619 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 88696589 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 135874255 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3818188 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 203306 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3005431260 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2750522 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 732020123 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 345520616 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 75 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 131111 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4921 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 71734 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 30723187 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 903682 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 31626869 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2066254472 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 520941220 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 89194639 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 363217963 # number of nop insts executed -system.cpu.iew.exec_refs 805775787 # number of memory reference insts executed -system.cpu.iew.exec_branches 280804576 # Number of branches executed -system.cpu.iew.exec_stores 283895168 # Number of stores executed -system.cpu.iew.exec_rate 1.608152 # Inst execution rate -system.cpu.iew.wb_sent 2067101811 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2065110477 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1176977005 # num instructions producing a value -system.cpu.iew.wb_consumers 1742514296 # num instructions consuming a value +system.cpu.iew.exec_nop 363212678 # number of nop insts executed +system.cpu.iew.exec_refs 804832688 # number of memory reference insts executed +system.cpu.iew.exec_branches 279771397 # Number of branches executed +system.cpu.iew.exec_stores 283891468 # Number of stores executed +system.cpu.iew.exec_rate 1.606654 # Inst execution rate +system.cpu.iew.wb_sent 2065581707 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2063581935 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1176945723 # num instructions producing a value +system.cpu.iew.wb_consumers 1742555439 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.605334 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.675448 # average fanout of values written-back +system.cpu.iew.wb_rate 1.604576 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.675414 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 985541279 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 979738658 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 28881185 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1149855532 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.747165 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.514043 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 28886163 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1150060787 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.746853 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.513737 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 542912132 47.22% 47.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 216611408 18.84% 66.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119775528 10.42% 76.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 61140403 5.32% 81.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 44127401 3.84% 85.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24962604 2.17% 87.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19277030 1.68% 89.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 15973081 1.39% 90.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 105075945 9.14% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 543040951 47.22% 47.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 216685952 18.84% 66.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119778809 10.41% 76.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 61132291 5.32% 81.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 44136002 3.84% 85.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24968433 2.17% 87.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19265020 1.68% 89.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 16055764 1.40% 90.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 104997565 9.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1149855532 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1150060787 # Number of insts commited each cycle system.cpu.commit.count 2008987604 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 721864922 # Number of memory references committed @@ -290,50 +290,50 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 105075945 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 104997565 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4033672060 # The number of ROB reads -system.cpu.rob.rob_writes 6125668302 # The number of ROB writes -system.cpu.timesIdled 3523 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 126464 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 4028153074 # The number of ROB reads +system.cpu.rob.rob_writes 6113513811 # The number of ROB writes +system.cpu.timesIdled 3507 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 125916 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.705636 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.705636 # CPI: Total CPI of All Threads -system.cpu.ipc 1.417160 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.417160 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2632175047 # number of integer regfile reads -system.cpu.int_regfile_writes 1493512495 # number of integer regfile writes -system.cpu.fp_regfile_reads 77824339 # number of floating regfile reads -system.cpu.fp_regfile_writes 52831274 # number of floating regfile writes +system.cpu.cpi 0.705447 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.705447 # CPI: Total CPI of All Threads +system.cpu.ipc 1.417540 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.417540 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2630724063 # number of integer regfile reads +system.cpu.int_regfile_writes 1493026464 # number of integer regfile writes +system.cpu.fp_regfile_reads 77824314 # number of floating regfile reads +system.cpu.fp_regfile_writes 52830391 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8247 # number of replacements -system.cpu.icache.tagsinuse 1649.560479 # Cycle average of tags in use -system.cpu.icache.total_refs 397812655 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 9954 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 39965.104983 # Average number of references to valid blocks. +system.cpu.icache.replacements 8239 # number of replacements +system.cpu.icache.tagsinuse 1650.873085 # Cycle average of tags in use +system.cpu.icache.total_refs 398299261 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 9946 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 40046.175447 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1649.560479 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.805449 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 397812655 # number of ReadReq hits -system.cpu.icache.demand_hits 397812655 # number of demand (read+write) hits -system.cpu.icache.overall_hits 397812655 # number of overall hits -system.cpu.icache.ReadReq_misses 11109 # number of ReadReq misses -system.cpu.icache.demand_misses 11109 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11109 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 182768000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 182768000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 182768000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 397823764 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 397823764 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 397823764 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 1650.873085 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.806090 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 398299261 # number of ReadReq hits +system.cpu.icache.demand_hits 398299261 # number of demand (read+write) hits +system.cpu.icache.overall_hits 398299261 # number of overall hits +system.cpu.icache.ReadReq_misses 11100 # number of ReadReq misses +system.cpu.icache.demand_misses 11100 # number of demand (read+write) misses +system.cpu.icache.overall_misses 11100 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 182477500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 182477500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 182477500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 398310361 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 398310361 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 398310361 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000028 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000028 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000028 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 16452.245927 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 16452.245927 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 16452.245927 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 16439.414414 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 16439.414414 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 16439.414414 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -343,65 +343,65 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1154 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1154 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1154 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 9955 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 9955 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 9955 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1153 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1153 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1153 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 9947 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 9947 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 9947 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 119824500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 119824500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 119824500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 119555000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 119555000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 119555000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12036.614766 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12036.614766 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12036.614766 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12019.201769 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12019.201769 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12019.201769 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1527589 # number of replacements -system.cpu.dcache.tagsinuse 4095.113908 # Cycle average of tags in use -system.cpu.dcache.total_refs 660891120 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1531685 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 431.479789 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 255450000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4095.113908 # Average occupied blocks per context +system.cpu.dcache.replacements 1527592 # number of replacements +system.cpu.dcache.tagsinuse 4095.113983 # Cycle average of tags in use +system.cpu.dcache.total_refs 660890207 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1531688 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 431.478347 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 255376000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4095.113983 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999784 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 450647870 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 210243240 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 10 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 660891110 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 660891110 # number of overall hits -system.cpu.dcache.ReadReq_misses 1928288 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 551656 # number of WriteReq misses +system.cpu.dcache.ReadReq_hits 450646939 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 210243259 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 660890198 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 660890198 # number of overall hits +system.cpu.dcache.ReadReq_misses 1928305 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 551637 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 2479944 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2479944 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 71428228500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 20878086491 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 2479942 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2479942 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 71444429000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 20878144491 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 59000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 92306314991 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 92306314991 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 452576158 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 92322573491 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 92322573491 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 452575244 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 12 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 663371054 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 663371054 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 663370140 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 663370140 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.004261 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.002617 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate 0.003738 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.003738 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 37042.303069 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 37846.205771 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 37050.377923 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 37847.614448 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 29500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 37221.128780 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 37221.128780 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 37227.714798 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 37227.714798 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 79500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 20500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked @@ -410,74 +410,74 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 5678.571429 system.cpu.dcache.avg_blocked_cycles::no_targets 20500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 107322 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 468211 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 480049 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 107326 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 468223 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 480032 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 948260 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 948260 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1460077 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 71607 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits 948255 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 948255 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1460082 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 71605 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1531684 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1531684 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 1531687 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1531687 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 49926913500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2493150500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 49942277500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2493130000 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 52420064000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 52420064000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 52435407500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 52435407500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.003226 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.083333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.090909 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.002309 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.002309 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34194.712676 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34817.133800 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34205.118274 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34817.819985 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34223.811178 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34223.811178 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34233.761532 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34233.761532 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480632 # number of replacements -system.cpu.l2cache.tagsinuse 31936.096319 # Cycle average of tags in use -system.cpu.l2cache.total_refs 63580 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1513319 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.042014 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1480630 # number of replacements +system.cpu.l2cache.tagsinuse 31935.913288 # Cycle average of tags in use +system.cpu.l2cache.total_refs 63583 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1513317 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.042016 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 28877.574420 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3058.521899 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.881274 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.093339 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 55956 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 107322 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 4752 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 60708 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 60708 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1414077 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::0 28876.475418 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 3059.437870 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.881240 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.093367 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 55959 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 107326 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 4750 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 60709 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 60709 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1414071 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 66855 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 1480932 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 1480932 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 48498416000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2349022500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 50847438500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 50847438500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1470033 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 107322 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 71607 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 1541640 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 1541640 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.961936 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.933638 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.960621 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.960621 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34296.870680 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 35136.078079 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34334.755748 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34334.755748 # average overall miss latency +system.cpu.l2cache.demand_misses 1480926 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 1480926 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 48513510000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2349021500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 50862531500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 50862531500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1470030 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 107326 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 71605 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 1541635 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 1541635 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.961933 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.933664 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.960620 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.960620 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34307.690349 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 35136.063122 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34345.086453 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34345.086453 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -489,24 +489,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 66898 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1414077 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 1414071 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 66855 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 1480932 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 1480932 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 1480926 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 1480926 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 43837572000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2147697500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 45985269500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 45985269500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 43837380500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2147695000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 45985075500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 45985075500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.961936 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.933638 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.960621 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.960621 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.838002 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32124.710194 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.573941 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.573941 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.961933 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.933664 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.960620 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.960620 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.834117 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32124.672799 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.568748 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.568748 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini index af0d319dc..d6e8feb5e 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout index b7bd4cae8..d1d73ccec 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 18 2011 17:30:35 -gem5 started Aug 18 2011 18:30:12 -gem5 executing on nadc-0330 +gem5 compiled Sep 11 2011 21:12:14 +gem5 started Sep 11 2011 21:52:21 +gem5 executing on u200439-lin.austin.arm.com command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1387,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 721574387500 because target called exit() +Exiting @ tick 708531477500 because target called exit() diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 2aa37fbb0..51c2df969 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.721574 # Number of seconds simulated -sim_ticks 721574387500 # Number of ticks simulated +sim_seconds 0.708531 # Number of seconds simulated +sim_ticks 708531477500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93472 # Simulator instruction rate (inst/s) -host_tick_rate 35774469 # Simulator tick rate (ticks/s) -host_mem_usage 269932 # Number of bytes of host memory used -host_seconds 20170.09 # Real time elapsed on the host +host_inst_rate 73177 # Simulator instruction rate (inst/s) +host_tick_rate 27500789 # Simulator tick rate (ticks/s) +host_mem_usage 269872 # Number of bytes of host memory used +host_seconds 25764.04 # Real time elapsed on the host sim_insts 1885333781 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses @@ -51,247 +51,247 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1443148776 # number of cpu cycles simulated +system.cpu.numCycles 1417062956 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 514101790 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 393960342 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 32849417 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 411992130 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 292369997 # Number of BTB hits +system.cpu.BPredUnit.lookups 503197532 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 388248962 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 32912455 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 402367124 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 282669140 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 61143344 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2847666 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 422838137 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2603354590 # Number of instructions fetch has processed -system.cpu.fetch.Branches 514101790 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 353513341 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 695385496 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 212683081 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 100667444 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2128 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 34744 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 396353337 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 13400662 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1391803250 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.587957 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.156576 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 59794264 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2845178 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 410598466 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2543215501 # Number of instructions fetch has processed +system.cpu.fetch.Branches 503197532 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 342463404 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 683221197 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 205184289 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 105176674 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2131 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 34940 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 384286264 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 12168665 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1365728364 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.589436 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.160278 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 696457133 50.04% 50.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 48140413 3.46% 53.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 109472309 7.87% 61.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 63203054 4.54% 65.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 93420590 6.71% 72.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 55467471 3.99% 76.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38010894 2.73% 79.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 34903580 2.51% 81.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 252727806 18.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 682546834 49.98% 49.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 48268776 3.53% 53.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 108820649 7.97% 61.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 62416445 4.57% 66.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 89329433 6.54% 72.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 54222188 3.97% 76.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 35559819 2.60% 79.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 34994936 2.56% 81.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 249569284 18.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1391803250 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.356236 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.803941 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 467512838 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 82010941 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 659587023 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9830183 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 172862265 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 71310699 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13247 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3482203473 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 23181 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 172862265 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 507308890 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 29017787 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3569068 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 628144166 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 50901074 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3355358425 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 75 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4098898 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 41311851 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 10 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3338398637 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 15926092867 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 15179476932 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 746615935 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1365728364 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.355099 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.794709 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 455451885 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 84966420 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 647527818 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 11100617 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 166681624 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 68771353 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13534 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3425616416 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 23343 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 166681624 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 496974681 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 29107016 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3577336 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 615567899 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53819808 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3299332882 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 85 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4545741 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 42264080 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 3261811960 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 15630618087 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 14995522132 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 635095955 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993153591 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1345245041 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 293826 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 289544 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 148458476 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1060445315 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 528215229 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 34855006 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 42545066 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 3129553839 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 287167 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2641710303 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18698476 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1243985610 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3101856113 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 77249 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1391803250 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.898049 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.895078 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1268658364 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 292165 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 287873 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 155635348 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1045682058 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 527865899 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 35886161 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 45188431 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 3078949788 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 286075 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2620068122 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18730048 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1193263945 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2902703474 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 76157 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1365728364 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.918440 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.900398 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 496637821 35.68% 35.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 187318392 13.46% 49.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 216683253 15.57% 64.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 183278078 13.17% 77.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 154759947 11.12% 89.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 88115850 6.33% 95.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 48435610 3.48% 98.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11635919 0.84% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4938380 0.35% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 480776818 35.20% 35.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 182697295 13.38% 48.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 216773103 15.87% 64.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 179469890 13.14% 77.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 151098316 11.06% 88.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 89760948 6.57% 95.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 48715298 3.57% 98.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11568409 0.85% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4868287 0.36% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1391803250 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1365728364 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2241949 2.46% 2.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 23931 0.03% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55591183 61.06% 63.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 33183599 36.45% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2047633 2.26% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 23928 0.03% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.28% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55695213 61.39% 63.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 32952568 36.32% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1209438891 45.78% 45.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11231174 0.43% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 6786 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876480 0.26% 46.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5505922 0.21% 46.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 24487735 0.93% 47.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 908321415 34.38% 82.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 474466611 17.96% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1201100528 45.84% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11234357 0.43% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 6823 0.00% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876481 0.26% 46.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5505298 0.21% 46.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 24361440 0.93% 47.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 896104682 34.20% 81.93% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 473503224 18.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2641710303 # Type of FU issued -system.cpu.iq.rate 1.830518 # Inst issue rate -system.cpu.iq.fu_busy_cnt 91040662 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.034463 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6653435449 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4251253883 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2425638071 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 131527545 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 124012557 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 57076576 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2665613044 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 67137921 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 72083065 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2620068122 # Type of FU issued +system.cpu.iq.rate 1.848943 # Inst issue rate +system.cpu.iq.fu_busy_cnt 90719342 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.034625 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6586805397 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4173231874 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2409969161 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 128508601 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 99321062 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 57077308 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2645158963 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 65628501 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 72009285 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 429056446 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 91786 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 2776714 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 251218246 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 414293189 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 264533 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1389891 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 250868916 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 88 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 87 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 172862265 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16375195 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1473977 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3129909418 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 11871497 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1060445315 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 528215229 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 275665 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1470985 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 210 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 2776714 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 34610253 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8646611 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 43256864 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2550234981 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 850160020 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 91475322 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 166681624 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16374995 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1474320 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3079304358 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 12740517 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1045682058 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 527865899 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 274568 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1470984 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 216 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1389891 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 34543873 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8891706 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 43435579 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2534937994 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 842579419 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 85130128 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 68412 # number of nop insts executed -system.cpu.iew.exec_refs 1303401841 # number of memory reference insts executed -system.cpu.iew.exec_branches 346693404 # Number of branches executed -system.cpu.iew.exec_stores 453241821 # Number of stores executed -system.cpu.iew.exec_rate 1.767132 # Inst execution rate -system.cpu.iew.wb_sent 2511392174 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2482714647 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1457352486 # num instructions producing a value -system.cpu.iew.wb_consumers 2693773506 # num instructions consuming a value +system.cpu.iew.exec_nop 68495 # number of nop insts executed +system.cpu.iew.exec_refs 1294824342 # number of memory reference insts executed +system.cpu.iew.exec_branches 344662618 # Number of branches executed +system.cpu.iew.exec_stores 452244923 # Number of stores executed +system.cpu.iew.exec_rate 1.788868 # Inst execution rate +system.cpu.iew.wb_sent 2496106713 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2467046469 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1448587293 # num instructions producing a value +system.cpu.iew.wb_consumers 2708320532 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.720346 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.541008 # average fanout of values written-back +system.cpu.iew.wb_rate 1.740958 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.534866 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1885344797 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 1244525975 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1193920948 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 209918 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 38374226 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1218940987 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.546707 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.221520 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 38436982 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1199046742 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.572370 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.256600 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 542456201 44.50% 44.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 304987693 25.02% 69.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110181944 9.04% 78.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 79585029 6.53% 85.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 53872031 4.42% 89.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24566271 2.02% 91.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 17102531 1.40% 92.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9210832 0.76% 93.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 76978455 6.32% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 532251438 44.39% 44.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 299124354 24.95% 69.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 106727923 8.90% 78.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 77554525 6.47% 84.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 53347084 4.45% 89.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23351353 1.95% 91.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 17117984 1.43% 92.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9328631 0.78% 93.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 80243450 6.69% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1218940987 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1199046742 # Number of insts commited each cycle system.cpu.commit.count 1885344797 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 908385851 # Number of memory references committed @@ -301,50 +301,50 @@ system.cpu.commit.branches 291350231 # Nu system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. system.cpu.commit.int_insts 1653705619 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 76978455 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 80243450 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4271814959 # The number of ROB reads -system.cpu.rob.rob_writes 6432618886 # The number of ROB writes -system.cpu.timesIdled 1340911 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 51345526 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 4198050692 # The number of ROB reads +system.cpu.rob.rob_writes 6325233568 # The number of ROB writes +system.cpu.timesIdled 1340861 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 51334592 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1885333781 # Number of Instructions Simulated system.cpu.committedInsts_total 1885333781 # Number of Instructions Simulated -system.cpu.cpi 0.765461 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.765461 # CPI: Total CPI of All Threads -system.cpu.ipc 1.306403 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.306403 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12650608214 # number of integer regfile reads -system.cpu.int_regfile_writes 2377451435 # number of integer regfile writes -system.cpu.fp_regfile_reads 68801235 # number of floating regfile reads -system.cpu.fp_regfile_writes 50191358 # number of floating regfile writes -system.cpu.misc_regfile_reads 4051722338 # number of misc regfile reads +system.cpu.cpi 0.751624 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.751624 # CPI: Total CPI of All Threads +system.cpu.ipc 1.330452 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.330452 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12569578143 # number of integer regfile reads +system.cpu.int_regfile_writes 2360113760 # number of integer regfile writes +system.cpu.fp_regfile_reads 68800138 # number of floating regfile reads +system.cpu.fp_regfile_writes 50190994 # number of floating regfile writes +system.cpu.misc_regfile_reads 3981621400 # number of misc regfile reads system.cpu.misc_regfile_writes 13776274 # number of misc regfile writes -system.cpu.icache.replacements 27265 # number of replacements -system.cpu.icache.tagsinuse 1631.022811 # Cycle average of tags in use -system.cpu.icache.total_refs 396319184 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 28937 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13695.931990 # Average number of references to valid blocks. +system.cpu.icache.replacements 27318 # number of replacements +system.cpu.icache.tagsinuse 1634.845440 # Cycle average of tags in use +system.cpu.icache.total_refs 384252011 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 28994 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13252.811306 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1631.022811 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.796398 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 396319190 # number of ReadReq hits -system.cpu.icache.demand_hits 396319190 # number of demand (read+write) hits -system.cpu.icache.overall_hits 396319190 # number of overall hits -system.cpu.icache.ReadReq_misses 34147 # number of ReadReq misses -system.cpu.icache.demand_misses 34147 # number of demand (read+write) misses -system.cpu.icache.overall_misses 34147 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 302756000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 302756000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 302756000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 396353337 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 396353337 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 396353337 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000086 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000086 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000086 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 8866.254722 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 8866.254722 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 8866.254722 # average overall miss latency +system.cpu.icache.occ_blocks::0 1634.845440 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.798264 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 384252124 # number of ReadReq hits +system.cpu.icache.demand_hits 384252124 # number of demand (read+write) hits +system.cpu.icache.overall_hits 384252124 # number of overall hits +system.cpu.icache.ReadReq_misses 34140 # number of ReadReq misses +system.cpu.icache.demand_misses 34140 # number of demand (read+write) misses +system.cpu.icache.overall_misses 34140 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 301222000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 301222000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 301222000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 384286264 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 384286264 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 384286264 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000089 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000089 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000089 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 8823.140012 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 8823.140012 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 8823.140012 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,67 +354,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 858 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 858 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 858 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 33289 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 33289 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 33289 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 774 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 774 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 774 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 33366 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 33366 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 33366 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 180196000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 180196000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 180196000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 180870500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 180870500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 180870500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000084 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5413.079396 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5413.079396 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5413.079396 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000087 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000087 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000087 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 5420.802613 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 5420.802613 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 5420.802613 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1531918 # number of replacements -system.cpu.dcache.tagsinuse 4094.807844 # Cycle average of tags in use -system.cpu.dcache.total_refs 1037036260 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1536014 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 675.147661 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 306953000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.807844 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999709 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 760874912 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 276118613 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 15353 # number of LoadLockedReq hits +system.cpu.dcache.replacements 1531930 # number of replacements +system.cpu.dcache.tagsinuse 4094.787279 # Cycle average of tags in use +system.cpu.dcache.total_refs 1029517706 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1536026 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 670.247578 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 306646000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.787279 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999704 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 753359421 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 276118539 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 14346 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits 11671 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 1036993525 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1036993525 # number of overall hits -system.cpu.dcache.ReadReq_misses 1940591 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 817065 # number of WriteReq misses +system.cpu.dcache.demand_hits 1029477960 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 1029477960 # number of overall hits +system.cpu.dcache.ReadReq_misses 1938279 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 817139 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 2757656 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2757656 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 69372468500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 28482649500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 2755418 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2755418 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 69353392500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 28486542000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 108500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 97855118000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 97855118000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 762815503 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 97839934500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 97839934500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 755297700 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 15356 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses 14349 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses 11671 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 1039751181 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 1039751181 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.002544 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.002950 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000195 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.002652 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.002652 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 35748.114105 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 34859.710672 # average WriteReq miss latency +system.cpu.dcache.demand_accesses 1032233378 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 1032233378 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.002566 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.002951 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.000209 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.002669 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.002669 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 35780.913119 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 34861.317352 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35484.889341 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35484.889341 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 35508.200389 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35508.200389 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 59500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -423,74 +423,74 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 14875 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 106488 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 477280 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 740009 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 106827 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 474953 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 740066 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1217289 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1217289 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1463311 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 77056 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1540367 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1540367 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 1215019 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1215019 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1463326 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 77073 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1540399 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1540399 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 50023449500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2483285500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 52506735000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 52506735000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 50026128000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2483951500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 52510079500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 52510079500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001918 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001937 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.001481 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.001481 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34185.111367 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32227.023204 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34087.159099 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34087.159099 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.001492 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.001492 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34186.591368 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32228.556044 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34088.622169 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34088.622169 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480007 # number of replacements -system.cpu.l2cache.tagsinuse 31971.458810 # Cycle average of tags in use -system.cpu.l2cache.total_refs 84947 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1512726 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.056155 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1480043 # number of replacements +system.cpu.l2cache.tagsinuse 31970.970884 # Cycle average of tags in use +system.cpu.l2cache.total_refs 85321 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1512763 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.056401 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 29004.872731 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 2966.586079 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.885158 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.090533 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 76859 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 106488 # number of Writeback hits +system.cpu.l2cache.occ_blocks::0 29004.040754 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 2966.930131 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.885133 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.090544 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 76995 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 106827 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 6622 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 83481 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 83481 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1415390 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 4348 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 66082 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 1481472 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 1481472 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 48557740000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2252374000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 50810114000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 50810114000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1492249 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 106488 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 4352 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 72704 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 1564953 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 1564953 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.948495 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.999081 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.908918 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.946656 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.946656 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34306.968397 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34084.531340 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34297.046451 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34297.046451 # average overall miss latency +system.cpu.l2cache.ReadExReq_hits 6620 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 83615 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 83615 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1415326 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 4368 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 66081 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 1481407 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 1481407 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 48560731500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2252343000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 50813074500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 50813074500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1492321 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 106827 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 4372 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 72701 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 1565022 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 1565022 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.948406 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.999085 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.908942 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.946573 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.946573 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34310.633381 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34084.578018 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34300.549748 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34300.549748 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -499,32 +499,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 66099 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 26 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 26 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 26 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1415364 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 4348 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 66082 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 1481446 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 1481446 # number of overall MSHR misses +system.cpu.l2cache.writebacks 66098 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 25 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 25 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 1415301 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 4368 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 66081 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 1481382 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 1481382 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 43973597000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 134788000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048603500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 46022200500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 46022200500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 43971676000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 135408000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048571000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 46020247000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 46020247000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.948477 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.999081 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908918 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.946639 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.946639 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31068.754751 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.948389 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.999085 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908942 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.946557 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.946557 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31068.780422 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.930662 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31065.729362 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31065.729362 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.907977 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31065.752790 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31065.752790 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 3ed32454b..2f92d3206 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout index f4cba8212..6c1f5182e 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -3,11 +3,11 @@ Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 14:47:20 -gem5 started Aug 17 2011 14:49:49 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 16:10:02 +gem5 started Aug 20 2011 16:10:08 +gem5 executing on zizzer command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 21280925000 because target called exit() +Exiting @ tick 21259532000 because target called exit() diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 3555b3a9e..a5baa0129 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.021281 # Number of seconds simulated -sim_ticks 21280925000 # Number of ticks simulated +sim_seconds 0.021260 # Number of seconds simulated +sim_ticks 21259532000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145761 # Simulator instruction rate (inst/s) -host_tick_rate 38973060 # Simulator tick rate (ticks/s) -host_mem_usage 261392 # Number of bytes of host memory used -host_seconds 546.04 # Real time elapsed on the host +host_inst_rate 184165 # Simulator instruction rate (inst/s) +host_tick_rate 49191900 # Simulator tick rate (ticks/s) +host_mem_usage 214460 # Number of bytes of host memory used +host_seconds 432.18 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22306086 # DTB read hits -system.cpu.dtb.read_misses 214886 # DTB read misses -system.cpu.dtb.read_acv 39 # DTB read access violations -system.cpu.dtb.read_accesses 22520972 # DTB read accesses -system.cpu.dtb.write_hits 15626167 # DTB write hits -system.cpu.dtb.write_misses 39215 # DTB write misses -system.cpu.dtb.write_acv 8 # DTB write access violations -system.cpu.dtb.write_accesses 15665382 # DTB write accesses -system.cpu.dtb.data_hits 37932253 # DTB hits -system.cpu.dtb.data_misses 254101 # DTB misses -system.cpu.dtb.data_acv 47 # DTB access violations -system.cpu.dtb.data_accesses 38186354 # DTB accesses -system.cpu.itb.fetch_hits 13891710 # ITB hits -system.cpu.itb.fetch_misses 28310 # ITB misses +system.cpu.dtb.read_hits 22309038 # DTB read hits +system.cpu.dtb.read_misses 216523 # DTB read misses +system.cpu.dtb.read_acv 41 # DTB read access violations +system.cpu.dtb.read_accesses 22525561 # DTB read accesses +system.cpu.dtb.write_hits 15629688 # DTB write hits +system.cpu.dtb.write_misses 39366 # DTB write misses +system.cpu.dtb.write_acv 9 # DTB write access violations +system.cpu.dtb.write_accesses 15669054 # DTB write accesses +system.cpu.dtb.data_hits 37938726 # DTB hits +system.cpu.dtb.data_misses 255889 # DTB misses +system.cpu.dtb.data_acv 50 # DTB access violations +system.cpu.dtb.data_accesses 38194615 # DTB accesses +system.cpu.itb.fetch_hits 13877051 # ITB hits +system.cpu.itb.fetch_misses 28133 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13920020 # ITB accesses +system.cpu.itb.fetch_accesses 13905184 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,145 +41,145 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 42561853 # number of cpu cycles simulated +system.cpu.numCycles 42519067 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16631874 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10794462 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 464307 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 14557589 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8568490 # Number of BTB hits +system.cpu.BPredUnit.lookups 16615602 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10784809 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 464390 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 14543138 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8570194 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1988710 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 35321 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 14916531 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105870429 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16631874 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 10557200 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20627655 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2038131 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 4875496 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 5851 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 284921 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 13891710 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 223928 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 42166283 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.510784 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.107272 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1986002 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 35485 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 14905140 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105779121 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16615602 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 10556196 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20616414 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2026173 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 4867777 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 5763 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 282637 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 13877051 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 219292 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 42124503 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.511107 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.106328 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21538628 51.08% 51.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2127742 5.05% 56.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1681102 3.99% 60.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1999349 4.74% 64.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3923245 9.30% 74.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1939114 4.60% 78.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 766205 1.82% 80.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1130528 2.68% 83.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7060370 16.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21508089 51.06% 51.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2128231 5.05% 56.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1654689 3.93% 60.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2031982 4.82% 64.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3913911 9.29% 74.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1970832 4.68% 78.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 733979 1.74% 80.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1130432 2.68% 83.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7052358 16.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 42166283 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.390769 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.487449 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15993014 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4441023 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19696798 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 677140 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1358308 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3731142 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 99597 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 104002025 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 279031 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1358308 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16480266 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2358783 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 84134 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19842827 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2041965 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102626564 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 182 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2800 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1928739 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61750639 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123717887 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123241434 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 476453 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 42124503 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.390780 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.487804 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15964361 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4443062 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19692488 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 675645 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1348947 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3728678 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 99733 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103933078 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 280329 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1348947 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16452599 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2364451 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 84031 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19835916 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2038559 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102562493 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 192 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2676 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1925408 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61709040 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123636906 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123159992 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 476914 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9203758 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5461 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5458 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4160134 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23154536 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16249616 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1221790 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 569270 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90755871 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5414 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88285827 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 101429 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10871074 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4987897 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 831 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 42166283 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.093754 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.072730 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9162159 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5463 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5460 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4149992 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23138107 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16243401 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1017520 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 376699 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90712605 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5415 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88293060 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 101013 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10834162 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4923026 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 832 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 42124503 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.096002 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.077334 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13277522 31.49% 31.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7349165 17.43% 48.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5870534 13.92% 62.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4909942 11.64% 74.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4829345 11.45% 85.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2472819 5.86% 91.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1859151 4.41% 96.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1153053 2.73% 98.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 444752 1.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13300851 31.58% 31.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7326403 17.39% 48.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5817137 13.81% 62.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4863957 11.55% 74.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4880067 11.58% 85.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2467879 5.86% 91.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1850711 4.39% 96.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1163401 2.76% 98.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 454097 1.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 42166283 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 42124503 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 104351 5.76% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 742075 40.96% 46.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 965203 53.28% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 99927 5.41% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 762620 41.31% 46.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 983690 53.28% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49336133 55.88% 55.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 44096 0.05% 55.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49334128 55.88% 55.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 44107 0.05% 55.93% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 126791 0.14% 56.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 127304 0.14% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 53 0.00% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 126794 0.14% 56.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 90 0.00% 56.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 127284 0.14% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 54 0.00% 56.21% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 38913 0.04% 56.26% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.26% # Type of FU issued @@ -202,85 +202,85 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.26% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22760648 25.78% 82.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15851801 17.96% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22763265 25.78% 82.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15858425 17.96% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88285827 # Type of FU issued -system.cpu.iq.rate 2.074295 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1811630 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020520 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 220029766 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101198436 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86307444 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 621230 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 457830 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 302539 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 89786725 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 310732 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1421646 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88293060 # Type of FU issued +system.cpu.iq.rate 2.076552 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1846238 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.020910 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 220034609 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101108296 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86316001 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 623265 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 459484 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 302223 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 89827554 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 311744 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1421900 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2877898 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4388 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 24438 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1636239 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2861469 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4255 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 15998 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1630024 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1319 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 40 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1270 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1358308 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1393023 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 60290 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100252216 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 329475 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23154536 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16249616 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5414 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 42581 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 713 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 24438 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 304612 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 116704 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 421316 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87314896 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22523751 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 970931 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1348947 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1395228 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 60292 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100209488 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 330917 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23138107 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16243401 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5415 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 42613 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 717 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 15998 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 305754 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 116766 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 422520 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87324044 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22528336 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 969016 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9490931 # number of nop insts executed -system.cpu.iew.exec_refs 38189606 # number of memory reference insts executed -system.cpu.iew.exec_branches 15067894 # Number of branches executed -system.cpu.iew.exec_stores 15665855 # Number of stores executed -system.cpu.iew.exec_rate 2.051482 # Inst execution rate -system.cpu.iew.wb_sent 87005186 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86609983 # cumulative count of insts written-back -system.cpu.iew.wb_producers 32995140 # num instructions producing a value -system.cpu.iew.wb_consumers 43003754 # num instructions consuming a value +system.cpu.iew.exec_nop 9491468 # number of nop insts executed +system.cpu.iew.exec_refs 38197877 # number of memory reference insts executed +system.cpu.iew.exec_branches 15069707 # Number of branches executed +system.cpu.iew.exec_stores 15669541 # Number of stores executed +system.cpu.iew.exec_rate 2.053762 # Inst execution rate +system.cpu.iew.wb_sent 87015038 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86618224 # cumulative count of insts written-back +system.cpu.iew.wb_producers 32981280 # num instructions producing a value +system.cpu.iew.wb_consumers 42978824 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.034920 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.767262 # average fanout of values written-back +system.cpu.iew.wb_rate 2.037162 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.767384 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 8883927 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8835054 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 366786 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 40807975 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.164789 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.804222 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 366565 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 40775556 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.166511 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.804904 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17689673 43.35% 43.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7101779 17.40% 60.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3525291 8.64% 69.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2171268 5.32% 74.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2044082 5.01% 79.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1229518 3.01% 82.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1144487 2.80% 85.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 731349 1.79% 87.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5170528 12.67% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17645835 43.28% 43.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7080138 17.36% 60.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3592753 8.81% 69.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2169640 5.32% 74.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2013725 4.94% 79.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1230420 3.02% 82.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1128970 2.77% 85.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 727312 1.78% 87.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5186763 12.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 40807975 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 40775556 # Number of insts commited each cycle system.cpu.commit.count 88340672 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 34890015 # Number of memory references committed @@ -290,50 +290,50 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5170528 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5186763 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 131544704 # The number of ROB reads -system.cpu.rob.rob_writes 195810643 # The number of ROB writes -system.cpu.timesIdled 15962 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 395570 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 131447177 # The number of ROB reads +system.cpu.rob.rob_writes 195703293 # The number of ROB writes +system.cpu.timesIdled 15923 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 394564 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.534752 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.534752 # CPI: Total CPI of All Threads -system.cpu.ipc 1.870026 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.870026 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115501345 # number of integer regfile reads -system.cpu.int_regfile_writes 57352944 # number of integer regfile writes -system.cpu.fp_regfile_reads 252582 # number of floating regfile reads -system.cpu.fp_regfile_writes 251221 # number of floating regfile writes -system.cpu.misc_regfile_reads 38138 # number of misc regfile reads +system.cpu.cpi 0.534214 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.534214 # CPI: Total CPI of All Threads +system.cpu.ipc 1.871907 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.871907 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115518864 # number of integer regfile reads +system.cpu.int_regfile_writes 57354047 # number of integer regfile writes +system.cpu.fp_regfile_reads 252314 # number of floating regfile reads +system.cpu.fp_regfile_writes 251108 # number of floating regfile writes +system.cpu.misc_regfile_reads 38108 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 88299 # number of replacements -system.cpu.icache.tagsinuse 1927.175283 # Cycle average of tags in use -system.cpu.icache.total_refs 13796878 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 90347 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 152.709863 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 17859322000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1927.175283 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.941004 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 13796878 # number of ReadReq hits -system.cpu.icache.demand_hits 13796878 # number of demand (read+write) hits -system.cpu.icache.overall_hits 13796878 # number of overall hits -system.cpu.icache.ReadReq_misses 94832 # number of ReadReq misses -system.cpu.icache.demand_misses 94832 # number of demand (read+write) misses -system.cpu.icache.overall_misses 94832 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 914342000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 914342000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 914342000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 13891710 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 13891710 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 13891710 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.006827 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.006827 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.006827 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 9641.703223 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 9641.703223 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 9641.703223 # average overall miss latency +system.cpu.icache.replacements 88378 # number of replacements +system.cpu.icache.tagsinuse 1927.638696 # Cycle average of tags in use +system.cpu.icache.total_refs 13782143 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 90426 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 152.413498 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 17839872000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 1927.638696 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.941230 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 13782143 # number of ReadReq hits +system.cpu.icache.demand_hits 13782143 # number of demand (read+write) hits +system.cpu.icache.overall_hits 13782143 # number of overall hits +system.cpu.icache.ReadReq_misses 94908 # number of ReadReq misses +system.cpu.icache.demand_misses 94908 # number of demand (read+write) misses +system.cpu.icache.overall_misses 94908 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 914028500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 914028500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 914028500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 13877051 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 13877051 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 13877051 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.006839 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.006839 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.006839 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 9630.679184 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 9630.679184 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 9630.679184 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -343,161 +343,161 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 4484 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 4484 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 4484 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 90348 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 90348 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 90348 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 4481 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 4481 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 4481 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 90427 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 90427 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 90427 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 542867000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 542867000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 542867000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 542589500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 542589500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 542589500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006504 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.006504 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.006504 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6008.622216 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6008.622216 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6008.622216 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.006516 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.006516 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.006516 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 6000.304113 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 6000.304113 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 6000.304113 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201353 # number of replacements -system.cpu.dcache.tagsinuse 4076.179768 # Cycle average of tags in use -system.cpu.dcache.total_refs 34205173 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205449 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 166.489849 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 157412000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4076.179768 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995161 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 20626522 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 13578601 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 50 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 34205123 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 34205123 # number of overall hits -system.cpu.dcache.ReadReq_misses 256524 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1034776 # number of WriteReq misses -system.cpu.dcache.demand_misses 1291300 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1291300 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 8257183000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 33901746500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 42158929500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 42158929500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 20883046 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 201340 # number of replacements +system.cpu.dcache.tagsinuse 4076.154176 # Cycle average of tags in use +system.cpu.dcache.total_refs 34207250 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205436 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 166.510495 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 157430000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4076.154176 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995155 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 20628725 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 13578476 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 49 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 34207201 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 34207201 # number of overall hits +system.cpu.dcache.ReadReq_misses 257071 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1034901 # number of WriteReq misses +system.cpu.dcache.demand_misses 1291972 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1291972 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 8273144500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 33900181500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 42173326000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 42173326000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 20885796 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 50 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 35496423 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 35496423 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.012284 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.070810 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.036378 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.036378 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 32188.734777 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 32762.401235 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 32648.439170 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 32648.439170 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 65000 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses 49 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 35499173 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 35499173 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.012308 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.070819 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.036394 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.036394 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 32182.332896 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 32756.931822 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 32642.600614 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 32642.600614 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 53500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 22 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2954.545455 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2675 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 161616 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 194474 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 891377 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1085851 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1085851 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 62050 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 143399 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 205449 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 205449 # number of overall MSHR misses +system.cpu.dcache.writebacks 161613 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 195029 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 891507 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1086536 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1086536 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 62042 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 143394 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 205436 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 205436 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1277837500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 4733841000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 6011678500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 6011678500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1278233000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4733826000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 6012059000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 6012059000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002971 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.005788 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.005788 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20593.674456 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 33011.673722 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 29261.171872 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 29261.171872 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.005787 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.005787 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20602.704619 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 33012.720197 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 29264.875679 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 29264.875679 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 149117 # number of replacements -system.cpu.l2cache.tagsinuse 18922.306950 # Cycle average of tags in use -system.cpu.l2cache.total_refs 136795 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 174479 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.784020 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 149119 # number of replacements +system.cpu.l2cache.tagsinuse 18923.797261 # Cycle average of tags in use +system.cpu.l2cache.total_refs 136861 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 174485 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.784371 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3199.290629 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15723.016321 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.097635 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.479828 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 108324 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 161616 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 12021 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 120345 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 120345 # number of overall hits -system.cpu.l2cache.ReadReq_misses 44045 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 131407 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 175452 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 175452 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1515912500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 4525567500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 6041480000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 6041480000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 152369 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 161616 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 143428 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 295797 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 295797 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.289068 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.916188 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.593150 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.593150 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34417.357248 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34439.318301 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34433.805257 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34433.805257 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 1000 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::0 3200.297768 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15723.499493 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.097665 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.479843 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 108391 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 161613 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 12014 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 120405 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 120405 # number of overall hits +system.cpu.l2cache.ReadReq_misses 44050 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 131408 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 175458 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 175458 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1516062500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 4525488500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 6041551000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 6041551000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 152441 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 161613 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 143422 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 295863 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 295863 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.288964 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.916233 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.593038 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.593038 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34416.855846 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34438.455041 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34433.032407 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34433.032407 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks 120521 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 44045 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 131407 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 175452 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 175452 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 44050 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 131408 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 175458 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 175458 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1367450000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4118334500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 5485784500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 5485784500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1367587500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4118168500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 5485756000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 5485756000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.289068 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.916188 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.593150 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.593150 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31046.656828 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31340.297701 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31266.582883 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31266.582883 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.288964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.916233 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.593038 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.593038 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31046.254257 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31338.795964 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31265.351252 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31265.351252 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini index 39371a1d2..3a0a5fb16 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout index 207188f08..c1184a1d5 100755 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout @@ -3,11 +3,11 @@ Redirecting stderr to build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 19:27:45 -gem5 started Aug 17 2011 21:03:42 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 12:27:58 +gem5 started Aug 20 2011 12:28:18 +gem5 executing on zizzer command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 31377609500 because target called exit() +Exiting @ tick 31207726500 because target called exit() diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt index 67af91500..665110dd2 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.031378 # Number of seconds simulated -sim_ticks 31377609500 # Number of ticks simulated +sim_seconds 0.031208 # Number of seconds simulated +sim_ticks 31207726500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 86505 # Simulator instruction rate (inst/s) -host_tick_rate 26972311 # Simulator tick rate (ticks/s) -host_mem_usage 272452 # Number of bytes of host memory used -host_seconds 1163.33 # Real time elapsed on the host -sim_insts 100633440 # Number of instructions simulated +host_inst_rate 157603 # Simulator instruction rate (inst/s) +host_tick_rate 48874778 # Simulator tick rate (ticks/s) +host_mem_usage 225884 # Number of bytes of host memory used +host_seconds 638.52 # Real time elapsed on the host +sim_insts 100633520 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,300 +51,300 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 62755220 # number of cpu cycles simulated +system.cpu.numCycles 62415454 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 17750529 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11606544 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 829921 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15137991 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 9794974 # Number of BTB hits +system.cpu.BPredUnit.lookups 17712573 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11586024 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 828480 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15104552 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 9800008 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1897089 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 178911 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 13034693 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 89118710 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17750529 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11692063 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 23121914 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2980918 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 23222293 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1054 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 12266935 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 235956 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 61445707 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.021826 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.078498 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1894610 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 179140 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 13000723 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 88894307 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17712573 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11694618 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 23068870 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2942261 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 22994151 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1125 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 12237155 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 232722 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 61101347 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.028542 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.080485 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 38339721 62.40% 62.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2446048 3.98% 66.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2617640 4.26% 70.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2484251 4.04% 74.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1726192 2.81% 77.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1710249 2.78% 80.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1014832 1.65% 81.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1300729 2.12% 84.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9806045 15.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 38048418 62.27% 62.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2437383 3.99% 66.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2590379 4.24% 70.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2495519 4.08% 74.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1726071 2.82% 77.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1712649 2.80% 80.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1014415 1.66% 81.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1324144 2.17% 84.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9752369 15.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 61445707 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.282853 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.420100 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14959115 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 21951327 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 21472779 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1093721 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1968765 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3488107 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 98503 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 121008055 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 332806 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1968765 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16904329 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2023707 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15518382 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20592468 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4438056 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 117725717 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3874 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3096804 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 422 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 119617057 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 541668803 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 541574389 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 94414 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99143173 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20473879 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 769482 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 769728 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12274515 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29853222 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22441342 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2796873 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3745515 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 112284917 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 766220 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107896322 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 310095 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12199571 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 30868237 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 65279 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 61445707 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.755962 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.898029 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 61101347 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.283785 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.424236 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14911699 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 21729904 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 21442913 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1077075 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1939756 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3477546 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 98242 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 120762342 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 332405 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1939756 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16842041 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2003570 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15407287 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20561842 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4346851 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 117493872 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3565 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3003461 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 318 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 119392349 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 540581981 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 540487699 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 94282 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99143301 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 20249043 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 768563 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 768716 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12082768 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29799998 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22399772 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2425661 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3419073 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 112105098 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 764637 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107812126 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 316132 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12020521 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 30346065 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 63680 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 61101347 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.764480 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.904021 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 22301465 36.29% 36.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11812133 19.22% 55.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8597395 13.99% 69.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7417461 12.07% 81.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4807172 7.82% 89.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3508678 5.71% 95.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1667450 2.71% 97.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 811386 1.32% 99.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 522567 0.85% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 22159484 36.27% 36.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11621982 19.02% 55.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8561362 14.01% 69.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7410232 12.13% 81.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4801172 7.86% 89.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3527397 5.77% 95.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1679086 2.75% 97.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 804521 1.32% 99.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 536111 0.88% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 61445707 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 61101347 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 87227 3.33% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1494399 56.99% 60.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1040416 39.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 88099 3.31% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1498283 56.35% 59.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1072737 40.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57176503 52.99% 52.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 87495 0.08% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 4 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29053069 26.93% 80.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21579219 20.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57136904 53.00% 53.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 87447 0.08% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 4 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.08% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29022906 26.92% 80.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21564833 20.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107896322 # Type of FU issued -system.cpu.iq.rate 1.719320 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2622042 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024301 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 280170245 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 125277700 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105616251 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 243 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 246 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 88 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 110518239 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 125 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1858517 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107812126 # Type of FU issued +system.cpu.iq.rate 1.727331 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2659119 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024664 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 279700662 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 124905792 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105547410 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 188 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 166 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 110471148 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1884692 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2544801 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4085 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28033 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1884293 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2491561 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3411 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 16339 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1842707 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 50 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 54 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 62 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1968765 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 949271 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 28405 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 113127739 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 631806 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29853222 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22441342 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 749089 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 969 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1264 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28033 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 689722 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 200512 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 890234 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106504319 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28672397 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1392003 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1939756 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 952120 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 28627 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 112946418 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 627319 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29799998 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22399772 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 747490 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1210 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1207 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 16339 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 688631 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 200572 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 889203 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106427513 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28649084 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1384613 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 76602 # number of nop insts executed -system.cpu.iew.exec_refs 49938031 # number of memory reference insts executed -system.cpu.iew.exec_branches 14639990 # Number of branches executed -system.cpu.iew.exec_stores 21265634 # Number of stores executed -system.cpu.iew.exec_rate 1.697139 # Inst execution rate -system.cpu.iew.wb_sent 105945343 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105616339 # cumulative count of insts written-back -system.cpu.iew.wb_producers 52584494 # num instructions producing a value -system.cpu.iew.wb_consumers 101353649 # num instructions consuming a value +system.cpu.iew.exec_nop 76683 # number of nop insts executed +system.cpu.iew.exec_refs 49896710 # number of memory reference insts executed +system.cpu.iew.exec_branches 14628801 # Number of branches executed +system.cpu.iew.exec_stores 21247626 # Number of stores executed +system.cpu.iew.exec_rate 1.705147 # Inst execution rate +system.cpu.iew.wb_sent 105874797 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105547479 # cumulative count of insts written-back +system.cpu.iew.wb_producers 52578934 # num instructions producing a value +system.cpu.iew.wb_consumers 101387160 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.682989 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.518822 # average fanout of values written-back +system.cpu.iew.wb_rate 1.691047 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.518596 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 100638992 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 12404270 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 700941 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 795177 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 59476943 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.692067 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.421797 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 100639072 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 12225024 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 700957 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 794036 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 59161592 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.701088 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.430633 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 26426974 44.43% 44.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14734590 24.77% 69.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4278530 7.19% 76.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3643335 6.13% 82.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2295146 3.86% 86.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1888116 3.17% 89.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 696870 1.17% 90.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 492103 0.83% 91.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5021279 8.44% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 26262806 44.39% 44.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14615219 24.70% 69.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4224786 7.14% 76.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3635680 6.15% 82.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2285256 3.86% 86.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1889118 3.19% 89.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 706435 1.19% 90.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 496319 0.84% 91.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5045973 8.53% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 59476943 # Number of insts commited each cycle -system.cpu.commit.count 100638992 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 59161592 # Number of insts commited each cycle +system.cpu.commit.count 100639072 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47865469 # Number of memory references committed -system.cpu.commit.loads 27308420 # Number of loads committed +system.cpu.commit.refs 47865501 # Number of memory references committed +system.cpu.commit.loads 27308436 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13669939 # Number of branches committed +system.cpu.commit.branches 13669955 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91478031 # Number of committed integer instructions. +system.cpu.commit.int_insts 91478095 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5021279 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5045973 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 167473627 # The number of ROB reads -system.cpu.rob.rob_writes 228061528 # The number of ROB writes -system.cpu.timesIdled 61721 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1309513 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 100633440 # Number of Instructions Simulated -system.cpu.committedInsts_total 100633440 # Number of Instructions Simulated -system.cpu.cpi 0.623602 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.623602 # CPI: Total CPI of All Threads -system.cpu.ipc 1.603587 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.603587 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 512681755 # number of integer regfile reads -system.cpu.int_regfile_writes 104103098 # number of integer regfile writes -system.cpu.fp_regfile_reads 154 # number of floating regfile reads -system.cpu.fp_regfile_writes 120 # number of floating regfile writes -system.cpu.misc_regfile_reads 146929222 # number of misc regfile reads -system.cpu.misc_regfile_writes 34462 # number of misc regfile writes -system.cpu.icache.replacements 26055 # number of replacements -system.cpu.icache.tagsinuse 1807.169356 # Cycle average of tags in use -system.cpu.icache.total_refs 12237713 # Total number of references to valid blocks. +system.cpu.rob.rob_reads 166954416 # The number of ROB reads +system.cpu.rob.rob_writes 227673782 # The number of ROB writes +system.cpu.timesIdled 61616 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1314107 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 100633520 # Number of Instructions Simulated +system.cpu.committedInsts_total 100633520 # Number of Instructions Simulated +system.cpu.cpi 0.620225 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.620225 # CPI: Total CPI of All Threads +system.cpu.ipc 1.612317 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.612317 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 512325342 # number of integer regfile reads +system.cpu.int_regfile_writes 104042616 # number of integer regfile writes +system.cpu.fp_regfile_reads 124 # number of floating regfile reads +system.cpu.fp_regfile_writes 92 # number of floating regfile writes +system.cpu.misc_regfile_reads 146636710 # number of misc regfile reads +system.cpu.misc_regfile_writes 34494 # number of misc regfile writes +system.cpu.icache.replacements 26059 # number of replacements +system.cpu.icache.tagsinuse 1807.414724 # Cycle average of tags in use +system.cpu.icache.total_refs 12207911 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 28088 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 435.691861 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 434.630839 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1807.169356 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.882407 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 12237715 # number of ReadReq hits -system.cpu.icache.demand_hits 12237715 # number of demand (read+write) hits -system.cpu.icache.overall_hits 12237715 # number of overall hits -system.cpu.icache.ReadReq_misses 29220 # number of ReadReq misses -system.cpu.icache.demand_misses 29220 # number of demand (read+write) misses -system.cpu.icache.overall_misses 29220 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 359586000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 359586000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 359586000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 12266935 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 12266935 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 12266935 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.002382 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.002382 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.002382 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 12306.160164 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 12306.160164 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 12306.160164 # average overall miss latency +system.cpu.icache.occ_blocks::0 1807.414724 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.882527 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 12207928 # number of ReadReq hits +system.cpu.icache.demand_hits 12207928 # number of demand (read+write) hits +system.cpu.icache.overall_hits 12207928 # number of overall hits +system.cpu.icache.ReadReq_misses 29227 # number of ReadReq misses +system.cpu.icache.demand_misses 29227 # number of demand (read+write) misses +system.cpu.icache.overall_misses 29227 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 359488500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 359488500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 359488500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 12237155 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 12237155 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 12237155 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.002388 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.002388 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.002388 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 12299.876826 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 12299.876826 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 12299.876826 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,146 +353,144 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1104 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1104 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1104 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 28116 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 28116 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 28116 # number of overall MSHR misses +system.cpu.icache.writebacks 1 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 1106 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1106 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1106 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 28121 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 28121 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 28121 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 247135000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 247135000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 247135000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 247525500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 247525500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 247525500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.002292 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.002292 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.002292 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 8789.834969 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 8789.834969 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 8789.834969 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.002298 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.002298 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.002298 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 8802.158529 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 8802.158529 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 8802.158529 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 157895 # number of replacements -system.cpu.dcache.tagsinuse 4072.454592 # Cycle average of tags in use -system.cpu.dcache.total_refs 44804358 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 161991 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 276.585477 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 307509000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4072.454592 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.994252 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 26458104 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 18310282 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 18655 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 17230 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 44768386 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 44768386 # number of overall hits -system.cpu.dcache.ReadReq_misses 108049 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1539619 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 28 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1647668 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1647668 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2398708000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 52285313500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 392000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 54684021500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 54684021500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 26566153 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 157957 # number of replacements +system.cpu.dcache.tagsinuse 4072.327719 # Cycle average of tags in use +system.cpu.dcache.total_refs 44754174 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162053 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 276.169981 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 306664000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4072.327719 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.994221 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 26407726 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 18310440 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 18642 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 17246 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 44718166 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 44718166 # number of overall hits +system.cpu.dcache.ReadReq_misses 109117 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1539461 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 29 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 1648578 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1648578 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 2423500000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 52284424500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 398000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 54707924500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 54707924500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 26516843 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 18683 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 17230 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 46416054 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 46416054 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.004067 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.077563 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.001499 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.035498 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.035498 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 22200.186952 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33959.904041 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 14000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33188.737962 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33188.737962 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses 18671 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 17246 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 46366744 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 46366744 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.004115 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.077555 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.001553 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.035555 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.035555 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 22210.104750 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33962.811984 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 13724.137931 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 33184.917244 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33184.917244 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 196000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 190500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19600 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19050 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 123449 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 52916 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1432732 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 28 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1485648 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1485648 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 55133 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 106887 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 162020 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 162020 # number of overall MSHR misses +system.cpu.dcache.writebacks 123460 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 53919 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1432572 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 29 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1486491 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1486491 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 55198 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 106889 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 162087 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 162087 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1036639500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3662530000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4699169500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4699169500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1037796500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3662032500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4699829000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4699829000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002075 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002082 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.005385 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.003491 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.003491 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18802.522990 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34265.439202 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 29003.638440 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 29003.638440 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.003496 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.003496 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18801.342440 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34260.143700 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 28995.718349 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 28995.718349 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 114951 # number of replacements -system.cpu.l2cache.tagsinuse 18297.678495 # Cycle average of tags in use -system.cpu.l2cache.total_refs 72351 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 133808 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.540708 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 114992 # number of replacements +system.cpu.l2cache.tagsinuse 18307.930672 # Cycle average of tags in use +system.cpu.l2cache.total_refs 72391 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 133845 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.540857 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2366.019129 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15931.659366 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.072205 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.486196 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 50475 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 123449 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 9 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 4296 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 54771 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 54771 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32704 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 102598 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 135302 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 135302 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1119458500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency 34000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3525951000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4645409500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4645409500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 83179 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 123449 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 106894 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 190073 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 190073 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.393176 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.678571 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.959811 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.711842 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.711842 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34230.017735 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency 1789.473684 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34366.664068 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34333.635127 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34333.635127 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 2377.365392 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15930.565280 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.072551 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.486162 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 50505 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 123461 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 12 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 4300 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 54805 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 54805 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32740 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 21 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 102589 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 135329 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 135329 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1120810000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3525271500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 4646081500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 4646081500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 83245 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 123461 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 33 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 106889 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 190134 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 190134 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.393297 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.636364 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.959771 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.711756 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.711756 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34233.659133 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34363.055493 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34331.750770 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34331.750770 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -501,32 +499,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 88458 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 87 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 87 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 87 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32617 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 102598 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 135215 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 135215 # number of overall MSHR misses +system.cpu.l2cache.writebacks 88460 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 79 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 79 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 79 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 32661 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 21 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 102589 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 135250 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 135250 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1013752000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 589000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3197491000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 4211243000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 4211243000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1015115500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 652000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3196978500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4212094000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4212094000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.392130 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.678571 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959811 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.711385 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.711385 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080.479505 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31165.237139 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31144.791628 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31144.791628 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.392348 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.636364 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959771 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.711340 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.711340 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080.355776 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31047.619048 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31162.975563 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31143.024030 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31143.024030 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index c23f9d7a4..a21027897 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/alpha/tru64/bzip2 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout index f6c6ec79d..a891031f9 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 14:47:20 -gem5 started Aug 17 2011 15:02:03 -gem5 executing on nadc-0388 -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing +gem5 compiled Aug 20 2011 16:10:02 +gem5 started Aug 20 2011 21:33:03 +gem5 executing on zizzer +command line: ./build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -25,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 620013549500 because target called exit() +Exiting @ tick 615292058500 because target called exit() diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index a98b75386..73dcce945 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.620014 # Number of seconds simulated -sim_ticks 620013549500 # Number of ticks simulated +sim_seconds 0.615292 # Number of seconds simulated +sim_ticks 615292058500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119897 # Simulator instruction rate (inst/s) -host_tick_rate 42820054 # Simulator tick rate (ticks/s) -host_mem_usage 252132 # Number of bytes of host memory used -host_seconds 14479.51 # Real time elapsed on the host +host_inst_rate 150883 # Simulator instruction rate (inst/s) +host_tick_rate 53476218 # Simulator tick rate (ticks/s) +host_mem_usage 211804 # Number of bytes of host memory used +host_seconds 11505.90 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 605264801 # DTB read hits -system.cpu.dtb.read_misses 10656374 # DTB read misses +system.cpu.dtb.read_hits 602552271 # DTB read hits +system.cpu.dtb.read_misses 10614048 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 615921175 # DTB read accesses -system.cpu.dtb.write_hits 208028494 # DTB write hits -system.cpu.dtb.write_misses 6799304 # DTB write misses +system.cpu.dtb.read_accesses 613166319 # DTB read accesses +system.cpu.dtb.write_hits 207913538 # DTB write hits +system.cpu.dtb.write_misses 6806894 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 214827798 # DTB write accesses -system.cpu.dtb.data_hits 813293295 # DTB hits -system.cpu.dtb.data_misses 17455678 # DTB misses +system.cpu.dtb.write_accesses 214720432 # DTB write accesses +system.cpu.dtb.data_hits 810465809 # DTB hits +system.cpu.dtb.data_misses 17420942 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 830748973 # DTB accesses -system.cpu.itb.fetch_hits 388376966 # ITB hits +system.cpu.dtb.data_accesses 827886751 # DTB accesses +system.cpu.itb.fetch_hits 385401096 # ITB hits system.cpu.itb.fetch_misses 38 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 388377004 # ITB accesses +system.cpu.itb.fetch_accesses 385401134 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,246 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1240027100 # number of cpu cycles simulated +system.cpu.numCycles 1230584118 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 371321925 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 286983057 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 19433409 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 338368339 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 331826895 # Number of BTB hits +system.cpu.BPredUnit.lookups 368788427 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 284655595 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 19443984 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 335810201 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 329206676 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 24336199 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1812 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 400687979 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3119280790 # Number of instructions fetch has processed -system.cpu.fetch.Branches 371321925 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 356163094 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 611390068 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 134440863 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 114604724 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 24336435 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1745 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 397544739 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3103801885 # Number of instructions fetch has processed +system.cpu.fetch.Branches 368788427 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 353543111 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 607804339 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 131920976 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 113986099 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 951 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 388376966 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 9643914 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1234576300 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.526600 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.016057 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 385401096 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 9585477 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1225061020 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.533590 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.019465 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 623186232 50.48% 50.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 52867156 4.28% 54.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 35732021 2.89% 57.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 53999250 4.37% 62.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 136250417 11.04% 73.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 74701815 6.05% 79.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 52334630 4.24% 83.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 43604913 3.53% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 161899866 13.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 617256681 50.39% 50.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 52795543 4.31% 54.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 34983733 2.86% 57.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 53721044 4.39% 61.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 135046011 11.02% 72.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 74719502 6.10% 79.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 51323378 4.19% 83.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 43567102 3.56% 86.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 161648026 13.20% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1234576300 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.299447 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.515494 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 429010583 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 102446210 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 582198456 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13029284 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 107891767 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 57297832 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 881 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3038448049 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1952 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 107891767 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 451268352 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 59486920 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3651 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 571427779 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 44497831 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2952461199 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 509967 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3056593 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 38427215 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2208688695 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3815339116 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3814332639 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1006477 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1225061020 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.299686 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.522218 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 426009855 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 101612047 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 578250802 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13464213 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 105724103 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 57118243 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 889 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3023280149 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1933 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 105724103 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 448226724 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 58166398 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3444 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 568166155 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 44774196 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2937967281 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 510732 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1525332 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 40266143 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2197783940 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3797275773 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3796267426 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1008347 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 832485732 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 193 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 190 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 93322285 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 667580197 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 249072955 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 55659961 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 31733911 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2660179037 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 172 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2468673818 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1992617 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 912469366 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 383003969 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 143 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1234576300 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.999612 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.936572 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 821580977 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 180 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 178 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 93606956 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 663953354 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 248514283 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 54484359 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 31450059 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2647456890 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 154 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2459087861 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1981205 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 899874302 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 377613541 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1225061020 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.007319 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.938295 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 394722049 31.97% 31.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 200520183 16.24% 48.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 195096973 15.80% 64.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 152865023 12.38% 76.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 138702547 11.23% 87.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 76304962 6.18% 93.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 56923142 4.61% 98.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14040598 1.14% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5400823 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 390052689 31.84% 31.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 197664545 16.14% 47.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 194534552 15.88% 63.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 152397104 12.44% 76.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 138172730 11.28% 87.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 75830053 6.19% 93.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 56958095 4.65% 98.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14036871 1.15% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5414381 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1234576300 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1225061020 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1834419 11.27% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11081610 68.08% 79.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3361740 20.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1870870 11.50% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11042349 67.89% 79.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3352440 20.61% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1613757187 65.37% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 92 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 253 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 20 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 155 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 634184534 25.69% 91.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 220731537 8.94% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1607157901 65.36% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 88 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 251 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 20 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 149 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 19 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 631365239 25.67% 91.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 220564170 8.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2468673818 # Type of FU issued -system.cpu.iq.rate 1.990822 # Inst issue rate -system.cpu.iq.fu_busy_cnt 16277769 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006594 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6188434736 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3572169427 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2366146276 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1759586 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1005347 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 824789 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2484075446 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 876141 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54414516 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2459087861 # Type of FU issued +system.cpu.iq.rate 1.998309 # Inst issue rate +system.cpu.iq.fu_busy_cnt 16265659 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006615 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6159722029 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3546409355 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2357254024 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1761577 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1006663 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 825129 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2474476437 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 877083 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 54564037 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 222984534 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 276039 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 531067 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 88344453 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 219357691 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 276764 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 87944 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 87785781 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 70 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 162806 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 71 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 162830 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 107891767 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22183001 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1020429 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2801921331 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 12930096 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 667580197 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 249072955 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 172 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 231741 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17901 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 531067 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 20319343 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2050255 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 22369598 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2414335785 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 615921372 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 54338033 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 105724103 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22305472 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1113476 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2788688851 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 12944530 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 663953354 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 248514283 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 154 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 231462 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18115 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 87944 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 20335960 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2039327 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 22375287 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2405013673 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 613166540 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 54074188 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 141742122 # number of nop insts executed -system.cpu.iew.exec_refs 830749189 # number of memory reference insts executed -system.cpu.iew.exec_branches 295817735 # Number of branches executed -system.cpu.iew.exec_stores 214827817 # Number of stores executed -system.cpu.iew.exec_rate 1.947002 # Inst execution rate -system.cpu.iew.wb_sent 2393878434 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2366971065 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1353323878 # num instructions producing a value -system.cpu.iew.wb_consumers 1710357727 # num instructions consuming a value +system.cpu.iew.exec_nop 141231807 # number of nop insts executed +system.cpu.iew.exec_refs 827886992 # number of memory reference insts executed +system.cpu.iew.exec_branches 294323253 # Number of branches executed +system.cpu.iew.exec_stores 214720452 # Number of stores executed +system.cpu.iew.exec_rate 1.954368 # Inst execution rate +system.cpu.iew.wb_sent 2384887539 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2358079153 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1347433304 # num instructions producing a value +system.cpu.iew.wb_consumers 1703552370 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.908806 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.791252 # average fanout of values written-back +system.cpu.iew.wb_rate 1.916228 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.790955 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 748592924 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 736139047 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 19432624 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1126684533 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.615164 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.477479 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 19443221 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1119336917 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.625766 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.487685 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 590961452 52.45% 52.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 189557925 16.82% 69.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 95769677 8.50% 77.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53357223 4.74% 82.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 37491988 3.33% 85.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27218230 2.42% 88.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 21816919 1.94% 90.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22438390 1.99% 92.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 88072729 7.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 586822597 52.43% 52.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 186310200 16.64% 69.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 95274520 8.51% 77.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53747896 4.80% 82.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 37177452 3.32% 85.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26985316 2.41% 88.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21737766 1.94% 90.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22635146 2.02% 92.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 88646024 7.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1126684533 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1119336917 # Number of insts commited each cycle system.cpu.commit.count 1819780126 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 605324165 # Number of memory references committed @@ -290,50 +290,50 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 88072729 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 88646024 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3521205654 # The number of ROB reads -system.cpu.rob.rob_writes 5244829032 # The number of ROB writes -system.cpu.timesIdled 389205 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5450800 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3500830866 # The number of ROB reads +system.cpu.rob.rob_writes 5217723058 # The number of ROB writes +system.cpu.timesIdled 398057 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5523098 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.714283 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.714283 # CPI: Total CPI of All Threads -system.cpu.ipc 1.400005 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.400005 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3248506464 # number of integer regfile reads -system.cpu.int_regfile_writes 1894457648 # number of integer regfile writes -system.cpu.fp_regfile_reads 12410 # number of floating regfile reads -system.cpu.fp_regfile_writes 512 # number of floating regfile writes +system.cpu.cpi 0.708844 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.708844 # CPI: Total CPI of All Threads +system.cpu.ipc 1.410748 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.410748 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3237009112 # number of integer regfile reads +system.cpu.int_regfile_writes 1887111006 # number of integer regfile writes +system.cpu.fp_regfile_reads 12550 # number of floating regfile reads +system.cpu.fp_regfile_writes 508 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 749.102661 # Cycle average of tags in use -system.cpu.icache.total_refs 388375634 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 943 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 411851.149523 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 746.155324 # Cycle average of tags in use +system.cpu.icache.total_refs 385399748 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 942 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 409129.244161 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 749.102661 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.365773 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 388375634 # number of ReadReq hits -system.cpu.icache.demand_hits 388375634 # number of demand (read+write) hits -system.cpu.icache.overall_hits 388375634 # number of overall hits -system.cpu.icache.ReadReq_misses 1332 # number of ReadReq misses -system.cpu.icache.demand_misses 1332 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1332 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 46849500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 46849500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 46849500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 388376966 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 388376966 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 388376966 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 746.155324 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.364334 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 385399748 # number of ReadReq hits +system.cpu.icache.demand_hits 385399748 # number of demand (read+write) hits +system.cpu.icache.overall_hits 385399748 # number of overall hits +system.cpu.icache.ReadReq_misses 1348 # number of ReadReq misses +system.cpu.icache.demand_misses 1348 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1348 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 47398000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 47398000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 47398000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 385401096 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 385401096 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 385401096 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35172.297297 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35172.297297 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35172.297297 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 35161.721068 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35161.721068 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35161.721068 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -343,169 +343,169 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 389 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 389 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 389 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 943 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 943 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 943 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 406 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 406 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 406 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 942 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 942 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 942 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 33478000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 33478000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 33478000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 33448000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 33448000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 33448000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35501.590668 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35501.590668 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35501.590668 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35507.430998 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35507.430998 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35507.430998 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9160008 # number of replacements -system.cpu.dcache.tagsinuse 4087.032311 # Cycle average of tags in use -system.cpu.dcache.total_refs 696282176 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9164104 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 75.979297 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5156765000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4087.032311 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997811 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 540448912 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 155833261 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 696282173 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 696282173 # number of overall hits -system.cpu.dcache.ReadReq_misses 10323793 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 4895241 # number of WriteReq misses +system.cpu.dcache.replacements 9159821 # number of replacements +system.cpu.dcache.tagsinuse 4086.961398 # Cycle average of tags in use +system.cpu.dcache.total_refs 693411949 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9163917 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 75.667637 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5157991000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4086.961398 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997793 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 537597174 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 155814773 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 2 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 693411947 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 693411947 # number of overall hits +system.cpu.dcache.ReadReq_misses 10313435 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 4913729 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 15219034 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 15219034 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 172136393500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 136959411379 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 15227164 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 15227164 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 172073260500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 137521396881 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 38500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 309095804879 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 309095804879 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 550772705 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 309594657381 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 309594657381 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 547910609 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 711501207 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 711501207 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.018744 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.030457 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.021390 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.021390 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 16673.754840 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 27978.073271 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 708639111 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 708639111 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.018823 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.030572 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.333333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.021488 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.021488 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 16684.379210 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 27987.175703 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 20309.817619 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 20309.817619 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 119249756 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2148365000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 37808 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65111 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3154.087918 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 32995.423200 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency 20331.734615 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 20331.734615 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 119268264 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2148368000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 37813 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65113 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3154.160315 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 32994.455792 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 3077590 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 3044730 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 3010201 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 6054931 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 6054931 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 7279063 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1885040 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks 3077535 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 3034555 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 3028693 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 6063248 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 6063248 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 7278880 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1885036 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 9164103 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 9164103 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 9163916 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 9163916 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 80943069500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 38634312034 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 81039107500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 38640356536 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 119577381534 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 119577381534 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 119679464036 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 119679464036 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.013216 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.013285 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.011728 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.250000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.012880 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.012880 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11119.984743 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20495.221340 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.012932 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.012932 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11133.458375 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20498.471401 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 13048.454555 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 13048.454555 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13059.860439 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13059.860439 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2693796 # number of replacements -system.cpu.l2cache.tagsinuse 26682.483839 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7633391 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2718433 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.808011 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 127776884500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 15920.049734 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10762.434105 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.485841 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.328443 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5459110 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 3077590 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 1001562 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6460672 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6460672 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1820887 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 883488 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 2704375 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 2704375 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 62517574500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 30445882000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 92963456500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 92963456500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 7279997 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 3077590 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1885050 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 9165047 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 9165047 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.250122 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.468681 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.295075 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.295075 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34333.582754 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34461.002300 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34375.209244 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34375.209244 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 17565000 # number of cycles access was blocked +system.cpu.l2cache.replacements 2693797 # number of replacements +system.cpu.l2cache.tagsinuse 26669.588705 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7633154 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2718439 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.807918 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 126954186500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 15903.024773 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 10766.563932 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.485322 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.328569 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 5458962 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 3077535 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 1001516 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 6460478 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 6460478 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1820852 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 883529 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 2704381 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 2704381 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 62524059000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 30450873000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 92974932000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 92974932000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 7279814 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 3077535 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1885045 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 9164859 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 9164859 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.250123 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.468704 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.295082 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.295082 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34337.803951 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34465.052081 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34379.376279 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34379.376279 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 17570000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 1700 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 1704 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10332.352941 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10311.032864 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 1171832 # number of writebacks +system.cpu.l2cache.writebacks 1171820 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1820887 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 883488 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 2704375 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 2704375 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 1820852 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 883529 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 2704381 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 2704381 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 56727891500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 27629735500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 84357627000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 84357627000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 56737753000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 27632234500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 84369987500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 84369987500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250122 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468681 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.295075 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.295075 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31153.987864 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31273.470041 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31193.021308 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31193.021308 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250123 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468704 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.295082 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.295082 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31160.002570 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31274.847232 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31197.522649 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31197.522649 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini index a651bdb28..93cd8d25f 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout index 83af142ca..bf70270df 100755 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 18 2011 17:30:35 -gem5 started Aug 18 2011 17:40:43 -gem5 executing on nadc-0330 +gem5 compiled Sep 11 2011 21:12:14 +gem5 started Sep 11 2011 22:28:54 +gem5 executing on u200439-lin.austin.arm.com command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -26,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 506532922500 because target called exit() +Exiting @ tick 483520764000 because target called exit() diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 135431d57..24e250396 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.506533 # Number of seconds simulated -sim_ticks 506532922500 # Number of ticks simulated +sim_seconds 0.483521 # Number of seconds simulated +sim_ticks 483520764000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123802 # Simulator instruction rate (inst/s) -host_tick_rate 36394183 # Simulator tick rate (ticks/s) -host_mem_usage 263680 # Number of bytes of host memory used -host_seconds 13917.96 # Real time elapsed on the host +host_inst_rate 88254 # Simulator instruction rate (inst/s) +host_tick_rate 24765480 # Simulator tick rate (ticks/s) +host_mem_usage 263692 # Number of bytes of host memory used +host_seconds 19523.98 # Real time elapsed on the host sim_insts 1723073849 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses @@ -51,247 +51,247 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1013065846 # number of cpu cycles simulated +system.cpu.numCycles 967041529 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 315530681 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 258143608 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18340117 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 278231679 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 251492518 # Number of BTB hits +system.cpu.BPredUnit.lookups 298900449 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 243980938 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 18344304 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 264330532 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 238781777 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 20187042 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 3509 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 313870814 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2260978275 # Number of instructions fetch has processed -system.cpu.fetch.Branches 315530681 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 271679560 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 505214363 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 101212316 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 104532477 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 328 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 301063999 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6471754 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1002877503 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.508485 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.026652 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 17662867 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 3505 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 295983189 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2175588902 # Number of instructions fetch has processed +system.cpu.fetch.Branches 298900449 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 256444644 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 484812336 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 87085918 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 107601139 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 294 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 285066920 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5311321 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 956724152 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.521766 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.026486 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 497663194 49.62% 49.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 37228948 3.71% 53.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 66606984 6.64% 59.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71463437 7.13% 67.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 48876391 4.87% 71.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 60858176 6.07% 78.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 55641741 5.55% 83.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 19086125 1.90% 85.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 145452507 14.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 471911868 49.33% 49.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 35379148 3.70% 53.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 65139184 6.81% 59.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 66872594 6.99% 66.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 46913058 4.90% 71.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 59711536 6.24% 77.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 54259656 5.67% 83.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 17705492 1.85% 85.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 138831616 14.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1002877503 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.311461 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.231818 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 341996878 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 89611613 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 478932686 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13077462 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 79258864 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 48434993 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 667 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2450495134 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2272 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 79258864 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 363548311 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 45530514 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19331 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 469125778 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 45394705 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2388695520 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19323 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2689291 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 36489292 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 11 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2366306887 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 11027767520 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 11027765811 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1709 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 956724152 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.309088 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.249737 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 323003673 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 92138171 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 459624740 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13631035 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 68326533 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46888019 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 679 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2352946295 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2296 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 68326533 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 343140693 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 46558738 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19729 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 451876616 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46801843 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2296129706 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19815 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2700855 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 37763142 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2264720698 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10606897757 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10606896049 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1708 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319951 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 659986931 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 807 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 800 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 96182774 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 645482909 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 225885161 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 74160075 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 61434686 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2258262830 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 791 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2062701357 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3805579 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 528742156 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1247770653 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 334 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1002877503 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.056783 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.854473 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 558400742 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 819 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 812 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 98759000 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 618794544 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 222188124 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 74432694 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 62140550 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2187930244 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 806 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2018487398 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3289652 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 458712680 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1051172668 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 349 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 956724152 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.109790 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.840040 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 290604713 28.98% 28.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 157949600 15.75% 44.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 174074952 17.36% 62.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 138718897 13.83% 75.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 127592193 12.72% 88.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 68569400 6.84% 95.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 32608818 3.25% 98.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10494958 1.05% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2263972 0.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 261965292 27.38% 27.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 150944559 15.78% 43.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 168632678 17.63% 60.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 136410439 14.26% 75.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 125113434 13.08% 88.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73446986 7.68% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 29046356 3.04% 98.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10235900 1.07% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 928508 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1002877503 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 956724152 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2048519 7.53% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 180 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19993289 73.47% 81.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5169269 19.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 898312 3.71% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 170 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18874903 77.94% 81.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4444569 18.35% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1260792748 61.12% 61.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1057290 0.05% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 6 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 606172338 29.39% 90.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 194678965 9.44% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1238989796 61.38% 61.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1018767 0.05% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 11 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 9 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 1 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 583947158 28.93% 90.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 194531653 9.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2062701357 # Type of FU issued -system.cpu.iq.rate 2.036098 # Inst issue rate -system.cpu.iq.fu_busy_cnt 27211257 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013192 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5159296764 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2790611549 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1986898801 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 289 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 310 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 125 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2089912468 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 146 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 50578054 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2018487398 # Type of FU issued +system.cpu.iq.rate 2.087281 # Inst issue rate +system.cpu.iq.fu_busy_cnt 24217954 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011998 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5021206278 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2646821889 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1958327848 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 276 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 115 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2042705213 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 139 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 55649565 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 159556137 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 214192 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 3609503 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 51038115 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 132867772 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 211365 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 180609 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 47341078 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 451763 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 452178 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 79258864 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 21822492 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1097447 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2258327486 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7242198 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 645482909 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 225885161 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 728 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 222856 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 63033 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 3609503 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 18937238 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1831687 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 20768925 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2019710082 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 582582512 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42991275 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 68326533 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22149991 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1213461 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2187949319 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7278781 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 618794544 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 222188124 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 743 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 219838 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 61091 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 180609 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 18951981 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1826621 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 20778602 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1986068567 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 570288882 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 32418831 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 63865 # number of nop insts executed -system.cpu.iew.exec_refs 773812500 # number of memory reference insts executed -system.cpu.iew.exec_branches 240248597 # Number of branches executed -system.cpu.iew.exec_stores 191229988 # Number of stores executed -system.cpu.iew.exec_rate 1.993661 # Inst execution rate -system.cpu.iew.wb_sent 1997612417 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1986898926 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1306276482 # num instructions producing a value -system.cpu.iew.wb_consumers 2072612086 # num instructions consuming a value +system.cpu.iew.exec_nop 18269 # number of nop insts executed +system.cpu.iew.exec_refs 761473758 # number of memory reference insts executed +system.cpu.iew.exec_branches 238644907 # Number of branches executed +system.cpu.iew.exec_stores 191184876 # Number of stores executed +system.cpu.iew.exec_rate 2.053757 # Inst execution rate +system.cpu.iew.wb_sent 1967261719 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1958327963 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1288121662 # num instructions producing a value +system.cpu.iew.wb_consumers 2036910460 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.961273 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.630256 # average fanout of values written-back +system.cpu.iew.wb_rate 2.025071 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.632390 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1723073867 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 535450016 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 464956551 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 457 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 18340062 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 923618640 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.865569 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.641231 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 18344332 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 888397620 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.939530 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.671610 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 417808285 45.24% 45.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 197293052 21.36% 66.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 87052087 9.43% 76.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 38036803 4.12% 80.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 20677754 2.24% 82.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 32036200 3.47% 85.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19042329 2.06% 87.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12956798 1.40% 89.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 98715332 10.69% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 383037346 43.12% 43.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 200906061 22.61% 65.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 81946763 9.22% 74.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 38644775 4.35% 79.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19780530 2.23% 81.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30949131 3.48% 85.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22271905 2.51% 87.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12048122 1.36% 88.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 98812987 11.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 923618640 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 888397620 # Number of insts commited each cycle system.cpu.commit.count 1723073867 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 660773817 # Number of memory references committed @@ -301,50 +301,50 @@ system.cpu.commit.branches 213462365 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941853 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 98715332 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 98812987 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3083426592 # The number of ROB reads -system.cpu.rob.rob_writes 4596573652 # The number of ROB writes -system.cpu.timesIdled 890932 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10188343 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2977614452 # The number of ROB reads +system.cpu.rob.rob_writes 4444617859 # The number of ROB writes +system.cpu.timesIdled 920049 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10317377 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1723073849 # Number of Instructions Simulated system.cpu.committedInsts_total 1723073849 # Number of Instructions Simulated -system.cpu.cpi 0.587941 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.587941 # CPI: Total CPI of All Threads -system.cpu.ipc 1.700851 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.700851 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10108398592 # number of integer regfile reads -system.cpu.int_regfile_writes 1972581504 # number of integer regfile writes -system.cpu.fp_regfile_reads 113 # number of floating regfile reads -system.cpu.fp_regfile_writes 31 # number of floating regfile writes -system.cpu.misc_regfile_reads 3008512623 # number of misc regfile reads +system.cpu.cpi 0.561230 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.561230 # CPI: Total CPI of All Threads +system.cpu.ipc 1.781799 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.781799 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9941893014 # number of integer regfile reads +system.cpu.int_regfile_writes 1939859629 # number of integer regfile writes +system.cpu.fp_regfile_reads 106 # number of floating regfile reads +system.cpu.fp_regfile_writes 43 # number of floating regfile writes +system.cpu.misc_regfile_reads 2914173755 # number of misc regfile reads system.cpu.misc_regfile_writes 126 # number of misc regfile writes -system.cpu.icache.replacements 11 # number of replacements -system.cpu.icache.tagsinuse 611.156574 # Cycle average of tags in use -system.cpu.icache.total_refs 301062972 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 745 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 404111.371812 # Average number of references to valid blocks. +system.cpu.icache.replacements 10 # number of replacements +system.cpu.icache.tagsinuse 611.960208 # Cycle average of tags in use +system.cpu.icache.total_refs 285065889 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 746 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 382125.856568 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 611.156574 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.298416 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 301062972 # number of ReadReq hits -system.cpu.icache.demand_hits 301062972 # number of demand (read+write) hits -system.cpu.icache.overall_hits 301062972 # number of overall hits -system.cpu.icache.ReadReq_misses 1027 # number of ReadReq misses -system.cpu.icache.demand_misses 1027 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1027 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 35502000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 35502000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 35502000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 301063999 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 301063999 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 301063999 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34568.646543 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34568.646543 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34568.646543 # average overall miss latency +system.cpu.icache.occ_blocks::0 611.960208 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.298809 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 285065889 # number of ReadReq hits +system.cpu.icache.demand_hits 285065889 # number of demand (read+write) hits +system.cpu.icache.overall_hits 285065889 # number of overall hits +system.cpu.icache.ReadReq_misses 1031 # number of ReadReq misses +system.cpu.icache.demand_misses 1031 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1031 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 35526500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 35526500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 35526500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 285066920 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 285066920 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 285066920 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 34458.292919 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34458.292919 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34458.292919 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,169 +354,169 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 282 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 282 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 282 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 745 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 745 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 745 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 285 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 285 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 285 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 746 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 746 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 746 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 25601000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 25601000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 25601000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 25635000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 25635000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 25635000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34363.758389 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34363.758389 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34363.758389 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34363.270777 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34363.270777 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34363.270777 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9572249 # number of replacements -system.cpu.dcache.tagsinuse 4087.950948 # Cycle average of tags in use -system.cpu.dcache.total_refs 684182956 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9576345 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 71.445103 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3569933000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4087.950948 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.998035 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 516770094 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 167412740 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 60 # number of LoadLockedReq hits +system.cpu.dcache.replacements 9570715 # number of replacements +system.cpu.dcache.tagsinuse 4087.762174 # Cycle average of tags in use +system.cpu.dcache.total_refs 666971462 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9574811 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 69.658969 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3484394000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4087.762174 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997989 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 499575855 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 167395484 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits 62 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 684182834 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 684182834 # number of overall hits -system.cpu.dcache.ReadReq_misses 10495679 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 5173307 # number of WriteReq misses +system.cpu.dcache.demand_hits 666971339 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 666971339 # number of overall hits +system.cpu.dcache.ReadReq_misses 10446749 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 5190563 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 15668986 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 15668986 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 184475737500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 128174581168 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 15637312 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 15637312 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 184495426500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 128540257604 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 113500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 312650318668 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 312650318668 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 527265773 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 313035684104 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 313035684104 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 510022604 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 63 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses 64 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses 62 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 699851820 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 699851820 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.019906 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.029975 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.047619 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.022389 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.022389 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 17576.350944 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 24776.140517 # average WriteReq miss latency +system.cpu.dcache.demand_accesses 682608651 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 682608651 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.020483 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.030075 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.046875 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.022908 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.022908 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 17660.558945 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 24764.222610 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 19953.449360 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 19953.449360 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 267517156 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 206500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 91155 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency 20018.509837 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 20018.509837 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 267225153 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 199000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 90802 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2934.750217 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 17208.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2942.943470 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 16583.333333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 3128719 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 2812049 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 3280592 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 3128462 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 2764582 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 3297919 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 6092641 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 6092641 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 7683630 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1892715 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 9576345 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 9576345 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 6062501 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 6062501 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 7682167 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1892644 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 9574811 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 9574811 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 91948284500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 45274333885 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 137222618385 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 137222618385 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 92043723000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 45263737820 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 137307460820 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 137307460820 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.014573 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010967 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.013683 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.013683 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11966.776706 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23920.312295 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 14329.331116 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 14329.331116 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.015062 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.010966 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.014027 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.014027 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11981.479054 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23915.611082 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 14340.487851 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 14340.487851 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2927741 # number of replacements -system.cpu.l2cache.tagsinuse 26823.943722 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7852858 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2955065 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.657423 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 103629166500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 16019.902231 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10804.041491 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.488889 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.329713 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5656678 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 3128719 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 980284 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6636962 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6636962 # number of overall hits -system.cpu.l2cache.ReadReq_misses 2027695 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 912433 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 2940128 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 2940128 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 69610117500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 31648090500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 101258208000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 101258208000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 7684373 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 3128719 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1892717 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 9577090 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 9577090 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.263873 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.482076 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.306996 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.306996 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34329.678527 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34685.385667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34440.067915 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34440.067915 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 56477000 # number of cycles access was blocked +system.cpu.l2cache.replacements 2927649 # number of replacements +system.cpu.l2cache.tagsinuse 26780.067409 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7851232 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2954973 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.656956 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 102089125500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 15983.054222 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 10797.013187 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.487764 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.329499 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 5655215 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 3128462 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 980262 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 6635477 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 6635477 # number of overall hits +system.cpu.l2cache.ReadReq_misses 2027697 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 912383 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 2940080 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 2940080 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 69611953000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 31645995500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 101257948500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 101257948500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 7682912 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 3128462 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1892645 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 9575557 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 9575557 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.263923 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.482068 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.307040 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.307040 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34330.549880 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34684.990295 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34440.541924 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34440.541924 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 56517000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 6600 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 6610 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8557.121212 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8550.226929 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 1217526 # number of writebacks +system.cpu.l2cache.writebacks 1217515 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 2027684 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 912433 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 2940117 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 2940117 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 2027686 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 912383 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 2940069 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 2940069 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 63223600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 28815061500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 92038661500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 92038661500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 63233834500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 28812323000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 92046157500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 92046157500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263871 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482076 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.306995 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.306995 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31180.203621 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31580.468374 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31304.421389 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31304.421389 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263922 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482068 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.307039 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.307039 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31185.220246 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31579.197552 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31307.482069 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31307.482069 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index cbca14c5b..249041a4d 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/alpha/tru64/twolf +executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index 43a475337..2583cc940 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -3,10 +3,12 @@ Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 14:47:20 -gem5 started Aug 17 2011 14:49:49 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 16:10:02 +gem5 started Aug 20 2011 16:10:09 +gem5 executing on zizzer command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +25,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 30278595500 because target called exit() +122 123 124 Exiting @ tick 29167093500 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 08d328376..f77f26233 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.030279 # Number of seconds simulated -sim_ticks 30278595500 # Number of ticks simulated +sim_seconds 0.029167 # Number of seconds simulated +sim_ticks 29167093500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116969 # Simulator instruction rate (inst/s) -host_tick_rate 42072708 # Simulator tick rate (ticks/s) -host_mem_usage 256296 # Number of bytes of host memory used -host_seconds 719.67 # Real time elapsed on the host +host_inst_rate 127298 # Simulator instruction rate (inst/s) +host_tick_rate 44106983 # Simulator tick rate (ticks/s) +host_mem_usage 209296 # Number of bytes of host memory used +host_seconds 661.28 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 25688278 # DTB read hits -system.cpu.dtb.read_misses 550762 # DTB read misses +system.cpu.dtb.read_hits 25236325 # DTB read hits +system.cpu.dtb.read_misses 540509 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 26239040 # DTB read accesses -system.cpu.dtb.write_hits 7360758 # DTB write hits -system.cpu.dtb.write_misses 1044 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 7361802 # DTB write accesses -system.cpu.dtb.data_hits 33049036 # DTB hits -system.cpu.dtb.data_misses 551806 # DTB misses -system.cpu.dtb.data_acv 4 # DTB access violations -system.cpu.dtb.data_accesses 33600842 # DTB accesses -system.cpu.itb.fetch_hits 19370237 # ITB hits -system.cpu.itb.fetch_misses 82 # ITB misses +system.cpu.dtb.read_accesses 25776834 # DTB read accesses +system.cpu.dtb.write_hits 7362909 # DTB write hits +system.cpu.dtb.write_misses 1032 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 7363941 # DTB write accesses +system.cpu.dtb.data_hits 32599234 # DTB hits +system.cpu.dtb.data_misses 541541 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 33140775 # DTB accesses +system.cpu.itb.fetch_hits 18604047 # ITB hits +system.cpu.itb.fetch_misses 85 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 19370319 # ITB accesses +system.cpu.itb.fetch_accesses 18604132 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,246 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 60557192 # number of cpu cycles simulated +system.cpu.numCycles 58334188 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 18972162 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 14043194 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1908534 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15684343 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 12020738 # Number of BTB hits +system.cpu.BPredUnit.lookups 18443606 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 13550904 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1909309 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15151906 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 11744171 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1817403 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2435 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 20660360 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 162109118 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18972162 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13838141 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 29871214 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8831306 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3272537 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1817 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 19370237 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 684277 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 60463700 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.681098 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.259568 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1797123 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2508 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 19753130 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 155901269 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18443606 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13541294 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 28873870 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8029527 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3519156 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1819 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 18604047 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 633220 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 58241050 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.676828 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.252315 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 30592486 50.60% 50.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2950542 4.88% 55.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2105012 3.48% 58.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3386904 5.60% 64.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4238557 7.01% 71.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1492876 2.47% 74.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1782148 2.95% 76.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1645056 2.72% 79.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 12270119 20.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29367180 50.42% 50.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2937608 5.04% 55.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2015194 3.46% 58.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3338566 5.73% 64.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4094138 7.03% 71.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1423310 2.44% 74.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1755062 3.01% 77.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1585835 2.72% 79.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11724157 20.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 60463700 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.313293 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.676959 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 22547787 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2537266 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 28115662 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 618580 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6644405 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2987075 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13654 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 155918946 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42842 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6644405 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24245198 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 523469 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6031 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 27028766 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2015831 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 148832808 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 266593 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1498062 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 109279851 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 192445710 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 181748286 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10697424 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 58241050 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.316171 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.672554 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 21649179 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2708949 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 27144653 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 658698 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6079571 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2969190 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13806 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 150046107 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 43597 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6079571 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 23241789 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 566661 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6095 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 26202396 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2144538 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 144061667 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 244284 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1605069 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 105522995 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 186327738 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 175726328 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10601410 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 40852490 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 518 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 515 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 6036784 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 30729381 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9521294 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2640558 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 881343 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 123679327 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 494 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105899114 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 512588 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 38384232 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 30395152 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 105 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 60463700 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.751449 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.825920 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 37095634 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 535 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 531 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 6071657 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29750182 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9383371 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2457988 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 836885 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 120824169 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 510 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 104934850 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 288533 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 35688110 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 27652526 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 121 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 58241050 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.801733 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.850509 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 21057299 34.83% 34.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11707934 19.36% 54.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9587960 15.86% 70.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6925941 11.45% 81.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5557420 9.19% 90.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2847009 4.71% 95.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1835835 3.04% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 796714 1.32% 99.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 147588 0.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19806248 34.01% 34.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11039636 18.96% 52.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9348946 16.05% 69.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6752104 11.59% 80.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5521673 9.48% 90.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2974014 5.11% 95.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1775531 3.05% 98.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 852122 1.46% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 170776 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 60463700 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 58241050 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 186761 11.23% 11.23% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.23% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 209 0.01% 11.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 6487 0.39% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 3444 0.21% 11.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 845716 50.84% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 62.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 517920 31.13% 93.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 103033 6.19% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 161609 9.97% 9.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 218 0.01% 9.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 6469 0.40% 10.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 2295 0.14% 10.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 845619 52.17% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 62.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 527151 32.52% 95.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77634 4.79% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 64090689 60.52% 60.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 486042 0.46% 60.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2799885 2.64% 63.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 114989 0.11% 63.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2411237 2.28% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311681 0.29% 66.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 763573 0.72% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 27425152 25.90% 92.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7495540 7.08% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 63561145 60.57% 60.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 485535 0.46% 61.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2794061 2.66% 63.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115045 0.11% 63.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2411045 2.30% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 308682 0.29% 66.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 763571 0.73% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 318 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 27006510 25.74% 92.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7488931 7.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105899114 # Type of FU issued -system.cpu.iq.rate 1.748745 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1663570 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015709 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 259207602 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 152594620 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93309235 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15230484 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9878183 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7072078 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 99520074 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8042603 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1240194 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 104934850 # Type of FU issued +system.cpu.iq.rate 1.798857 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1620995 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015448 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 254843963 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 146750024 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 92740043 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15176315 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9791044 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7062550 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 98540004 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8015834 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1319105 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10733183 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14770 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 472388 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3020191 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 9753984 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 15279 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28494 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2882268 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10319 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 10177 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6644405 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 74686 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 16385 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 135563884 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 881728 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 30729381 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9521294 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 494 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 173 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 6079571 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 81043 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 15363 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 132624218 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 876009 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29750182 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9383371 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 510 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 184 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 33 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 472388 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1792269 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 350241 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2142510 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 103141866 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 26239584 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2757248 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 28494 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1787084 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 342134 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2129218 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 102333218 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25777384 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2601632 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 11884063 # number of nop insts executed -system.cpu.iew.exec_refs 33601488 # number of memory reference insts executed -system.cpu.iew.exec_branches 12972684 # Number of branches executed -system.cpu.iew.exec_stores 7361904 # Number of stores executed -system.cpu.iew.exec_rate 1.703214 # Inst execution rate -system.cpu.iew.wb_sent 101639951 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 100381313 # cumulative count of insts written-back -system.cpu.iew.wb_producers 68069676 # num instructions producing a value -system.cpu.iew.wb_consumers 93955815 # num instructions consuming a value +system.cpu.iew.exec_nop 11799539 # number of nop insts executed +system.cpu.iew.exec_refs 33141424 # number of memory reference insts executed +system.cpu.iew.exec_branches 12916232 # Number of branches executed +system.cpu.iew.exec_stores 7364040 # Number of stores executed +system.cpu.iew.exec_rate 1.754258 # Inst execution rate +system.cpu.iew.wb_sent 101006568 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99802593 # cumulative count of insts written-back +system.cpu.iew.wb_producers 67789343 # num instructions producing a value +system.cpu.iew.wb_consumers 93484829 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.657628 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.724486 # average fanout of values written-back +system.cpu.iew.wb_rate 1.710877 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.725137 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 43662883 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 40723267 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1895215 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 53819295 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.707623 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.466902 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1895854 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 52161479 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.761895 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.510937 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 24819499 46.12% 46.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11624197 21.60% 67.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5120039 9.51% 77.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2844700 5.29% 82.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1712935 3.18% 85.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1498439 2.78% 88.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 822147 1.53% 90.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 790849 1.47% 91.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4586490 8.52% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23655247 45.35% 45.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11195713 21.46% 66.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5070133 9.72% 76.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2810925 5.39% 81.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1675607 3.21% 85.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1392452 2.67% 87.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 795157 1.52% 89.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 831289 1.59% 90.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4734956 9.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 53819295 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 52161479 # Number of insts commited each cycle system.cpu.commit.count 91903055 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 26497301 # Number of memory references committed @@ -290,50 +290,50 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4586490 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4734956 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 184797703 # The number of ROB reads -system.cpu.rob.rob_writes 277819902 # The number of ROB writes -system.cpu.timesIdled 2285 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 93492 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 180051805 # The number of ROB reads +system.cpu.rob.rob_writes 271380444 # The number of ROB writes +system.cpu.timesIdled 2277 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 93138 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.719380 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.719380 # CPI: Total CPI of All Threads -system.cpu.ipc 1.390086 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.390086 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 139300854 # number of integer regfile reads -system.cpu.int_regfile_writes 75996636 # number of integer regfile writes -system.cpu.fp_regfile_reads 6185785 # number of floating regfile reads -system.cpu.fp_regfile_writes 6053506 # number of floating regfile writes -system.cpu.misc_regfile_reads 715599 # number of misc regfile reads +system.cpu.cpi 0.692972 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.692972 # CPI: Total CPI of All Threads +system.cpu.ipc 1.443060 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.443060 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 138495671 # number of integer regfile reads +system.cpu.int_regfile_writes 75435014 # number of integer regfile writes +system.cpu.fp_regfile_reads 6177236 # number of floating regfile reads +system.cpu.fp_regfile_writes 6044349 # number of floating regfile writes +system.cpu.misc_regfile_reads 715554 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8657 # number of replacements -system.cpu.icache.tagsinuse 1596.063648 # Cycle average of tags in use -system.cpu.icache.total_refs 19358424 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10590 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1827.990935 # Average number of references to valid blocks. +system.cpu.icache.replacements 8695 # number of replacements +system.cpu.icache.tagsinuse 1593.002324 # Cycle average of tags in use +system.cpu.icache.total_refs 18592194 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10628 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1749.359616 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1596.063648 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.779328 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 19358424 # number of ReadReq hits -system.cpu.icache.demand_hits 19358424 # number of demand (read+write) hits -system.cpu.icache.overall_hits 19358424 # number of overall hits -system.cpu.icache.ReadReq_misses 11813 # number of ReadReq misses -system.cpu.icache.demand_misses 11813 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11813 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 188211000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 188211000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 188211000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 19370237 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 19370237 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 19370237 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000610 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000610 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000610 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 15932.531956 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 15932.531956 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 15932.531956 # average overall miss latency +system.cpu.icache.occ_blocks::0 1593.002324 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.777833 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 18592194 # number of ReadReq hits +system.cpu.icache.demand_hits 18592194 # number of demand (read+write) hits +system.cpu.icache.overall_hits 18592194 # number of overall hits +system.cpu.icache.ReadReq_misses 11853 # number of ReadReq misses +system.cpu.icache.demand_misses 11853 # number of demand (read+write) misses +system.cpu.icache.overall_misses 11853 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 188036500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 188036500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 188036500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 18604047 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 18604047 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 18604047 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000637 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000637 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000637 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 15864.042858 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 15864.042858 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 15864.042858 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -343,65 +343,65 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1223 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1223 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1223 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 10590 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 10590 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 10590 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1225 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1225 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1225 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 10628 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 10628 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 10628 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 124783500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 124783500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 124783500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 124769000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 124769000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 124769000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000547 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000547 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000547 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11783.144476 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11783.144476 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11783.144476 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000571 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000571 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000571 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11739.649981 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11739.649981 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11739.649981 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 156 # number of replacements -system.cpu.dcache.tagsinuse 1459.699326 # Cycle average of tags in use -system.cpu.dcache.total_refs 30929897 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2239 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13814.156766 # Average number of references to valid blocks. +system.cpu.dcache.replacements 159 # number of replacements +system.cpu.dcache.tagsinuse 1462.507461 # Cycle average of tags in use +system.cpu.dcache.total_refs 30399158 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2246 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 13534.798753 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1459.699326 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.356372 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 24436799 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 6493056 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 42 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 30929855 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 30929855 # number of overall hits -system.cpu.dcache.ReadReq_misses 922 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 8047 # number of WriteReq misses +system.cpu.dcache.occ_blocks::0 1462.507461 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.357057 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 23906051 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 6493055 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 52 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 30399106 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 30399106 # number of overall hits +system.cpu.dcache.ReadReq_misses 938 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 8048 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 8969 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 8969 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 27935000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 289776500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 8986 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 8986 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 28163500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 289889000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 38000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 317711500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 317711500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 24437721 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 318052500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 318052500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 23906989 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 30938824 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 30938824 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 30408092 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 30408092 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.001238 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.023256 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.000290 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000290 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 30298.264642 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 36010.500808 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_miss_rate 0.018868 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.000296 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000296 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 30025.053305 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 36020.004970 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35423.291337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35423.291337 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 35394.224349 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35394.224349 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -410,73 +410,73 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 106 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 416 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6315 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 6731 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 6731 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1732 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks 108 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 424 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6317 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 6741 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 6741 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 514 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1731 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2238 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2238 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 2245 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2245 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 16310000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 61605000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 16469500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 61655000 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 77915000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 77915000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 78124500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 78124500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.023256 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000072 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000072 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32233.201581 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35568.706697 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.018868 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.000074 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000074 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32041.828794 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35618.139804 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34814.566577 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34814.566577 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34799.331849 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34799.331849 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2399.023561 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7622 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3552 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.145833 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2400.275766 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7666 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3556 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.155793 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2381.411279 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.612282 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.072675 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000537 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 7611 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 106 # number of Writeback hits +system.cpu.l2cache.occ_blocks::0 2382.642182 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 17.633584 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.072712 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000538 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 7655 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 108 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 25 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 7636 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 7636 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3486 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1707 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5193 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5193 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 119743000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 59251500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 178994500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 178994500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 11097 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1732 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 12829 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 12829 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.314139 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.985566 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.404786 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.404786 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34349.684452 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34710.896309 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34468.419026 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34468.419026 # average overall miss latency +system.cpu.l2cache.demand_hits 7680 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 7680 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3488 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 1706 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 5194 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 5194 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 119792500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 59244000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 179036500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 179036500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 11143 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 108 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1731 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 12874 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 12874 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.313022 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.985557 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.403449 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.403449 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34344.180046 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34726.846424 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34469.869080 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34469.869080 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -488,24 +488,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3486 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1707 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5193 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5193 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 3488 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1706 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 5194 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 5194 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 108417500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 53859000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 162276500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 162276500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 108490000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 53828000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 162318000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 162318000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.314139 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985566 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.404786 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.404786 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31100.831899 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31551.845343 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31249.085307 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31249.085307 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.313022 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985557 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.403449 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.403449 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31103.784404 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31552.168816 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31251.058914 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31251.058914 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini index 00b76845b..342457a8b 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/arm/linux/twolf +executable=/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout index c549133d9..7a94cf61c 100755 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/s gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 19:27:45 -gem5 started Aug 17 2011 19:41:03 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 12:27:58 +gem5 started Aug 20 2011 12:28:18 +gem5 executing on zizzer command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sav Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sv2 @@ -25,4 +25,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 108225133500 because target called exit() +122 123 124 Exiting @ tick 105782426500 because target called exit() diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt index 0b4a9f9c5..9c02493cb 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.108225 # Number of seconds simulated -sim_ticks 108225133500 # Number of ticks simulated +sim_seconds 0.105782 # Number of seconds simulated +sim_ticks 105782426500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75904 # Simulator instruction rate (inst/s) -host_tick_rate 43540817 # Simulator tick rate (ticks/s) -host_mem_usage 267548 # Number of bytes of host memory used -host_seconds 2485.60 # Real time elapsed on the host -sim_insts 188667477 # Number of instructions simulated +host_inst_rate 104930 # Simulator instruction rate (inst/s) +host_tick_rate 58832155 # Simulator tick rate (ticks/s) +host_mem_usage 220996 # Number of bytes of host memory used +host_seconds 1798.04 # Real time elapsed on the host +sim_insts 188667447 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,299 +51,299 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 216450268 # number of cpu cycles simulated +system.cpu.numCycles 211564854 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 103300495 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 81633853 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 9933179 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 85260221 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79838053 # Number of BTB hits +system.cpu.BPredUnit.lookups 102102959 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80693522 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 9934423 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 84198795 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79209656 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4770425 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 112925 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 45859797 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 427202269 # Number of instructions fetch has processed -system.cpu.fetch.Branches 103300495 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 84608478 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 110661906 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 34687559 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 35479219 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 650 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4697254 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 112889 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 44543100 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 416703604 # Number of instructions fetch has processed +system.cpu.fetch.Branches 102102959 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 83906910 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 108778714 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 33211132 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 34936553 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 16 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 779 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 41734734 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2307922 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 216391705 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.142578 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.666710 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 40617038 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2208646 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 211506610 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.137206 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.647564 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 105933481 48.95% 48.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4813111 2.22% 51.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 32934004 15.22% 66.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 18446280 8.52% 74.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 9282990 4.29% 79.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 12615981 5.83% 85.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 8571229 3.96% 89.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4380123 2.02% 91.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 19414506 8.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 102929819 48.67% 48.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4598020 2.17% 50.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 32955527 15.58% 66.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 18221421 8.62% 75.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 9181259 4.34% 79.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 12523238 5.92% 85.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 8470282 4.00% 89.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4319419 2.04% 91.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 18307625 8.66% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 216391705 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.477248 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.973674 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 54721006 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 34041868 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 102087484 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1309075 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 24232272 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14250687 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 167114 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 433129762 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 697150 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 24232272 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63872072 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 611164 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 28890421 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 94161740 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4624036 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 397542070 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 22398 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2387180 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 678079214 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1699552910 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1681277450 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 18275460 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298061696 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 380017513 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2786987 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2738977 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 24570466 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 49895918 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 17636120 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4759553 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2845254 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 339889742 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2325465 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 265876001 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1090686 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 151055977 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 362148819 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 689877 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 216391705 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.228679 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.485743 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 211506610 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.482608 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.969626 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 53228641 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 33488153 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 100485702 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1214398 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 23089716 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14176819 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 166958 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 422710144 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 694356 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 23089716 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 62181422 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 455271 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28556828 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 92670031 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4553342 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 388732639 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 21427 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2224138 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 666278753 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1657677699 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1639787081 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17890618 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298061648 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 368217100 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2705646 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2657641 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 23338281 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 46771972 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16999423 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3794588 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2434419 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 332719440 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2206649 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 261972515 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1005249 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 143535623 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 342170938 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 571067 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 211506610 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.238602 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.491475 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 100636897 46.51% 46.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 38680237 17.88% 64.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34682486 16.03% 80.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 22976662 10.62% 91.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 11626624 5.37% 96.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4959669 2.29% 98.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2310222 1.07% 99.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 416631 0.19% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 102277 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 97729672 46.21% 46.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 37811383 17.88% 64.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34093128 16.12% 80.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 22769109 10.77% 90.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 11443716 5.41% 96.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4778532 2.26% 98.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2323194 1.10% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 402147 0.19% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 155729 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 216391705 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 211506610 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 400224 18.78% 18.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5529 0.26% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 59 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 1 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 41 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1248313 58.57% 77.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 477105 22.39% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 397392 17.88% 17.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5524 0.25% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 54 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 43 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1333839 60.01% 78.15% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 485736 21.85% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 206820187 77.79% 77.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 928873 0.35% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 5969 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33098 0.01% 78.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 166620 0.06% 78.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 261178 0.10% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76402 0.03% 78.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 472124 0.18% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 207762 0.08% 78.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71816 0.03% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 326 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 42647461 16.04% 94.67% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 14184185 5.33% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 205005652 78.25% 78.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 928362 0.35% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 5862 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33106 0.01% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 166621 0.06% 78.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 256879 0.10% 78.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76399 0.03% 78.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 467584 0.18% 78.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 207638 0.08% 79.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71818 0.03% 79.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 328 0.00% 79.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 40692198 15.53% 94.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 14060068 5.37% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 265876001 # Type of FU issued -system.cpu.iq.rate 1.228347 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2131272 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008016 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 747569642 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 491340043 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 245818526 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3796023 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2315934 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1850284 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266096231 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1911042 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1286575 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 261972515 # Type of FU issued +system.cpu.iq.rate 1.238261 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2222588 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008484 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 734922033 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 476231649 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 242866615 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3757444 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2242269 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1844486 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 262305042 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1890061 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1598366 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 20044239 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 9909 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 389239 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4989293 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 16920299 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 31179 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12638 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4352602 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 21 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 24232272 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 29384 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2101 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 342268798 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4011941 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 49895918 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 17636120 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2301609 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 367 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1495 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 389239 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10042133 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1698405 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11740538 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 252918304 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 40460736 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12957697 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 23089716 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 13717 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1061 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 334979671 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 3743340 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 46771972 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16999423 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2182801 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 480 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 255 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12638 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 9998550 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1696549 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11695099 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 249247765 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 38548373 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 12724750 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 53591 # number of nop insts executed -system.cpu.iew.exec_refs 54201060 # number of memory reference insts executed -system.cpu.iew.exec_branches 52956495 # Number of branches executed -system.cpu.iew.exec_stores 13740324 # Number of stores executed -system.cpu.iew.exec_rate 1.168482 # Inst execution rate -system.cpu.iew.wb_sent 249352337 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 247668810 # cumulative count of insts written-back -system.cpu.iew.wb_producers 150626342 # num instructions producing a value -system.cpu.iew.wb_consumers 251613909 # num instructions consuming a value +system.cpu.iew.exec_nop 53582 # number of nop insts executed +system.cpu.iew.exec_refs 52189835 # number of memory reference insts executed +system.cpu.iew.exec_branches 52589546 # Number of branches executed +system.cpu.iew.exec_stores 13641462 # Number of stores executed +system.cpu.iew.exec_rate 1.178115 # Inst execution rate +system.cpu.iew.wb_sent 246271273 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 244711101 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148454614 # num instructions producing a value +system.cpu.iew.wb_consumers 247957784 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.144230 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.598641 # average fanout of values written-back +system.cpu.iew.wb_rate 1.156672 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.598709 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 188681865 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 153577683 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1635588 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9794361 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 192159434 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.981903 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.655341 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 188681835 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 146288700 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1635582 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9795726 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 188416895 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.001406 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.682967 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 108154489 56.28% 56.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41572533 21.63% 77.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 19548903 10.17% 88.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8803666 4.58% 92.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5118368 2.66% 95.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2098797 1.09% 96.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1631204 0.85% 97.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1005945 0.52% 97.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4225529 2.20% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 105298145 55.89% 55.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 40798709 21.65% 77.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 19462081 10.33% 87.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8761911 4.65% 92.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4909468 2.61% 95.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2009419 1.07% 96.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1710426 0.91% 97.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1008180 0.54% 97.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4458556 2.37% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 192159434 # Number of insts commited each cycle -system.cpu.commit.count 188681865 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 188416895 # Number of insts commited each cycle +system.cpu.commit.count 188681835 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42498505 # Number of memory references committed -system.cpu.commit.loads 29851678 # Number of loads committed +system.cpu.commit.refs 42498493 # Number of memory references committed +system.cpu.commit.loads 29851672 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40283876 # Number of branches committed +system.cpu.commit.branches 40283870 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150114997 # Number of committed integer instructions. +system.cpu.commit.int_insts 150114973 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4225529 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4458556 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 530188252 # The number of ROB reads -system.cpu.rob.rob_writes 708816282 # The number of ROB writes -system.cpu.timesIdled 1726 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 58563 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 188667477 # Number of Instructions Simulated -system.cpu.committedInsts_total 188667477 # Number of Instructions Simulated -system.cpu.cpi 1.147258 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.147258 # CPI: Total CPI of All Threads -system.cpu.ipc 0.871644 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.871644 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1130629656 # number of integer regfile reads -system.cpu.int_regfile_writes 411782000 # number of integer regfile writes -system.cpu.fp_regfile_reads 2929902 # number of floating regfile reads -system.cpu.fp_regfile_writes 2506543 # number of floating regfile writes -system.cpu.misc_regfile_reads 516287293 # number of misc regfile reads -system.cpu.misc_regfile_writes 824422 # number of misc regfile writes -system.cpu.icache.replacements 1945 # number of replacements -system.cpu.icache.tagsinuse 1331.549144 # Cycle average of tags in use -system.cpu.icache.total_refs 41730466 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3654 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11420.488779 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 518923673 # The number of ROB reads +system.cpu.rob.rob_writes 693093847 # The number of ROB writes +system.cpu.timesIdled 1715 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 58244 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 188667447 # Number of Instructions Simulated +system.cpu.committedInsts_total 188667447 # Number of Instructions Simulated +system.cpu.cpi 1.121364 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.121364 # CPI: Total CPI of All Threads +system.cpu.ipc 0.891771 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.891771 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1112037925 # number of integer regfile reads +system.cpu.int_regfile_writes 407325224 # number of integer regfile writes +system.cpu.fp_regfile_reads 2928951 # number of floating regfile reads +system.cpu.fp_regfile_writes 2497682 # number of floating regfile writes +system.cpu.misc_regfile_reads 502867512 # number of misc regfile reads +system.cpu.misc_regfile_writes 824410 # number of misc regfile writes +system.cpu.icache.replacements 1940 # number of replacements +system.cpu.icache.tagsinuse 1334.073699 # Cycle average of tags in use +system.cpu.icache.total_refs 40612809 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 3646 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11139.004114 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1331.549144 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.650170 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 41730466 # number of ReadReq hits -system.cpu.icache.demand_hits 41730466 # number of demand (read+write) hits -system.cpu.icache.overall_hits 41730466 # number of overall hits -system.cpu.icache.ReadReq_misses 4268 # number of ReadReq misses -system.cpu.icache.demand_misses 4268 # number of demand (read+write) misses -system.cpu.icache.overall_misses 4268 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 101918000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 101918000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 101918000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 41734734 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 41734734 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 41734734 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000102 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000102 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000102 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 23879.568885 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 23879.568885 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 23879.568885 # average overall miss latency +system.cpu.icache.occ_blocks::0 1334.073699 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.651403 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 40612809 # number of ReadReq hits +system.cpu.icache.demand_hits 40612809 # number of demand (read+write) hits +system.cpu.icache.overall_hits 40612809 # number of overall hits +system.cpu.icache.ReadReq_misses 4229 # number of ReadReq misses +system.cpu.icache.demand_misses 4229 # number of demand (read+write) misses +system.cpu.icache.overall_misses 4229 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 101377500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 101377500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 101377500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 40617038 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 40617038 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 40617038 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000104 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000104 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000104 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 23971.979191 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 23971.979191 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 23971.979191 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,67 +353,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 614 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 614 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 614 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 3654 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 3654 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 3654 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 583 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 583 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 583 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 3646 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 3646 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 3646 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 74785000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 74785000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 74785000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 74805000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 74805000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 74805000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000088 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 20466.611932 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 20466.611932 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 20466.611932 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000090 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000090 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000090 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 20517.004937 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 20517.004937 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 20517.004937 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 53 # number of replacements -system.cpu.dcache.tagsinuse 1408.919446 # Cycle average of tags in use -system.cpu.dcache.total_refs 50759192 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1852 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27407.771058 # Average number of references to valid blocks. +system.cpu.dcache.replacements 55 # number of replacements +system.cpu.dcache.tagsinuse 1408.142162 # Cycle average of tags in use +system.cpu.dcache.total_refs 48578921 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1851 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 26244.689897 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1408.919446 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.343974 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 38350065 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 12356747 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 27780 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 24600 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 50706812 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 50706812 # number of overall hits -system.cpu.dcache.ReadReq_misses 1815 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 7540 # number of WriteReq misses +system.cpu.dcache.occ_blocks::0 1408.142162 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.343785 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 36170054 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 12356741 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 27532 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 24594 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 48526795 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 48526795 # number of overall hits +system.cpu.dcache.ReadReq_misses 1787 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 7546 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 9355 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 9355 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 59756000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 236779500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 9333 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 9333 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 59024500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 236727000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 63500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 296535500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 296535500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 38351880 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 295751500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 295751500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 36171841 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 27782 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 24600 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 50716167 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 50716167 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses 27534 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 24594 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 48536128 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 48536128 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000049 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.000610 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000072 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.000184 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000184 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 32923.415978 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 31403.116711 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_miss_rate 0.000073 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.000192 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000192 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 33029.938444 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 31371.190034 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 31750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 31698.075895 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 31698.075895 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 31688.792457 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 31688.792457 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 20500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,70 +422,70 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 20500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 17 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1051 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6452 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 19 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1026 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6456 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 7503 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 7503 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 764 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1088 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1852 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1852 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 7482 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 7482 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 761 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1090 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1851 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1851 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24358000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 38245500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 62603500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 62603500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 24308000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 38322000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 62630000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 62630000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000037 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000037 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31882.198953 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35152.113971 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33803.185745 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33803.185745 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.000038 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000038 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31942.181340 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35157.798165 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 33835.764452 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 33835.764452 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1935.489256 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1725 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2688 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.641741 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 1934.153388 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1714 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2689 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.637412 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1932.435208 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3.054049 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058973 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1931.095297 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 3.058091 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.058932 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.000093 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1725 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 17 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits 1714 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 19 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 9 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1734 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1734 # number of overall hits +system.cpu.l2cache.demand_hits 1723 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1723 # number of overall hits system.cpu.l2cache.ReadReq_misses 2693 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1079 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 3772 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 3772 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 92325500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 37082000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 129407500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 129407500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 4418 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 17 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1088 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 5506 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 5506 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.609552 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.991728 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.685071 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.685071 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34283.512811 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34367.006487 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34307.396607 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34307.396607 # average overall miss latency +system.cpu.l2cache.ReadExReq_misses 1081 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 3774 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 3774 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 92316000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 37162000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 129478000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 129478000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 4407 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 19 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1090 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 5497 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 5497 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.611073 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.991743 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.686556 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.686556 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34279.985147 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34377.428307 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34307.896131 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34307.896131 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -495,27 +495,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets no_value system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 13 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 13 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 13 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 2680 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1079 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 3759 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 3759 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 14 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 2679 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1081 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 3760 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 3760 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 83299500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 33503500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 116803000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 116803000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 83267000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 33562000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 116829000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 116829000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.606609 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.991728 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.682710 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.682710 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.902985 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31050.509731 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31072.891727 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31072.891727 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.607897 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.991743 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.684009 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.684009 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.373647 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31047.178538 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31071.542553 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31071.542553 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini index 5bb467c35..8802a5811 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/x86/linux/twolf +executable=/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout index 7a3f808a7..f7d229ce0 100755 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout @@ -3,10 +3,12 @@ Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/s gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 17:25:41 -gem5 started Aug 17 2011 17:43:51 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 13:24:14 +gem5 started Aug 20 2011 13:24:28 +gem5 executing on zizzer command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,4 +26,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 99831779000 because target called exit() +122 123 124 Exiting @ tick 96610526000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index 21b77f826..43a8220e5 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,251 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.099832 # Number of seconds simulated -sim_ticks 99831779000 # Number of ticks simulated +sim_seconds 0.096611 # Number of seconds simulated +sim_ticks 96610526000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87193 # Simulator instruction rate (inst/s) -host_tick_rate 39323014 # Simulator tick rate (ticks/s) -host_mem_usage 268152 # Number of bytes of host memory used -host_seconds 2538.76 # Real time elapsed on the host +host_inst_rate 102112 # Simulator instruction rate (inst/s) +host_tick_rate 44565176 # Simulator tick rate (ticks/s) +host_mem_usage 220868 # Number of bytes of host memory used +host_seconds 2167.85 # Real time elapsed on the host sim_insts 221363017 # Number of instructions simulated system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 199663559 # number of cpu cycles simulated +system.cpu.numCycles 193221053 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 26033375 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 26033375 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2892272 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 23801635 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 21124617 # Number of BTB hits +system.cpu.BPredUnit.lookups 25817967 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 25817967 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2894858 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 23614164 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 20981330 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31432261 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 264493397 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26033375 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 21124617 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 71518034 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27440776 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 72430048 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 173 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1577 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 29258071 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 583239 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 199575786 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.208704 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.313982 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30977399 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 261503264 # Number of instructions fetch has processed +system.cpu.fetch.Branches 25817967 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 20981330 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70791188 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26915794 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 67651206 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 160 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1398 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 28846864 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 549492 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 193133856 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.260391 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.334586 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 129959453 65.12% 65.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4150455 2.08% 67.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3286315 1.65% 68.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4425223 2.22% 71.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4327377 2.17% 73.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4568651 2.29% 75.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5572926 2.79% 78.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3068408 1.54% 79.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 40216978 20.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 124189193 64.30% 64.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4110604 2.13% 66.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3242349 1.68% 68.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4337138 2.25% 70.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4293938 2.22% 72.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4598067 2.38% 74.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5546943 2.87% 77.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3021455 1.56% 79.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 39794169 20.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 199575786 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.130386 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.324695 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45674333 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 62083287 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 57427578 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10196895 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 24193693 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 428380569 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 24193693 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 54435501 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 16645801 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 21737 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 58104790 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 46174264 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 415835044 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 22459451 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 21291992 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 441873091 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1077088979 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1065665407 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 11423572 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 193133856 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.133619 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.353389 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 44744191 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 57710964 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 57165261 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9800935 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 23712505 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 424257825 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 23712505 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 53368695 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14594998 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21883 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 57606354 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 43829421 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 411666463 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 18981117 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22454802 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 438110122 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1066455351 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1055559190 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10896161 # Number of floating rename lookups system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 207509682 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1829 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1823 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 98204521 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 105334480 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37821412 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 75455534 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 24783352 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 400833570 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1827 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 286380326 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 245766 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 179000562 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 366769994 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 581 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 199575786 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.434945 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.451491 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 203746713 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1780 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1774 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 94916865 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104240418 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 37277466 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 67123936 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21592423 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 396698453 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1768 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 287681057 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 248197 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 174766428 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 350779105 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 522 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 193133856 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.489542 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.479240 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 64436357 32.29% 32.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 57784347 28.95% 61.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 35429830 17.75% 78.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 21049464 10.55% 89.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 13197205 6.61% 96.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 5079102 2.54% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1923482 0.96% 99.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 545287 0.27% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 130712 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 60593209 31.37% 31.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 53908728 27.91% 59.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 35738338 18.50% 77.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 21062429 10.91% 88.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 13747169 7.12% 95.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 5239198 2.71% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2106456 1.09% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 621668 0.32% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 116661 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 199575786 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 193133856 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 94614 3.23% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2515029 85.77% 88.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 322713 11.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 106266 3.87% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2319161 84.53% 88.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 318223 11.60% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1207901 0.42% 0.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 187612443 65.51% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1650340 0.58% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 71566969 24.99% 91.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 24342673 8.50% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1204809 0.42% 0.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 187032245 65.01% 65.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1651608 0.57% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 73242981 25.46% 91.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 24549414 8.53% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 286380326 # Type of FU issued -system.cpu.iq.rate 1.434314 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2932356 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010239 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 770019302 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 574569480 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 277218966 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5495258 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 5820238 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2640122 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 285339093 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2765688 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17496370 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 287681057 # Type of FU issued +system.cpu.iq.rate 1.488870 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2743650 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009537 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 765972748 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 566387994 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 278383951 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5515069 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 5414925 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2649060 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 286446350 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2773548 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18375293 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 48684890 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26476 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 567154 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 17305696 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 47590828 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 32389 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 343467 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16761750 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 45677 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 46017 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 24193693 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 457791 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 303468 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 400835397 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 134633 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 105334480 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 37821412 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1827 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 212810 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14667 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 567154 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2502429 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 590366 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3092795 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 282646911 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 70091222 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3733415 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 23712505 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 356267 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 212332 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 396700221 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 134682 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104240418 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 37277466 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1768 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 118966 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14039 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 343467 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2505670 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 594786 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3100456 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 283858854 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 71711617 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3822203 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 93958027 # number of memory reference insts executed -system.cpu.iew.exec_branches 15691329 # Number of branches executed -system.cpu.iew.exec_stores 23866805 # Number of stores executed -system.cpu.iew.exec_rate 1.415616 # Inst execution rate -system.cpu.iew.wb_sent 281113586 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 279859088 # cumulative count of insts written-back -system.cpu.iew.wb_producers 226653177 # num instructions producing a value -system.cpu.iew.wb_consumers 377782482 # num instructions consuming a value +system.cpu.iew.exec_refs 95762495 # number of memory reference insts executed +system.cpu.iew.exec_branches 15668383 # Number of branches executed +system.cpu.iew.exec_stores 24050878 # Number of stores executed +system.cpu.iew.exec_rate 1.469089 # Inst execution rate +system.cpu.iew.wb_sent 282330192 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 281033011 # cumulative count of insts written-back +system.cpu.iew.wb_producers 227942764 # num instructions producing a value +system.cpu.iew.wb_consumers 378918606 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.401653 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.599957 # average fanout of values written-back +system.cpu.iew.wb_rate 1.454464 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.601561 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 179482154 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 175344362 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2892451 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 175382093 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.262176 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.674972 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2895014 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 169421351 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.306583 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.742468 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 66614816 37.98% 37.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 64778126 36.94% 74.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 16236292 9.26% 84.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12183178 6.95% 91.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5701402 3.25% 94.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3006065 1.71% 96.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2037233 1.16% 97.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1096406 0.63% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3728575 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 63568929 37.52% 37.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 62259787 36.75% 74.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15643694 9.23% 83.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11988406 7.08% 90.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5417709 3.20% 93.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2980917 1.76% 95.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2013932 1.19% 96.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1192205 0.70% 97.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4355772 2.57% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 175382093 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 169421351 # Number of insts commited each cycle system.cpu.commit.count 221363017 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 77165306 # Number of memory references committed @@ -255,50 +255,50 @@ system.cpu.commit.branches 12326943 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 3728575 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4355772 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 572498689 # The number of ROB reads -system.cpu.rob.rob_writes 825932723 # The number of ROB writes -system.cpu.timesIdled 1919 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 87773 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 561772958 # The number of ROB reads +system.cpu.rob.rob_writes 817171098 # The number of ROB writes +system.cpu.timesIdled 1889 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 87197 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 221363017 # Number of Instructions Simulated system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated -system.cpu.cpi 0.901973 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.901973 # CPI: Total CPI of All Threads -system.cpu.ipc 1.108680 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.108680 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 526429192 # number of integer regfile reads -system.cpu.int_regfile_writes 287807377 # number of integer regfile writes -system.cpu.fp_regfile_reads 3610412 # number of floating regfile reads -system.cpu.fp_regfile_writes 2295659 # number of floating regfile writes -system.cpu.misc_regfile_reads 148624711 # number of misc regfile reads +system.cpu.cpi 0.872870 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.872870 # CPI: Total CPI of All Threads +system.cpu.ipc 1.145646 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.145646 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 530742767 # number of integer regfile reads +system.cpu.int_regfile_writes 288972647 # number of integer regfile writes +system.cpu.fp_regfile_reads 3616458 # number of floating regfile reads +system.cpu.fp_regfile_writes 2303580 # number of floating regfile writes +system.cpu.misc_regfile_reads 149927786 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 4242 # number of replacements -system.cpu.icache.tagsinuse 1597.360420 # Cycle average of tags in use -system.cpu.icache.total_refs 29250473 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6209 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4710.979707 # Average number of references to valid blocks. +system.cpu.icache.replacements 4235 # number of replacements +system.cpu.icache.tagsinuse 1597.100373 # Cycle average of tags in use +system.cpu.icache.total_refs 28839309 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6200 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4651.501452 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1597.360420 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.779961 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 29250474 # number of ReadReq hits -system.cpu.icache.demand_hits 29250474 # number of demand (read+write) hits -system.cpu.icache.overall_hits 29250474 # number of overall hits -system.cpu.icache.ReadReq_misses 7597 # number of ReadReq misses -system.cpu.icache.demand_misses 7597 # number of demand (read+write) misses -system.cpu.icache.overall_misses 7597 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 175067500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 175067500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 175067500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 29258071 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 29258071 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 29258071 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000260 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000260 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000260 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 23044.293800 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 23044.293800 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 23044.293800 # average overall miss latency +system.cpu.icache.occ_blocks::0 1597.100373 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.779834 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 28839309 # number of ReadReq hits +system.cpu.icache.demand_hits 28839309 # number of demand (read+write) hits +system.cpu.icache.overall_hits 28839309 # number of overall hits +system.cpu.icache.ReadReq_misses 7555 # number of ReadReq misses +system.cpu.icache.demand_misses 7555 # number of demand (read+write) misses +system.cpu.icache.overall_misses 7555 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 173857500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 173857500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 173857500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 28846864 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 28846864 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 28846864 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000262 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000262 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000262 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 23012.243547 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 23012.243547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 23012.243547 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -308,59 +308,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1135 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1135 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1135 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 6462 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 6462 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 6462 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1113 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1113 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1113 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 6442 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 6442 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 6442 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 125815000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 125815000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 125815000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 125492000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 125492000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 125492000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000221 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000221 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000221 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 19469.978335 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 19469.978335 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 19469.978335 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000223 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000223 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000223 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 19480.285626 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 19480.285626 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 19480.285626 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 58 # number of replacements -system.cpu.dcache.tagsinuse 1414.389130 # Cycle average of tags in use -system.cpu.dcache.total_refs 72873832 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1985 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 36712.257935 # Average number of references to valid blocks. +system.cpu.dcache.replacements 59 # number of replacements +system.cpu.dcache.tagsinuse 1420.172872 # Cycle average of tags in use +system.cpu.dcache.total_refs 73596568 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1986 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37057.687815 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1414.389130 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.345310 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 52365835 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 20507475 # number of WriteReq hits -system.cpu.dcache.demand_hits 72873310 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 72873310 # number of overall hits -system.cpu.dcache.ReadReq_misses 884 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 8255 # number of WriteReq misses -system.cpu.dcache.demand_misses 9139 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 9139 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 27524500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 227342500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 254867000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 254867000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 52366719 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 1420.172872 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.346722 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 53088625 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 20507488 # number of WriteReq hits +system.cpu.dcache.demand_hits 73596113 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 73596113 # number of overall hits +system.cpu.dcache.ReadReq_misses 844 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 8242 # number of WriteReq misses +system.cpu.dcache.demand_misses 9086 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 9086 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 26292500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 227102000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 253394500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 253394500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 53089469 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 72882449 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 72882449 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 73605199 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 73605199 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000016 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.000402 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000125 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 31136.312217 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 27539.975772 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 27887.843309 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 27887.843309 # average overall miss latency +system.cpu.dcache.demand_miss_rate 0.000123 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000123 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 31152.251185 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 27554.234409 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 27888.454766 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 27888.454766 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -370,71 +370,71 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 14 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 460 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6439 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 6899 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 6899 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 420 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6436 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 6856 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 6856 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 424 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1816 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2240 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2240 # number of overall MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1806 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2230 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2230 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14073500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 63530000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 77603500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 77603500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 14047000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 63209500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 77256500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 77256500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000031 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 33192.216981 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34983.480176 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34644.419643 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34644.419643 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.000030 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000030 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 33129.716981 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34999.723145 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34644.170404 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34644.170404 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2508.886918 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2866 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3770 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.760212 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2499.008056 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2867 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3761 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.762297 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2507.064055 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1.822864 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.076510 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000056 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2865 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::0 2497.026903 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 1.981153 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.076203 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000060 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 2866 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 14 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 2873 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2873 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3766 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 253 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 1556 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5322 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5322 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 128966500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 53203000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 182169500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 182169500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 6631 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_hits 2874 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2874 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3757 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 242 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 1557 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 5314 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 5314 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 128666000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 53239000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 181905000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 181905000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 6623 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 14 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 253 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1564 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 8195 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 8195 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.567938 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_accesses 242 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1565 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 8188 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 8188 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.567266 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.994885 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.649420 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.649420 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34244.954859 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34192.159383 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34229.518978 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34229.518978 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate 0.994888 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.648999 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.648999 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34247.005590 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34193.320488 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34231.275875 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34231.275875 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -446,28 +446,28 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3766 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 253 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1556 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5322 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5322 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 3757 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 242 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1557 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 5314 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 5314 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 116813500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7843000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 48344500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 165158000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 165158000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 116539500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7502000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 48375000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 164914500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 164914500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.567938 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.567266 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994885 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.649420 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.649420 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31017.923526 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994888 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.648999 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.648999 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.297312 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.730077 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31033.070274 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31033.070274 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.364162 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31033.966880 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31033.966880 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |