diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2010-10-31 00:07:48 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-10-31 00:07:48 -0700 |
| commit | b53231e7feeb6535f9bbb06a8bfd52208d6fa215 (patch) | |
| tree | 4e9b81e94dd0228a64e18d3b9299362d3b87d62b /tests/long | |
| parent | 6f4bd2c1da0dc7783da87c4877a41332901199b2 (diff) | |
| download | gem5-b53231e7feeb6535f9bbb06a8bfd52208d6fa215.tar.xz | |
Ref output: Update refs for PCState change.
Diffstat (limited to 'tests/long')
| -rw-r--r-- | tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini | 2 | ||||
| -rwxr-xr-x | tests/long/00.gzip/ref/sparc/linux/o3-timing/simout | 10 | ||||
| -rw-r--r-- | tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt | 644 |
3 files changed, 328 insertions, 328 deletions
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 5d6f66b52..659cb8ca7 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/gzip +executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index b4e773530..6ef53b4dd 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 16:20:33 -M5 executing on phenom +M5 compiled Sep 26 2010 21:00:10 +M5 revision eb8d8f78ca15 7689 default qtip tip pctype.patch qbase +M5 started Sep 26 2010 21:05:23 +M5 executing on burrito command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -43,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1095331467500 because target called exit() +Exiting @ tick 601454696500 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 68e9f863d..5cdef52fc 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,414 +1,414 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 138841 # Simulator instruction rate (inst/s) -host_mem_usage 198176 # Number of bytes of host memory used -host_seconds 10123.96 # Real time elapsed on the host -host_tick_rate 108192045 # Simulator tick rate (ticks/s) +host_inst_rate 119996 # Simulator instruction rate (inst/s) +host_mem_usage 230000 # Number of bytes of host memory used +host_seconds 11713.80 # Real time elapsed on the host +host_tick_rate 51345807 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1405618374 # Number of instructions simulated -sim_seconds 1.095331 # Number of seconds simulated -sim_ticks 1095331467500 # Number of ticks simulated +sim_insts 1405604152 # Number of instructions simulated +sim_seconds 0.601455 # Number of seconds simulated +sim_ticks 601454696500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 175591574 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 198504175 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 98804348 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 100538146 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 83489596 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 252577407 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 252577407 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 5348299 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 105812900 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 105812900 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 86248929 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 9068364 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 21328327 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1951658061 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.763216 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.203742 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1172134111 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.270779 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.680126 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 1079992719 55.34% 55.34% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 573544089 29.39% 84.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 118996755 6.10% 90.82% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 118578034 6.08% 96.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 27958213 1.43% 98.33% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 7829070 0.40% 98.73% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 11095017 0.57% 99.30% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 4595800 0.24% 99.54% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 9068364 0.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 418023744 35.66% 35.66% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 498322579 42.51% 78.18% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 52995965 4.52% 82.70% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 103673250 8.84% 91.54% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 32915504 2.81% 94.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 8294294 0.71% 95.06% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 25634202 2.19% 97.25% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 10946246 0.93% 98.18% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 21328327 1.82% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1951658061 # Number of insts commited each cycle -system.cpu.commit.COM:count 1489537517 # Number of instructions committed -system.cpu.commit.COM:loads 402517252 # Number of loads committed +system.cpu.commit.COM:committed_per_cycle::total 1172134111 # Number of insts commited each cycle +system.cpu.commit.COM:count 1489523295 # Number of instructions committed +system.cpu.commit.COM:loads 402512844 # Number of loads committed system.cpu.commit.COM:membars 51356 # Number of memory barriers committed -system.cpu.commit.COM:refs 569375208 # Number of memory references committed +system.cpu.commit.COM:refs 569360986 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 83489596 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 1489537517 # The number of committed instructions +system.cpu.commit.branchMispredicts 5348299 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1344365389 # The number of squashed insts skipped by commit -system.cpu.committedInsts 1405618374 # Number of Instructions Simulated -system.cpu.committedInsts_total 1405618374 # Number of Instructions Simulated -system.cpu.cpi 1.558505 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.558505 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 428071377 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 13932.868577 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6644.344451 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 427202678 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 12103469000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.002029 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 868699 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 619015 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1658986500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 249684 # number of ReadReq MSHR misses +system.cpu.commit.commitSquashedInsts 219352878 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1405604152 # Number of Instructions Simulated +system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated +system.cpu.cpi 0.855795 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.855795 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 295701747 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 14658.100936 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7465.537350 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 294883428 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 11995002500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002767 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 818319 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 604827 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1593832500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000722 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 213492 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 38071.428571 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35071.428571 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 38214.285714 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35214.285714 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 266500 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 267500 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 245500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 246500 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 14486.830110 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11574.912497 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 165064790 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 25958081664 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.010739 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1791840 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1512123 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 3237699799 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001676 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 279717 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 15552.165643 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12826.834160 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 165080576 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 27468857045 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.010586 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1766240 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1498175 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 3438425299 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001607 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 268065 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1118.737886 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 955.148896 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 594928007 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 14305.954795 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9249.484415 # average overall mshr miss latency -system.cpu.dcache.demand_hits 592267468 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 38061550664 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.004472 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2660539 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2131138 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4896686299 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000890 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 529401 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 462548563 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 15269.088284 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 10449.973314 # average overall mshr miss latency +system.cpu.dcache.demand_hits 459964004 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 39463859545 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005588 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2584559 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2103002 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 5032257799 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.001041 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 481557 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999897 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4095.577700 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 594928007 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 14305.954795 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9249.484415 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999860 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4095.424781 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 462548563 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 15269.088284 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 10449.973314 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 592267468 # number of overall hits -system.cpu.dcache.overall_miss_latency 38061550664 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.004472 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2660539 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2131138 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4896686299 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000890 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 529401 # number of overall MSHR misses +system.cpu.dcache.overall_hits 459964004 # number of overall hits +system.cpu.dcache.overall_miss_latency 39463859545 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005588 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2584559 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2103002 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 5032257799 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.001041 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 481557 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 525312 # number of replacements -system.cpu.dcache.sampled_refs 529408 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 477468 # number of replacements +system.cpu.dcache.sampled_refs 481564 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.577700 # Cycle average of tags in use -system.cpu.dcache.total_refs 592268787 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 165936000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 467492 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 419165001 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 3408944329 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 761736999 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 767859019 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 238675861 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 2897042 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 252577407 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 355041427 # Number of cache lines fetched -system.cpu.fetch.Cycles 1184621367 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 11557522 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 3696750718 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 90055290 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.115297 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 355041427 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 175591574 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.687503 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 2190333922 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.687757 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.837142 # Number of instructions fetched each cycle (Total) +system.cpu.dcache.tagsinuse 4095.424781 # Cycle average of tags in use +system.cpu.dcache.total_refs 459965323 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 132220000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 428419 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 393630434 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 1750728609 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 405694605 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 351105685 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 30409425 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 21703387 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 105812900 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 173095521 # Number of cache lines fetched +system.cpu.fetch.Cycles 548231197 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1429406 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 1760522570 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 6170035 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.087964 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 173095521 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 98804348 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.463554 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1202543536 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.463999 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.699989 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1360754025 62.13% 62.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 248782776 11.36% 73.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 79015111 3.61% 77.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 36736924 1.68% 78.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 85275355 3.89% 82.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 39319900 1.80% 84.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 30979848 1.41% 85.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 19612924 0.90% 86.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 289857059 13.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 827407907 68.80% 68.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 82886631 6.89% 75.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 45822474 3.81% 79.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22740031 1.89% 81.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 33832186 2.81% 84.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 32824396 2.73% 86.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 14991772 1.25% 88.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7935570 0.66% 88.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 134102569 11.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 2190333922 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 355041427 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 33183.081998 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34797.601744 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 355039305 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 70414500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 2122 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 746 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 47881500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1376 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 1202543536 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 173095521 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35040.947075 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35056.370656 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 173093726 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 62898500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1795 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 500 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 45398000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 1295 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 258210.403636 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 133766.403400 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 355041427 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 33183.081998 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34797.601744 # average overall mshr miss latency -system.cpu.icache.demand_hits 355039305 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 70414500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses -system.cpu.icache.demand_misses 2122 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 746 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 47881500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1376 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 173095521 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35040.947075 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35056.370656 # average overall mshr miss latency +system.cpu.icache.demand_hits 173093726 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 62898500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000010 # miss rate for demand accesses +system.cpu.icache.demand_misses 1795 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 500 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 45398000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 1295 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.517160 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1059.143452 # Average occupied blocks per context -system.cpu.icache.overall_accesses 355041427 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 33183.081998 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34797.601744 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.509837 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1044.146064 # Average occupied blocks per context +system.cpu.icache.overall_accesses 173095521 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35040.947075 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35056.370656 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 355039305 # number of overall hits -system.cpu.icache.overall_miss_latency 70414500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses -system.cpu.icache.overall_misses 2122 # number of overall misses -system.cpu.icache.overall_mshr_hits 746 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 47881500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1376 # number of overall MSHR misses +system.cpu.icache.overall_hits 173093726 # number of overall hits +system.cpu.icache.overall_miss_latency 62898500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000010 # miss rate for overall accesses +system.cpu.icache.overall_misses 1795 # number of overall misses +system.cpu.icache.overall_mshr_hits 500 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 45398000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 1295 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 218 # number of replacements -system.cpu.icache.sampled_refs 1375 # Sample count of references to valid blocks. +system.cpu.icache.replacements 158 # number of replacements +system.cpu.icache.sampled_refs 1294 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1059.143452 # Cycle average of tags in use -system.cpu.icache.total_refs 355039305 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1044.146064 # Cycle average of tags in use +system.cpu.icache.total_refs 173093726 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 329014 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 129329311 # Number of branches executed -system.cpu.iew.EXEC:nop 343977069 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.860181 # Inst execution rate -system.cpu.iew.EXEC:refs 750434371 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 206174463 # Number of stores executed +system.cpu.idleCycles 365858 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 89387994 # Number of branches executed +system.cpu.iew.EXEC:nop 102270125 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.226831 # Inst execution rate +system.cpu.iew.EXEC:refs 590482453 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 169844558 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1480496045 # num instructions consuming a value -system.cpu.iew.WB:count 1847584929 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.961963 # average fanout of values written-back +system.cpu.iew.WB:consumers 1212155834 # num instructions consuming a value +system.cpu.iew.WB:count 1472494694 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.958320 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1424182878 # num instructions producing a value -system.cpu.iew.WB:rate 0.843391 # insts written-back per cycle -system.cpu.iew.WB:sent 1859595547 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 91828645 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2291655 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 731683017 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21329829 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 16631995 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 299730608 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2833977471 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 544259908 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 92682608 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1884367319 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 43246 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1161633451 # num instructions producing a value +system.cpu.iew.WB:rate 1.224111 # insts written-back per cycle +system.cpu.iew.WB:sent 1473866323 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 5524573 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2522825 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 468103706 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 2974733 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 4542151 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 188277007 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1708968213 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 420637895 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6158070 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1475767085 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 67059 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 5071 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 238675861 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 70086 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 9806 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 30409425 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 130990 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 28836 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 116166112 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 85848 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 40442 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 124904325 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 7473 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 6831445 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 329165765 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 132872652 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 6831445 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 2781524 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 89047121 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.641641 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.641641 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 832421 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 264 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 65590862 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 21428865 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 832421 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 648511 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 4876062 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.168504 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.168504 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1175590605 59.46% 59.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2994259 0.15% 59.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 570634170 28.86% 88.48% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 227830893 11.52% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 884681338 59.70% 59.70% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.70% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.70% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2618266 0.18% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 423845666 28.60% 88.48% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 170779885 11.52% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1977049927 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 4131140 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.002090 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 1481925155 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 3244981 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.002190 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 148870 3.60% 3.60% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 3.60% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 3.60% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 222262 5.38% 8.98% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 8.98% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 8.98% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 8.98% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 8.98% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 8.98% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 3423281 82.87% 91.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 336727 8.15% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 213199 6.57% 6.57% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 6.57% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 6.57% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 176159 5.43% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 2529934 77.96% 89.96% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 325689 10.04% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 2190333922 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.902625 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.145189 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1202543536 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.232326 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.127768 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 1077130624 49.18% 49.18% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 581443700 26.55% 75.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 301967857 13.79% 89.51% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 159877963 7.30% 96.81% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 45264546 2.07% 98.87% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 18451049 0.84% 99.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 4794612 0.22% 99.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 1273045 0.06% 99.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 130526 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 320551307 26.66% 26.66% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 511598648 42.54% 69.20% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 219310152 18.24% 87.44% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 94899047 7.89% 95.33% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 39949634 3.32% 98.65% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 10701892 0.89% 99.54% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 5167484 0.43% 99.97% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 226814 0.02% 99.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 138558 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 2190333922 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.902489 # Inst issue rate -system.cpu.iq.iqInstsAdded 2468355699 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1977049927 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21644703 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1031033219 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 637277 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 19401032 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1242826340 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 279724 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34530.938042 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31386.377770 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 218618 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2110047500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.218451 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 61106 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1917896000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.218451 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 61106 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 251060 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34076.007326 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.126905 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 217208 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1153541000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.134836 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33852 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1049484000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.134836 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33852 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 467492 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 467492 # number of Writeback hits +system.cpu.iq.ISSUE:issued_per_cycle::total 1202543536 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.231951 # Inst issue rate +system.cpu.iq.iqInstsAdded 1603622713 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1481925155 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 3075375 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 200589396 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 67249 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 831704 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 279090439 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 268080 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.656689 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31319.323632 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 207610 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 2080631000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.225567 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 60470 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893879500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225567 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 60470 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 214779 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34036.266738 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.958285 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 181098 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1146375500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.156817 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33681 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1044278000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156817 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33681 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 428419 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 428419 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 5.866131 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 5.114556 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 530784 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34368.757767 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31249.394469 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 435826 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3263588500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.178901 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 94958 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 482859 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34274.797931 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31206.864505 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 388708 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 3227006500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.194987 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 94151 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2967380000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.178901 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 94958 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 2938157500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.194987 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 94151 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.061469 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.477467 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2014.215255 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15645.646003 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 530784 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34368.757767 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31249.394469 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.060603 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.478382 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1985.832482 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15675.625212 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 482859 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34274.797931 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31206.864505 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 435826 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3263588500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.178901 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 94958 # number of overall misses +system.cpu.l2cache.overall_hits 388708 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3227006500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.194987 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 94151 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2967380000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.178901 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 94958 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 2938157500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.194987 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 94151 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 76745 # number of replacements -system.cpu.l2cache.sampled_refs 92262 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 75917 # number of replacements +system.cpu.l2cache.sampled_refs 91431 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17659.861257 # Cycle average of tags in use -system.cpu.l2cache.total_refs 541221 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 17661.457694 # Cycle average of tags in use +system.cpu.l2cache.total_refs 467629 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 59365 # number of writebacks -system.cpu.memDep0.conflictingLoads 443698156 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 136383139 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 731683017 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 299730608 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 2190662936 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 17189054 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1244779268 # Number of HB maps that are committed -system.cpu.rename.RENAME:FullRegisterEvents 463 # Number of times there has been no free registers -system.cpu.rename.RENAME:IQFullEvents 34257 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 824291881 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 24214806 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 8 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 4869886562 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 3060544953 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2396042530 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 704670101 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 238675861 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 33809858 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1151263262 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 371697167 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 21697179 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 175779479 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21533408 # count of temporary serializing insts renamed -system.cpu.timesIdled 8581 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.l2cache.writebacks 59275 # number of writebacks +system.cpu.memDep0.conflictingLoads 406523725 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 165664801 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 468103706 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 188277007 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 1202909394 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 123850376 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1244770452 # Number of HB maps that are committed +system.cpu.rename.RENAME:FullRegisterEvents 28358883 # Number of times there has been no free registers +system.cpu.rename.RENAME:IQFullEvents 134234500 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 443697356 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 41034725 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 2926103966 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 1732026812 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 1445187078 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 329587648 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 30409425 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 217220624 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 200416626 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 57778107 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 3036469 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 385260528 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 3035800 # count of temporary serializing insts renamed +system.cpu.timesIdled 11398 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- |