diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2010-05-13 23:45:59 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2010-05-13 23:45:59 -0400 |
| commit | e63c73b45d688c7af7a1a3ed01dbde538c57acc2 (patch) | |
| tree | b10b8bbf9dd89f219c5c63ab9d2d745924935425 /tests/long | |
| parent | fc746c2268bfceded0014749cddd8234fa55a35a (diff) | |
| download | gem5-e63c73b45d688c7af7a1a3ed01dbde538c57acc2.tar.xz | |
BPRED: Update regressions for tournament predictor fix.
Diffstat (limited to 'tests/long')
29 files changed, 3733 insertions, 3729 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 474c2633d..80a3274df 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/gzip +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index 223344a8e..e75420ce2 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:02:05 -M5 executing on SC2B0619 +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:52:49 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index b56c75dd6..319df7c1b 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,340 +1,340 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 207071 # Simulator instruction rate (inst/s) -host_mem_usage 192708 # Number of bytes of host memory used -host_seconds 2731.20 # Real time elapsed on the host -host_tick_rate 61173967 # Simulator tick rate (ticks/s) +host_inst_rate 206060 # Simulator instruction rate (inst/s) +host_mem_usage 206972 # Number of bytes of host memory used +host_seconds 2744.60 # Real time elapsed on the host +host_tick_rate 61062862 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated -sim_seconds 0.167078 # Number of seconds simulated -sim_ticks 167078146500 # Number of ticks simulated +sim_seconds 0.167593 # Number of seconds simulated +sim_ticks 167593085500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 65718859 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 73181368 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 4206850 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 70112287 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 76039018 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 63922842 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 71487962 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 180 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 4121924 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 70504427 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 76440051 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1674270 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 17700250 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 18448626 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 322711250 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.865001 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.301723 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 323575021 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.860023 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.297815 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 108088758 33.49% 33.49% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 100475751 31.13% 64.63% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 37367184 11.58% 76.21% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 9733028 3.02% 79.22% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 10676883 3.31% 82.53% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 22147835 6.86% 89.40% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 13251874 4.11% 93.50% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 3269687 1.01% 94.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 17700250 5.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 107931872 33.36% 33.36% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 101513205 31.37% 64.73% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 37265964 11.52% 76.25% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 10166735 3.14% 79.39% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 11290718 3.49% 82.88% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 21721468 6.71% 89.59% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 12702626 3.93% 93.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 2533807 0.78% 94.30% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 18448626 5.70% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 322711250 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 323575021 # Number of insts commited each cycle system.cpu.commit.COM:count 601856963 # Number of instructions committed system.cpu.commit.COM:loads 115049510 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 154862033 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4206223 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 4121096 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 61418165 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 61591802 # The number of squashed insts skipped by commit system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.590849 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.590849 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 113146786 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 19647.173839 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7806.243845 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 112293703 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 16760670000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.007540 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 853083 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 636806 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1688311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001911 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 216277 # number of ReadReq MSHR misses +system.cpu.cpi 0.592670 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.592670 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 4 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 113443216 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 19248.740390 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7746.370369 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 112634831 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 15560393000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007126 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 808385 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 590181 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1690289000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001923 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 218204 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 32801.298408 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35637.649046 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 37121636 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 76416692881 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.059052 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2329685 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1992407 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 12019794995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.008549 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 337278 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6922.723577 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 21318.181818 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 317.179202 # Average number of references to valid blocks. +system.cpu.dcache.WriteReq_avg_miss_latency 32797.392555 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35638.802347 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 37116231 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 76584863381 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.059189 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2335090 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1996724 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 12058958995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.008577 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 338366 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6528.414634 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 21363.636364 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 316.462124 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 123 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 851495 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 234500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 802995 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 235000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 152598107 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 29275.574871 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency -system.cpu.dcache.demand_hits 149415339 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 93177362881 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.020857 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3182768 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2629213 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 13708105995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003628 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 553555 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 152894537 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 29313.182507 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 24703.537731 # average overall mshr miss latency +system.cpu.dcache.demand_hits 149751062 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 92145256381 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.020560 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3143475 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2586905 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 13749247995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003640 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 556570 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999561 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.203417 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 152598107 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 29275.574871 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999563 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.208277 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 152894537 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 29313.182507 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 24703.537731 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 149415339 # number of overall hits -system.cpu.dcache.overall_miss_latency 93177362881 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.020857 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3182768 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2629213 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 13708105995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003628 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 553555 # number of overall MSHR misses +system.cpu.dcache.overall_hits 149751062 # number of overall hits +system.cpu.dcache.overall_miss_latency 92145256381 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.020560 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3143475 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2586905 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 13749247995 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003640 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 556570 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 468828 # number of replacements -system.cpu.dcache.sampled_refs 472924 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 470982 # number of replacements +system.cpu.dcache.sampled_refs 475078 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.203417 # Cycle average of tags in use -system.cpu.dcache.total_refs 150001657 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126581000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 334123 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 49202518 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 654 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4158991 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 689696194 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 144199483 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 123896058 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 9869862 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 2004 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 5413191 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 163077390 # DTB accesses +system.cpu.dcache.tagsinuse 4094.208277 # Cycle average of tags in use +system.cpu.dcache.total_refs 150344193 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126612000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 335213 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 51119249 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 861 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 4177292 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 689843810 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 144051375 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 122990983 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 9853353 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 3386 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 5413414 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 163070578 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 163013880 # DTB hits -system.cpu.dtb.data_misses 63510 # DTB misses +system.cpu.dtb.data_hits 163012019 # DTB hits +system.cpu.dtb.data_misses 58559 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 122284109 # DTB read accesses +system.cpu.dtb.read_accesses 122259759 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 122260496 # DTB read hits -system.cpu.dtb.read_misses 23613 # DTB read misses -system.cpu.dtb.write_accesses 40793281 # DTB write accesses +system.cpu.dtb.read_hits 122237048 # DTB read hits +system.cpu.dtb.read_misses 22711 # DTB read misses +system.cpu.dtb.write_accesses 40810819 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 40753384 # DTB write hits -system.cpu.dtb.write_misses 39897 # DTB write misses -system.cpu.fetch.Branches 76039018 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 66014406 # Number of cache lines fetched -system.cpu.fetch.Cycles 197129335 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1352914 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 698864013 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 4233115 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.227555 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 66014406 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 67411078 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.091429 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 332581112 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.101334 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.065263 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 40774971 # DTB write hits +system.cpu.dtb.write_misses 35848 # DTB write misses +system.cpu.fetch.Branches 76440051 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 65631744 # Number of cache lines fetched +system.cpu.fetch.Cycles 195845469 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1315609 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 699070033 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 4181068 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.228053 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 65631744 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 65597112 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.085617 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 333428374 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.096612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.077342 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 201466223 60.58% 60.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 10360747 3.12% 63.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 15882081 4.78% 68.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 14599006 4.39% 72.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 12362950 3.72% 76.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 14822134 4.46% 81.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 6008311 1.81% 82.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 3307530 0.99% 83.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 53772130 16.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 203214688 60.95% 60.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 10311898 3.09% 64.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 15894466 4.77% 68.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 13958250 4.19% 72.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 12033268 3.61% 76.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 13973782 4.19% 80.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 5916300 1.77% 82.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 3411105 1.02% 83.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 54714617 16.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 332581112 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 66014406 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36214.713430 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35498.337029 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 66013237 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 42335000 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 333428374 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 65631744 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36217.817562 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35518.743109 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 65630571 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 42483500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1169 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 267 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 32019500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 1173 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 266 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 32215500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 907 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 73185.406874 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 72360.056229 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 66014406 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36214.713430 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency -system.cpu.icache.demand_hits 66013237 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 42335000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 65631744 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36217.817562 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35518.743109 # average overall mshr miss latency +system.cpu.icache.demand_hits 65630571 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 42483500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses -system.cpu.icache.demand_misses 1169 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 267 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 32019500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 1173 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 266 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 32215500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 907 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.375881 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 769.803945 # Average occupied blocks per context -system.cpu.icache.overall_accesses 66014406 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36214.713430 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.378038 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 774.221896 # Average occupied blocks per context +system.cpu.icache.overall_accesses 65631744 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36217.817562 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35518.743109 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 66013237 # number of overall hits -system.cpu.icache.overall_miss_latency 42335000 # number of overall miss cycles +system.cpu.icache.overall_hits 65630571 # number of overall hits +system.cpu.icache.overall_miss_latency 42483500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses -system.cpu.icache.overall_misses 1169 # number of overall misses -system.cpu.icache.overall_mshr_hits 267 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 32019500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 1173 # number of overall misses +system.cpu.icache.overall_mshr_hits 266 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 32215500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 907 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 34 # number of replacements -system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks. +system.cpu.icache.replacements 35 # number of replacements +system.cpu.icache.sampled_refs 907 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 769.803945 # Cycle average of tags in use -system.cpu.icache.total_refs 66013237 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 774.221896 # Cycle average of tags in use +system.cpu.icache.total_refs 65630571 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1575182 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 67316859 # Number of branches executed -system.cpu.iew.EXEC:nop 42997381 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.793347 # Inst execution rate -system.cpu.iew.EXEC:refs 164017993 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 41189464 # Number of stores executed +system.cpu.idleCycles 1757798 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 67441684 # Number of branches executed +system.cpu.iew.EXEC:nop 43298534 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.787674 # Inst execution rate +system.cpu.iew.EXEC:refs 164010690 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 41206389 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 487237002 # num instructions consuming a value -system.cpu.iew.WB:count 596051147 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.811465 # average fanout of values written-back +system.cpu.iew.WB:consumers 488922033 # num instructions consuming a value +system.cpu.iew.WB:count 596002683 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.810520 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 395375802 # num instructions producing a value -system.cpu.iew.WB:rate 1.783750 # insts written-back per cycle -system.cpu.iew.WB:sent 597227180 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4671561 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2251979 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 126977202 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3270425 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 43223597 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 663379957 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 122828529 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6459968 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 599258144 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 2443 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 396281024 # num instructions producing a value +system.cpu.iew.WB:rate 1.778124 # insts written-back per cycle +system.cpu.iew.WB:sent 597106328 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4603784 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2069078 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 126900612 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 3145838 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 43054897 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 663551547 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 122804301 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6319339 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 599203767 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 4454 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 34441 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 9869862 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 84552 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 32589 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 9853353 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 86305 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 207 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 9107751 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 14447 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 194 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 8787843 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 12289 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 29567 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5881 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 11927692 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 3411074 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 29567 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 540315 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 4131246 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.692479 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.692479 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 89737 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 5921 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 11851102 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 3242374 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 89737 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 943709 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3660075 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.687279 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.687279 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 438834840 72.45% 72.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 6546 0.00% 72.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 72.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 29 0.00% 72.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 5 0.00% 72.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 72.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 124855453 20.61% 93.06% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 42021230 6.94% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 438810493 72.47% 72.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 6669 0.00% 72.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 72.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 29 0.00% 72.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 5 0.00% 72.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 72.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 124770612 20.61% 93.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 41935289 6.93% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 605718112 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 7232323 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011940 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 605523106 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 7132172 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011779 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 5390831 74.54% 74.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 67 0.00% 74.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 74.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 74.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 74.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 74.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 74.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 74.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 74.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 1490139 20.60% 95.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 351286 4.86% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 5335622 74.81% 74.81% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 49 0.00% 74.81% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 74.81% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 74.81% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 74.81% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 74.81% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 74.81% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 74.81% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 74.81% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 1469402 20.60% 95.41% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 327099 4.59% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 332581112 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.821264 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.674645 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 333428374 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.816052 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.661323 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 92203773 27.72% 27.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 67051353 20.16% 47.88% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 80133780 24.09% 71.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 36043478 10.84% 82.82% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 30084945 9.05% 91.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 14579095 4.38% 96.25% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 10850493 3.26% 99.51% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 1143008 0.34% 99.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 491187 0.15% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 91844434 27.55% 27.55% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 66796624 20.03% 47.58% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 82026036 24.60% 72.18% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 37142853 11.14% 83.32% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 29318508 8.79% 92.11% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 13804488 4.14% 96.25% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 11015283 3.30% 99.56% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 983503 0.29% 99.85% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 496645 0.15% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 332581112 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.812679 # Inst issue rate -system.cpu.iq.iqInstsAdded 620382553 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 605718112 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 53519286 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 12833 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 29313548 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 333428374 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.806528 # Inst issue rate +system.cpu.iq.iqInstsAdded 620252984 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 605523106 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 53278148 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 39411 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 29138505 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 66014446 # ITB accesses +system.cpu.itb.fetch_accesses 65631783 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 66014406 # ITB hits -system.cpu.itb.fetch_misses 40 # ITB misses +system.cpu.itb.fetch_hits 65631744 # ITB hits +system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -343,106 +343,106 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 256647 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34260.342026 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31141.538767 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 8792814000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 256875 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34263.188321 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31137.765450 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 8801356500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 256647 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 7992382500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 256875 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 7998513500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 256647 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 217179 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34303.986479 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31015.630238 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 181383 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1227945500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.164823 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 35796 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1110235500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.164823 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 35796 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 80643 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34136.391255 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31030.684622 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 2752861000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 256875 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 219110 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34284.038279 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31037.107304 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 183268 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1228808500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.163580 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 35842 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1112432000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.163580 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 35842 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 81505 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34131.924422 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31025.814367 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 2781922500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 80643 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2502407500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 81505 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2528759000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 80643 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 334123 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 334123 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5083.333333 # average number of cycles each access was blocked +system.cpu.l2cache.UpgradeReq_mshr_misses 81505 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 335213 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 335213 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5455.882353 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.723010 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 78 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 3.750936 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 68 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 396500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 371000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 473826 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34265.684253 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 181383 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10020759500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.617195 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 292443 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 475985 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34265.741313 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31125.440272 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 183268 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 10030165000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.614971 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 292717 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9102618000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.617195 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 292443 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 9110945500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.614971 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 292717 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.051040 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.447409 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1672.465668 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14660.696789 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 473826 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34265.684253 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.051123 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.447698 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1675.210024 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14670.153699 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 475985 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34265.741313 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31125.440272 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 181383 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10020759500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.617195 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 292443 # number of overall misses +system.cpu.l2cache.overall_hits 183268 # number of overall hits +system.cpu.l2cache.overall_miss_latency 10030165000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.614971 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 292717 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9102618000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.617195 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 292443 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 9110945500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.614971 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 292717 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 85262 # number of replacements -system.cpu.l2cache.sampled_refs 100888 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 85307 # number of replacements +system.cpu.l2cache.sampled_refs 100934 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16333.162457 # Cycle average of tags in use -system.cpu.l2cache.total_refs 375607 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16345.363723 # Cycle average of tags in use +system.cpu.l2cache.total_refs 378597 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 63236 # number of writebacks -system.cpu.memDep0.conflictingLoads 19292303 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 14732751 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 126977202 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 43223597 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 334156294 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 15214853 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 63240 # number of writebacks +system.cpu.memDep0.conflictingLoads 18950859 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15231969 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 126900612 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 43054897 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 335186172 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14808263 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 31587363 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 151899436 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2286618 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 131 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 896816353 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 680424744 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 519473797 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 116400987 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 9869862 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 39195268 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 55618908 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 706 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 77660298 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 26 # count of temporary serializing insts renamed -system.cpu.timesIdled 36534 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 34154270 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 151775927 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2034435 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 82 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 895748431 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 680023810 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 518612424 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 115460168 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 9853353 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 41529646 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 54757535 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 1017 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 33 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 80752072 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 33 # count of temporary serializing insts renamed +system.cpu.timesIdled 42487 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 4a852e5ff..7751f11d1 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/gzip +executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index 23f626d38..0c73642e7 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:11:32 -M5 executing on SC2B0619 +M5 compiled May 12 2010 02:45:56 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:48:22 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -43,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1102659088000 because target called exit() +Exiting @ tick 1088715493000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index e06d74489..74618889d 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,422 +1,422 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 117151 # Simulator instruction rate (inst/s) -host_mem_usage 194316 # Number of bytes of host memory used -host_seconds 11998.32 # Real time elapsed on the host -host_tick_rate 91901100 # Simulator tick rate (ticks/s) +host_inst_rate 141900 # Simulator instruction rate (inst/s) +host_mem_usage 208776 # Number of bytes of host memory used +host_seconds 9905.67 # Real time elapsed on the host +host_tick_rate 109908342 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1405618365 # Number of instructions simulated -sim_seconds 1.102659 # Number of seconds simulated -sim_ticks 1102659088000 # Number of ticks simulated +sim_insts 1405618369 # Number of instructions simulated +sim_seconds 1.088715 # Number of seconds simulated +sim_ticks 1088715493000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 182414509 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 203429498 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 173332559 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 194142411 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 83681535 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 254458061 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 254458061 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 81910123 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 251618660 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 251618660 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 86248929 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 8096109 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 8014877 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1964055004 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.758399 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.188214 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1942378796 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.766863 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.200662 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 1088074201 55.40% 55.40% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 575643784 29.31% 84.71% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 120435541 6.13% 90.84% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 120975798 6.16% 97.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 27955067 1.42% 98.42% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 8084166 0.41% 98.83% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 10447088 0.53% 99.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 4343250 0.22% 99.59% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 8096109 0.41% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 1072972593 55.24% 55.24% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 568760584 29.28% 84.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 118179777 6.08% 90.61% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 122167717 6.29% 96.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 27965504 1.44% 98.34% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 8603273 0.44% 98.78% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 11084471 0.57% 99.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 4630000 0.24% 99.59% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 8014877 0.41% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1964055004 # Number of insts commited each cycle -system.cpu.commit.COM:count 1489537508 # Number of instructions committed -system.cpu.commit.COM:loads 402517243 # Number of loads committed +system.cpu.commit.COM:committed_per_cycle::total 1942378796 # Number of insts commited each cycle +system.cpu.commit.COM:count 1489537512 # Number of instructions committed +system.cpu.commit.COM:loads 402517247 # Number of loads committed system.cpu.commit.COM:membars 51356 # Number of memory barriers committed -system.cpu.commit.COM:refs 569375199 # Number of memory references committed +system.cpu.commit.COM:refs 569375203 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 83681535 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 1489537508 # The number of committed instructions +system.cpu.commit.branchMispredicts 81910123 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 1489537512 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1390237652 # The number of squashed insts skipped by commit -system.cpu.committedInsts 1405618365 # Number of Instructions Simulated -system.cpu.committedInsts_total 1405618365 # Number of Instructions Simulated -system.cpu.cpi 1.568931 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.568931 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 426261934 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14297.662769 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6789.135084 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 425346235 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 13092355500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.002148 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 915699 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 667386 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1685830500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 248313 # number of ReadReq MSHR misses +system.cpu.commit.commitSquashedInsts 1349352602 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1405618369 # Number of Instructions Simulated +system.cpu.committedInsts_total 1405618369 # Number of Instructions Simulated +system.cpu.cpi 1.549091 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.549091 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 421562233 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 14361.598866 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6977.217093 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 420657692 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 12990655000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002146 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 904541 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 666380 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1661701000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000565 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 238161 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 38037.500000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35037.500000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 38025 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35025 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 1521500 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 1521000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 1401500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 1401000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 37763.269313 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36078.327068 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 164634096 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 83930150000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.013320 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2222534 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1870625 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 12696288000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.002109 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 351909 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 37779.329951 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36098.948570 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 164660283 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 82976518000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.013163 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2196347 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1851198 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 12459516000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.002069 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 345149 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1119.158447 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1140.488307 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 593118564 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 30916.284897 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23961.331807 # average overall mshr miss latency -system.cpu.dcache.demand_hits 589980331 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 97022505500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005291 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3138233 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2538011 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 14382118500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.001012 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 600222 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 588418863 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 30948.287394 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 24208.768922 # average overall mshr miss latency +system.cpu.dcache.demand_hits 585317975 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 95967173000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005270 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3100888 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2517578 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 14121217000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000991 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 583310 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999897 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4095.579742 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 593118564 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 30916.284897 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23961.331807 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999896 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4095.574437 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 588418863 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 30948.287394 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 24208.768922 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 589980331 # number of overall hits -system.cpu.dcache.overall_miss_latency 97022505500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005291 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3138233 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2538011 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 14382118500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.001012 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 600222 # number of overall MSHR misses +system.cpu.dcache.overall_hits 585317975 # number of overall hits +system.cpu.dcache.overall_miss_latency 95967173000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005270 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3100888 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2517578 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 14121217000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000991 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 583310 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 523278 # number of replacements -system.cpu.dcache.sampled_refs 527374 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 509323 # number of replacements +system.cpu.dcache.sampled_refs 513419 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.579742 # Cycle average of tags in use -system.cpu.dcache.total_refs 590215067 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 166150000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 348749 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 416443317 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 3435538799 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 762668513 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 782001789 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 239759977 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 2941385 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 254458061 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 354588619 # Number of cache lines fetched -system.cpu.fetch.Cycles 1199300749 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 10659931 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 3732201000 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 88873599 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.115384 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 354588619 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 182414509 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.692364 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 2203814981 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.693518 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.831719 # Number of instructions fetched each cycle (Total) +system.cpu.dcache.tagsinuse 4095.574437 # Cycle average of tags in use +system.cpu.dcache.total_refs 585548366 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 166128000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 341989 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 421912263 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 3394284142 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 753420072 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 764076323 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 233540433 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 2970138 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 251618660 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 350290492 # Number of cache lines fetched +system.cpu.fetch.Cycles 1175688320 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 10057151 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 3685758924 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 87714492 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.115558 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 350290492 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 173332559 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.692710 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 2175919229 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.693886 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.844671 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 1359102894 61.67% 61.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 256500547 11.64% 73.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 81150170 3.68% 76.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 38425919 1.74% 78.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 85384463 3.87% 82.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 41200023 1.87% 84.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 32567288 1.48% 85.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 20688755 0.94% 86.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 288794922 13.10% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 1350521444 62.07% 62.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 247724506 11.38% 73.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 78785496 3.62% 77.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 36714251 1.69% 78.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 82505145 3.79% 82.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 39097939 1.80% 84.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 30045371 1.38% 85.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 19662444 0.90% 86.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 290862633 13.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 2203814981 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 354588619 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 33291.255289 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34798.042059 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 354586492 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 70810500 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 2175919229 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 350290492 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 33351.843100 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34801.230992 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 350288376 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 70572500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 2127 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 748 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 47986500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 2116 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 735 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 48060500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1379 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 1381 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 257319.660377 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 253832.156522 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 354588619 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 33291.255289 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency -system.cpu.icache.demand_hits 354586492 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 70810500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 350290492 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 33351.843100 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34801.230992 # average overall mshr miss latency +system.cpu.icache.demand_hits 350288376 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 70572500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses -system.cpu.icache.demand_misses 2127 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 748 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 47986500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 2116 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 735 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 48060500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1379 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 1381 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.516598 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1057.993144 # Average occupied blocks per context -system.cpu.icache.overall_accesses 354588619 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 33291.255289 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.517203 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1059.231284 # Average occupied blocks per context +system.cpu.icache.overall_accesses 350290492 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 33351.843100 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34801.230992 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 354586492 # number of overall hits -system.cpu.icache.overall_miss_latency 70810500 # number of overall miss cycles +system.cpu.icache.overall_hits 350288376 # number of overall hits +system.cpu.icache.overall_miss_latency 70572500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses -system.cpu.icache.overall_misses 2127 # number of overall misses -system.cpu.icache.overall_mshr_hits 748 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 47986500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 2116 # number of overall misses +system.cpu.icache.overall_mshr_hits 735 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 48060500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1379 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 1381 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 222 # number of replacements -system.cpu.icache.sampled_refs 1378 # Sample count of references to valid blocks. +system.cpu.icache.replacements 223 # number of replacements +system.cpu.icache.sampled_refs 1380 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1057.993144 # Cycle average of tags in use -system.cpu.icache.total_refs 354586492 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1059.231284 # Cycle average of tags in use +system.cpu.icache.total_refs 350288376 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1503196 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 128154505 # Number of branches executed -system.cpu.iew.EXEC:nop 351416641 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.859194 # Inst execution rate -system.cpu.iew.EXEC:refs 749485536 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 207432555 # Number of stores executed +system.cpu.idleCycles 1511758 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 126596313 # Number of branches executed +system.cpu.iew.EXEC:nop 341046394 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.865157 # Inst execution rate +system.cpu.iew.EXEC:refs 745176720 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 207345254 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1490113215 # num instructions consuming a value -system.cpu.iew.WB:count 1862924801 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.963395 # average fanout of values written-back +system.cpu.iew.WB:consumers 1478969218 # num instructions consuming a value +system.cpu.iew.WB:count 1850021692 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.963149 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1435567297 # num instructions producing a value -system.cpu.iew.WB:rate 0.844742 # insts written-back per cycle -system.cpu.iew.WB:sent 1872447487 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 91815044 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 3100855 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 743909112 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21390967 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 17059392 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 301399339 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2879831174 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 542052981 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 94512444 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1894795217 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 42359 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1424467072 # num instructions producing a value +system.cpu.iew.WB:rate 0.849635 # insts written-back per cycle +system.cpu.iew.WB:sent 1860023576 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 88314915 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 3103548 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 732453281 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21345324 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 16485503 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 296886262 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2838946953 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 537831466 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 95847914 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1883819308 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 43195 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 9892 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 239759977 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 75722 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 9926 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 233540433 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 76384 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 115767211 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 47414 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 116246750 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 24118 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 5474059 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 341391869 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 134541383 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 5474059 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1481544 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 90333500 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.637377 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.637377 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 6075012 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 20 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 329936034 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 130028306 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 6075012 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2827686 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 85487229 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.645540 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.645540 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1186637129 59.65% 59.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2990803 0.15% 59.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 571681967 28.74% 88.54% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 227997762 11.46% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1178571095 59.53% 59.53% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2996630 0.15% 59.69% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.69% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.69% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.69% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.69% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.69% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 570412087 28.81% 88.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 227687410 11.50% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1989307661 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 4014627 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.002018 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 1979667222 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 5110932 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.002582 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 142220 3.54% 3.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 3.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 3.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 232755 5.80% 9.34% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 9.34% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 9.34% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 9.34% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 9.34% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 9.34% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 3328922 82.92% 92.26% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 310730 7.74% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 148685 2.91% 2.91% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.91% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.91% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 233686 4.57% 7.48% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.48% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.48% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.48% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.48% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.48% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 4411963 86.32% 93.81% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 316598 6.19% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 2203814981 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.902665 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.144866 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 2175919229 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.909807 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.157368 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 1083881876 49.18% 49.18% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 586425801 26.61% 75.79% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 298714420 13.55% 89.35% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 164995038 7.49% 96.83% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 47215803 2.14% 98.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 14943143 0.68% 99.65% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 6716019 0.30% 99.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 790183 0.04% 99.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 132698 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 1068255963 49.09% 49.09% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 579314637 26.62% 75.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 292421261 13.44% 89.16% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 161809686 7.44% 96.59% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 50369072 2.31% 98.91% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 14937591 0.69% 99.60% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 7897011 0.36% 99.96% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 777368 0.04% 99.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 136640 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 2203814981 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.902050 # Inst issue rate -system.cpu.iq.iqInstsAdded 2506731488 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1989307661 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21683045 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1079315429 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 646014 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 19439374 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1293054156 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 279061 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34294.562838 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31161.514866 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 9570275000 # number of ReadExReq miss cycles +system.cpu.iq.ISSUE:issued_per_cycle::total 2175919229 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.909176 # Inst issue rate +system.cpu.iq.iqInstsAdded 2476265906 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1979667222 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21634653 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 1050976502 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1545941 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 19390982 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1261656908 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 275258 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34298.440009 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31164.934352 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 9440920000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 279061 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 8695963500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 275258 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 8578397500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 279061 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 249692 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34106.857257 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.384760 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 214678 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1194217500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.140229 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 35014 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1085517500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.140229 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 35014 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 72896 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34203.262182 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31019.788466 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 2493281000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 275258 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 239542 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34105.753589 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.482948 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 204503 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1195031500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.146275 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 35039 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1086296000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146275 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 35039 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 69939 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34214.100859 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31021.876206 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 2392900000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 72896 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2261218500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 69939 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2169639000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 72896 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 348749 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 348749 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 69939 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 341989 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 341989 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.234507 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.064673 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 528753 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34273.636870 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31143.774576 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 214678 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10764492500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.593992 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 314075 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 514800 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34276.681695 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31146.590202 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 204503 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 10635951500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.602753 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 310297 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9781481000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.593992 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 314075 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 9664693500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.602753 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 310297 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.055938 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.444640 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1832.969770 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14569.950583 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 528753 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34273.636870 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31143.774576 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.056082 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.444448 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1837.702550 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14563.687199 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 514800 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34276.681695 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31146.590202 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 214678 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10764492500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.593992 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 314075 # number of overall misses +system.cpu.l2cache.overall_hits 204503 # number of overall hits +system.cpu.l2cache.overall_miss_latency 10635951500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.602753 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 310297 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9781481000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.593992 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 314075 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 9664693500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.602753 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 310297 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 84499 # number of replacements -system.cpu.l2cache.sampled_refs 99950 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 84514 # number of replacements +system.cpu.l2cache.sampled_refs 99965 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16402.920353 # Cycle average of tags in use -system.cpu.l2cache.total_refs 423239 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16401.389748 # Cycle average of tags in use +system.cpu.l2cache.total_refs 406325 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61948 # number of writebacks -system.cpu.memDep0.conflictingLoads 460341314 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 141106002 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 301399339 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 2205318177 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 17694861 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1244779250 # Number of HB maps that are committed -system.cpu.rename.RENAME:FullRegisterEvents 863 # Number of times there has been no free registers -system.cpu.rename.RENAME:IQFullEvents 27117 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 826425901 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 23298995 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 7 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 4917191691 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 3093611594 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2420068259 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 717791884 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 239759977 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 32521130 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1175289009 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 369621228 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 21984761 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 170791702 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21775082 # count of temporary serializing insts renamed -system.cpu.timesIdled 43184 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.l2cache.writebacks 61949 # number of writebacks +system.cpu.memDep0.conflictingLoads 446168372 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 144446189 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 732453281 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 296886262 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 2177430987 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 18705831 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1244779258 # Number of HB maps that are committed +system.cpu.rename.RENAME:FullRegisterEvents 818 # Number of times there has been no free registers +system.cpu.rename.RENAME:IQFullEvents 29460 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 816810065 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 24399902 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 4 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 4857699412 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 3052479029 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2393152182 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 700108886 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 233540433 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 34052536 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1148372924 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 372701478 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 21719371 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 176909620 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21553732 # count of temporary serializing insts renamed +system.cpu.timesIdled 44523 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 803aca1ba..035a139c8 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux mem_mode=timing -pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -660,7 +660,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -680,7 +680,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -806,7 +806,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr index f51a48835..cde3a8c1f 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr @@ -2,6 +2,6 @@ warn: Sockets disabled, not accepting terminal connections For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: 125740500: Trying to launch CPU number 1! +warn: 125751000: Trying to launch CPU number 1! For more information see: http://www.m5sim.org/warn/8f7d2563 hack: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index dc5374eea..fa47c5c0e 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:13:04 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 24 2010 23:13:11 -M5 executing on SC2B0619 +M5 compiled May 12 2010 02:36:15 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:36:17 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1907705384500 because m5_exit instruction encountered +Exiting @ tick 1907689250500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 5561f4961..3e4d779fa 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,447 +1,447 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 126888 # Simulator instruction rate (inst/s) -host_mem_usage 280000 # Number of bytes of host memory used -host_seconds 442.84 # Real time elapsed on the host -host_tick_rate 4307932213 # Simulator tick rate (ticks/s) +host_inst_rate 123563 # Simulator instruction rate (inst/s) +host_mem_usage 293920 # Number of bytes of host memory used +host_seconds 454.60 # Real time elapsed on the host +host_tick_rate 4196424819 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 56190549 # Number of instructions simulated -sim_seconds 1.907705 # Number of seconds simulated -sim_ticks 1907705384500 # Number of ticks simulated +sim_insts 56171530 # Number of instructions simulated +sim_seconds 1.907689 # Number of seconds simulated +sim_ticks 1907689250500 # Number of ticks simulated system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.BTBHits 4976194 # Number of BTB hits -system.cpu0.BPredUnit.BTBLookups 9270305 # Number of BTB lookups -system.cpu0.BPredUnit.RASInCorrect 24350 # Number of incorrect RAS predictions. -system.cpu0.BPredUnit.condIncorrect 550496 # Number of conditional branches incorrect -system.cpu0.BPredUnit.condPredicted 8475185 # Number of conditional branches predicted -system.cpu0.BPredUnit.lookups 10093433 # Number of BP lookups -system.cpu0.BPredUnit.usedRAS 690374 # Number of times the RAS was used to get a target. -system.cpu0.commit.COM:branches 5979895 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 670392 # number cycles where commit BW limit reached +system.cpu0.BPredUnit.BTBHits 5124021 # Number of BTB hits +system.cpu0.BPredUnit.BTBLookups 9548324 # Number of BTB lookups +system.cpu0.BPredUnit.RASInCorrect 25931 # Number of incorrect RAS predictions. +system.cpu0.BPredUnit.condIncorrect 576265 # Number of conditional branches incorrect +system.cpu0.BPredUnit.condPredicted 8953132 # Number of conditional branches predicted +system.cpu0.BPredUnit.lookups 10665388 # Number of BP lookups +system.cpu0.BPredUnit.usedRAS 730260 # Number of times the RAS was used to get a target. +system.cpu0.commit.COM:branches 6306789 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 727470 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.COM:committed_per_cycle::samples 69432713 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::mean 0.574171 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::stdev 1.330726 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::samples 73665183 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::mean 0.571097 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::stdev 1.330919 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::0-1 52133999 75.09% 75.09% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::1-2 7662367 11.04% 86.12% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::2-3 4443977 6.40% 92.52% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::3-4 2023862 2.91% 95.44% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::4-5 1473823 2.12% 97.56% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::5-6 453845 0.65% 98.21% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::6-7 276436 0.40% 98.61% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::7-8 294012 0.42% 99.03% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::8 670392 0.97% 100.00% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::0-1 55454240 75.28% 75.28% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::1-2 8064036 10.95% 86.23% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::2-3 4660922 6.33% 92.55% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::3-4 2129949 2.89% 95.44% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::4-5 1559149 2.12% 97.56% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::5-6 477103 0.65% 98.21% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::6-7 293859 0.40% 98.61% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::7-8 298455 0.41% 99.01% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::8 727470 0.99% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::total 69432713 # Number of insts commited each cycle -system.cpu0.commit.COM:count 39866260 # Number of instructions committed -system.cpu0.commit.COM:loads 6404474 # Number of loads committed -system.cpu0.commit.COM:membars 151021 # Number of memory barriers committed -system.cpu0.commit.COM:refs 10831640 # Number of memory references committed +system.cpu0.commit.COM:committed_per_cycle::total 73665183 # Number of insts commited each cycle +system.cpu0.commit.COM:count 42069937 # Number of instructions committed +system.cpu0.commit.COM:loads 6784715 # Number of loads committed +system.cpu0.commit.COM:membars 161083 # Number of memory barriers committed +system.cpu0.commit.COM:refs 11506692 # Number of memory references committed system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.branchMispredicts 524450 # The number of times a branch was mispredicted -system.cpu0.commit.commitCommittedInsts 39866260 # The number of committed instructions -system.cpu0.commit.commitNonSpecStalls 458375 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 6218733 # The number of squashed insts skipped by commit -system.cpu0.committedInsts 37660679 # Number of Instructions Simulated -system.cpu0.committedInsts_total 37660679 # Number of Instructions Simulated -system.cpu0.cpi 2.679241 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.679241 # CPI: Total CPI of All Threads -system.cpu0.dcache.LoadLockedReq_accesses::0 147686 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 147686 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15414.654688 # average LoadLockedReq miss latency +system.cpu0.commit.branchMispredicts 548150 # The number of times a branch was mispredicted +system.cpu0.commit.commitCommittedInsts 42069937 # The number of committed instructions +system.cpu0.commit.commitNonSpecStalls 486094 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.commitSquashedInsts 6570892 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 39732534 # Number of Instructions Simulated +system.cpu0.committedInsts_total 39732534 # Number of Instructions Simulated +system.cpu0.cpi 2.659989 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.659989 # CPI: Total CPI of All Threads +system.cpu0.dcache.LoadLockedReq_accesses::0 157022 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157022 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15337.494650 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11879.766663 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits::0 135219 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 135219 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 192174500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.084416 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses::0 12467 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 12467 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_mshr_hits 3210 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 109971000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.062680 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11734.631539 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits::0 143004 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 143004 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 215001000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.089274 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses::0 14018 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 14018 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_hits 3542 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 122932000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.066717 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 9257 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses::0 6414671 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6414671 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency::0 28975.322669 # average ReadReq miss latency +system.cpu0.dcache.LoadLockedReq_mshr_misses 10476 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses::0 6796922 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6796922 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency::0 28045.834026 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 28717.577320 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27628.067292 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits::0 5468114 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5468114 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 27426794500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate::0 0.147561 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses::0 946557 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 946557 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 250848 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 19979077000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.108456 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_hits::0 5780701 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5780701 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 28500765500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate::0 0.149512 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses::0 1016221 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1016221 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 272772 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 20540059000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.109380 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 695709 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 639862500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses::0 156551 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 156551 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 54668.039693 # average StoreCondReq miss latency +system.cpu0.dcache.ReadReq_mshr_misses 743449 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 639143000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses::0 165236 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 165236 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 54890.406800 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51668.039693 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits::0 140528 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 140528 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 875946000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.102350 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses::0 16023 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 16023 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 827877000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.102350 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51890.406800 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits::0 147119 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 147119 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 994449500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.109643 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses::0 18117 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18117 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 940098500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.109643 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 16023 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses::0 4258061 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4258061 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency::0 48857.609099 # average WriteReq miss latency +system.cpu0.dcache.StoreCondReq_mshr_misses 18117 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses::0 4544003 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4544003 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency::0 48917.848661 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53930.542507 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 54316.339615 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits::0 2612712 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 2612712 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 80387818274 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate::0 0.386408 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses::0 1645349 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1645349 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_hits 1362208 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 15269947736 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.066495 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_hits::0 2781940 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 2781940 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 86196331165 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate::0 0.387778 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses::0 1762063 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1762063 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_hits 1458631 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_miss_latency 16481315562 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.066776 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 283141 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1050789497 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9307.081114 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 16250 # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 9.224233 # Average number of references to valid blocks. -system.cpu0.dcache.blocked::no_mshrs 116343 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_mshrs 1082813738 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 32500 # number of cycles access was blocked +system.cpu0.dcache.WriteReq_mshr_misses 303432 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1049908497 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9537.404034 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 9.143990 # Average number of references to valid blocks. +system.cpu0.dcache.blocked::no_mshrs 120871 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 1152795563 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses::0 10672732 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::0 11340925 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10672732 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency::0 41596.652338 # average overall miss latency +system.cpu0.dcache.demand_accesses::total 11340925 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency::0 41283.431307 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 36010.649983 # average overall mshr miss latency -system.cpu0.dcache.demand_hits::0 8080826 # number of demand (read+write) hits +system.cpu0.dcache.demand_avg_mshr_miss_latency 35363.498394 # average overall mshr miss latency +system.cpu0.dcache.demand_hits::0 8562641 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8080826 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 107814612774 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate::0 0.242853 # miss rate for demand accesses +system.cpu0.dcache.demand_hits::total 8562641 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 114697096665 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate::0 0.244979 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.demand_misses::0 2591906 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::0 2778284 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2591906 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 1613056 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 35249024736 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate::0 0.091715 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_misses::total 2778284 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 1731403 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 37021374562 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate::0 0.092310 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 978850 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses 1046881 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.863629 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 442.178159 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses::0 10672732 # number of overall (read+write) accesses +system.cpu0.dcache.occ_%::0 0.870622 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 445.758667 # Average occupied blocks per context +system.cpu0.dcache.overall_accesses::0 11340925 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10672732 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency::0 41596.652338 # average overall miss latency +system.cpu0.dcache.overall_accesses::total 11340925 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency::0 41283.431307 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 36010.649983 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 35363.498394 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits::0 8080826 # number of overall hits +system.cpu0.dcache.overall_hits::0 8562641 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 8080826 # number of overall hits -system.cpu0.dcache.overall_miss_latency 107814612774 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate::0 0.242853 # miss rate for overall accesses +system.cpu0.dcache.overall_hits::total 8562641 # number of overall hits +system.cpu0.dcache.overall_miss_latency 114697096665 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate::0 0.244979 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.overall_misses::0 2591906 # number of overall misses +system.cpu0.dcache.overall_misses::0 2778284 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 2591906 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 1613056 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 35249024736 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate::0 0.091715 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_misses::total 2778284 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 1731403 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 37021374562 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate::0 0.092310 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 978850 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 1690651997 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_misses 1046881 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 1689051497 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.replacements 922726 # number of replacements -system.cpu0.dcache.sampled_refs 923123 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 987239 # number of replacements +system.cpu0.dcache.sampled_refs 987751 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 442.178159 # Cycle average of tags in use -system.cpu0.dcache.total_refs 8515102 # Total number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 297339 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 33638519 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:BranchMispred 26518 # Number of times decode detected a branch misprediction -system.cpu0.decode.DECODE:BranchResolved 401378 # Number of times decode resolved a branch -system.cpu0.decode.DECODE:DecodedInsts 50930123 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 25726073 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 9143955 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 1094070 # Number of cycles decode is squashing -system.cpu0.decode.DECODE:SquashedInsts 84180 # Number of squashed instructions handled by decode -system.cpu0.decode.DECODE:UnblockCycles 924165 # Number of cycles decode is unblocking -system.cpu0.dtb.data_accesses 812672 # DTB accesses -system.cpu0.dtb.data_acv 801 # DTB access violations -system.cpu0.dtb.data_hits 11625422 # DTB hits -system.cpu0.dtb.data_misses 28525 # DTB misses +system.cpu0.dcache.tagsinuse 445.758667 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9031985 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 21394000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 319854 # number of writebacks +system.cpu0.decode.DECODE:BlockedCycles 35782513 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:BranchMispred 28650 # Number of times decode detected a branch misprediction +system.cpu0.decode.DECODE:BranchResolved 428056 # Number of times decode resolved a branch +system.cpu0.decode.DECODE:DecodedInsts 53705173 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 27333196 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 9585932 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 1147003 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:SquashedInsts 91050 # Number of squashed instructions handled by decode +system.cpu0.decode.DECODE:UnblockCycles 963541 # Number of cycles decode is unblocking +system.cpu0.dtb.data_accesses 873282 # DTB accesses +system.cpu0.dtb.data_acv 817 # DTB access violations +system.cpu0.dtb.data_hits 12339819 # DTB hits +system.cpu0.dtb.data_misses 31654 # DTB misses system.cpu0.dtb.fetch_accesses 0 # ITB accesses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.read_accesses 605265 # DTB read accesses -system.cpu0.dtb.read_acv 596 # DTB read access violations -system.cpu0.dtb.read_hits 7063658 # DTB read hits -system.cpu0.dtb.read_misses 24056 # DTB read misses -system.cpu0.dtb.write_accesses 207407 # DTB write accesses -system.cpu0.dtb.write_acv 205 # DTB write access violations -system.cpu0.dtb.write_hits 4561764 # DTB write hits -system.cpu0.dtb.write_misses 4469 # DTB write misses -system.cpu0.fetch.Branches 10093433 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 6456937 # Number of cache lines fetched -system.cpu0.fetch.Cycles 16710986 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 292610 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 52006541 # Number of instructions fetch has processed -system.cpu0.fetch.MiscStallCycles 347 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.SquashCycles 660337 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.100032 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 6456937 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 5666568 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 0.515416 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist::samples 70526783 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.737401 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.023896 # Number of instructions fetched each cycle (Total) +system.cpu0.dtb.read_accesses 648811 # DTB read accesses +system.cpu0.dtb.read_acv 602 # DTB read access violations +system.cpu0.dtb.read_hits 7477600 # DTB read hits +system.cpu0.dtb.read_misses 25745 # DTB read misses +system.cpu0.dtb.write_accesses 224471 # DTB write accesses +system.cpu0.dtb.write_acv 215 # DTB write access violations +system.cpu0.dtb.write_hits 4862219 # DTB write hits +system.cpu0.dtb.write_misses 5909 # DTB write misses +system.cpu0.fetch.Branches 10665388 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 6760263 # Number of cache lines fetched +system.cpu0.fetch.Cycles 17500096 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 314893 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 54825819 # Number of instructions fetch has processed +system.cpu0.fetch.MiscStallCycles 926 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.SquashCycles 690026 # Number of cycles fetch has spent squashing +system.cpu0.fetch.branchRate 0.100914 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 6760263 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 5854281 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 0.518751 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::samples 74812186 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.732846 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.023907 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0-1 60303519 85.50% 85.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1-2 761816 1.08% 86.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2-3 1433855 2.03% 88.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3-4 636077 0.90% 89.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4-5 2329701 3.30% 92.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5-6 474692 0.67% 93.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6-7 552515 0.78% 94.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7-8 815434 1.16% 95.44% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3219174 4.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0-1 64104390 85.69% 85.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1-2 792685 1.06% 86.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2-3 1475450 1.97% 88.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3-4 663490 0.89% 89.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4-5 2416214 3.23% 92.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5-6 489674 0.65% 93.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6-7 557514 0.75% 94.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7-8 868698 1.16% 95.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3444071 4.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 70526783 # Number of instructions fetched each cycle (Total) -system.cpu0.icache.ReadReq_accesses::0 6456937 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6456937 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency::0 15194.125887 # average ReadReq miss latency +system.cpu0.fetch.rateDist::total 74812186 # Number of instructions fetched each cycle (Total) +system.cpu0.icache.ReadReq_accesses::0 6760263 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6760263 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency::0 15111.361670 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.650508 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits::0 5806694 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5806694 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 9879873999 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate::0 0.100705 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses::0 650243 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 650243 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 29877 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 7526063499 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.096077 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12055.592401 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits::0 6055842 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6055842 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 10644760499 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate::0 0.104200 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses::0 704421 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 704421 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_hits 31973 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 8106758999 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.099471 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 620366 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11808.794118 # average number of cycles each access was blocked +system.cpu0.icache.ReadReq_mshr_misses 672448 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11292.658537 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 9.361634 # Average number of references to valid blocks. -system.cpu0.icache.blocked::no_mshrs 34 # number of cycles access was blocked +system.cpu0.icache.avg_refs 9.007622 # Average number of references to valid blocks. +system.cpu0.icache.blocked::no_mshrs 41 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_mshrs 401499 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 462999 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses::0 6456937 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::0 6760263 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6456937 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency::0 15194.125887 # average overall miss latency +system.cpu0.icache.demand_accesses::total 6760263 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency::0 15111.361670 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 12131.650508 # average overall mshr miss latency -system.cpu0.icache.demand_hits::0 5806694 # number of demand (read+write) hits +system.cpu0.icache.demand_avg_mshr_miss_latency 12055.592401 # average overall mshr miss latency +system.cpu0.icache.demand_hits::0 6055842 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5806694 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 9879873999 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate::0 0.100705 # miss rate for demand accesses +system.cpu0.icache.demand_hits::total 6055842 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 10644760499 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate::0 0.104200 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.demand_misses::0 650243 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::0 704421 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 650243 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 29877 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 7526063499 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate::0 0.096077 # mshr miss rate for demand accesses +system.cpu0.icache.demand_misses::total 704421 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 31973 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 8106758999 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate::0 0.099471 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 620366 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses 672448 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.995760 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 509.829037 # Average occupied blocks per context -system.cpu0.icache.overall_accesses::0 6456937 # number of overall (read+write) accesses +system.cpu0.icache.occ_%::0 0.995774 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 509.836147 # Average occupied blocks per context +system.cpu0.icache.overall_accesses::0 6760263 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6456937 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency::0 15194.125887 # average overall miss latency +system.cpu0.icache.overall_accesses::total 6760263 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency::0 15111.361670 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 12131.650508 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12055.592401 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits::0 5806694 # number of overall hits +system.cpu0.icache.overall_hits::0 6055842 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 5806694 # number of overall hits -system.cpu0.icache.overall_miss_latency 9879873999 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate::0 0.100705 # miss rate for overall accesses +system.cpu0.icache.overall_hits::total 6055842 # number of overall hits +system.cpu0.icache.overall_miss_latency 10644760499 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate::0 0.104200 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.overall_misses::0 650243 # number of overall misses +system.cpu0.icache.overall_misses::0 704421 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 650243 # number of overall misses -system.cpu0.icache.overall_mshr_hits 29877 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 7526063499 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate::0 0.096077 # mshr miss rate for overall accesses +system.cpu0.icache.overall_misses::total 704421 # number of overall misses +system.cpu0.icache.overall_mshr_hits 31973 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 8106758999 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate::0 0.099471 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 620366 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses 672448 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 619753 # number of replacements -system.cpu0.icache.sampled_refs 620265 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 671790 # number of replacements +system.cpu0.icache.sampled_refs 672302 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 509.829037 # Cycle average of tags in use -system.cpu0.icache.total_refs 5806694 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 25308080000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tagsinuse 509.836147 # Cycle average of tags in use +system.cpu0.icache.total_refs 6055842 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 25289603000 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idleCycles 30375240 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.EXEC:branches 6436261 # Number of branches executed -system.cpu0.iew.EXEC:nop 2512857 # number of nop insts executed -system.cpu0.iew.EXEC:rate 0.402648 # Inst execution rate -system.cpu0.iew.EXEC:refs 11740586 # number of memory reference insts executed -system.cpu0.iew.EXEC:stores 4575950 # Number of stores executed +system.cpu0.idleCycles 30875932 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 6794464 # Number of branches executed +system.cpu0.iew.EXEC:nop 2650714 # number of nop insts executed +system.cpu0.iew.EXEC:rate 0.405657 # Inst execution rate +system.cpu0.iew.EXEC:refs 12475412 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 4878585 # Number of stores executed system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 24161341 # num instructions consuming a value -system.cpu0.iew.WB:count 40226053 # cumulative count of insts written-back -system.cpu0.iew.WB:fanout 0.779058 # average fanout of values written-back +system.cpu0.iew.WB:consumers 25547065 # num instructions consuming a value +system.cpu0.iew.WB:count 42445288 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.775506 # average fanout of values written-back system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 18823082 # num instructions producing a value -system.cpu0.iew.WB:rate 0.398664 # insts written-back per cycle -system.cpu0.iew.WB:sent 40293911 # cumulative count of insts sent to commit -system.cpu0.iew.branchMispredicts 568843 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewBlockCycles 7178019 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 7553743 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 1229599 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 771955 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 4836003 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 46191057 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 7164636 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 359402 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 40627967 # Number of executed instructions -system.cpu0.iew.iewIQFullEvents 33758 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.WB:producers 19811901 # num instructions producing a value +system.cpu0.iew.WB:rate 0.401609 # insts written-back per cycle +system.cpu0.iew.WB:sent 42518285 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 591859 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewBlockCycles 7490199 # Number of cycles IEW is blocking +system.cpu0.iew.iewDispLoadInsts 8008916 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 1306307 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispSquashedInsts 773924 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispStoreInsts 5151785 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 48752960 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 7596827 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 385648 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 42873082 # Number of executed instructions +system.cpu0.iew.iewIQFullEvents 34285 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewLSQFullEvents 4184 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 1094070 # Number of cycles IEW is squashing -system.cpu0.iew.iewUnblockCycles 453368 # Number of cycles IEW is unblocking +system.cpu0.iew.iewLSQFullEvents 4894 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1147003 # Number of cycles IEW is squashing +system.cpu0.iew.iewUnblockCycles 462624 # Number of cycles IEW is unblocking system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread.0.cacheBlocked 243041 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 357779 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread.0.ignoredResponses 8886 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread.0.cacheBlocked 256589 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread.0.forwLoads 371728 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.ignoredResponses 8138 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 34087 # Number of memory ordering violations -system.cpu0.iew.lsq.thread.0.rescheduledLoads 12236 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 1149269 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 408837 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 34087 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 255799 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.predictedTakenIncorrect 313044 # Number of branches that were predicted taken incorrectly -system.cpu0.ipc 0.373240 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.373240 # IPC: Total IPC of All Threads -system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3326 0.01% 0.01% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntAlu 28267868 68.97% 68.98% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntMult 42211 0.10% 69.08% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 12076 0.03% 69.11% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1657 0.00% 69.11% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemRead 7398159 18.05% 87.16% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemWrite 4612021 11.25% 98.41% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IprAccess 650051 1.59% 100.00% # Type of FU issued +system.cpu0.iew.lsq.thread.0.memOrderViolation 36722 # Number of memory ordering violations +system.cpu0.iew.lsq.thread.0.rescheduledLoads 12836 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread.0.squashedLoads 1224201 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 429808 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 36722 # Number of memory order violations +system.cpu0.iew.predictedNotTakenIncorrect 290524 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 301335 # Number of branches that were predicted taken incorrectly +system.cpu0.ipc 0.375941 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.375941 # IPC: Total IPC of All Threads +system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntAlu 29744442 68.76% 68.77% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntMult 44172 0.10% 68.87% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 13702 0.03% 68.90% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.90% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.90% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.90% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1883 0.00% 68.91% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.91% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemRead 7844859 18.13% 87.04% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemWrite 4914921 11.36% 98.40% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IprAccess 690973 1.60% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::total 40987369 # Type of FU issued -system.cpu0.iq.ISSUE:fu_busy_cnt 290458 # FU busy when requested -system.cpu0.iq.ISSUE:fu_busy_rate 0.007087 # FU busy rate (busy events/executed inst) +system.cpu0.iq.ISSUE:FU_type_0::total 43258732 # Type of FU issued +system.cpu0.iq.ISSUE:fu_busy_cnt 310534 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_rate 0.007179 # FU busy rate (busy events/executed inst) system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntAlu 33502 11.53% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemRead 185621 63.91% 75.44% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemWrite 71335 24.56% 100.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntAlu 34104 10.98% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemRead 200961 64.71% 75.70% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemWrite 75469 24.30% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:issued_per_cycle::samples 70526783 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.581160 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.133092 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::samples 74812186 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.578231 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.135171 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::0-1 49764700 70.56% 70.56% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::1-2 10507721 14.90% 85.46% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::2-3 4625277 6.56% 92.02% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::3-4 2839073 4.03% 96.04% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::4-5 1729944 2.45% 98.50% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::5-6 663617 0.94% 99.44% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::6-7 315224 0.45% 99.88% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::7-8 67146 0.10% 99.98% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::8 14081 0.02% 100.00% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::0-1 52955077 70.78% 70.78% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::1-2 11074556 14.80% 85.59% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::2-3 4848896 6.48% 92.07% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::3-4 2948908 3.94% 96.01% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::4-5 1827398 2.44% 98.45% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::5-6 727506 0.97% 99.43% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::6-7 332197 0.44% 99.87% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::7-8 81828 0.11% 99.98% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::8 15820 0.02% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::total 70526783 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:rate 0.406210 # Inst issue rate -system.cpu0.iq.iqInstsAdded 42280479 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 40987369 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 1397721 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 5737875 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedInstsIssued 23380 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 939346 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 3058582 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.ISSUE:issued_per_cycle::total 74812186 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:rate 0.409306 # Inst issue rate +system.cpu0.iq.iqInstsAdded 44617182 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 43258732 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 1485064 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 6087251 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedInstsIssued 24441 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedNonSpecRemoved 998970 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 3229124 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_hits 0 # DTB hits system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.fetch_accesses 875811 # ITB accesses -system.cpu0.itb.fetch_acv 900 # ITB acv -system.cpu0.itb.fetch_hits 845925 # ITB hits -system.cpu0.itb.fetch_misses 29886 # ITB misses +system.cpu0.itb.fetch_accesses 930014 # ITB accesses +system.cpu0.itb.fetch_acv 893 # ITB acv +system.cpu0.itb.fetch_hits 898869 # ITB hits +system.cpu0.itb.fetch_misses 31145 # ITB misses system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.read_acv 0 # DTB read access violations system.cpu0.itb.read_hits 0 # DTB read hits @@ -452,551 +452,549 @@ system.cpu0.itb.write_hits 0 # DT system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wripir 96 0.07% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2410 1.86% 1.94% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.04% 1.98% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.01% 1.98% # number of callpals executed -system.cpu0.kern.callpal::swpipl 116005 89.53% 91.51% # number of callpals executed -system.cpu0.kern.callpal::rdps 6357 4.91% 96.41% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.41% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.42% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.42% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.42% # number of callpals executed -system.cpu0.kern.callpal::rti 4116 3.18% 99.60% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.29% 99.90% # number of callpals executed -system.cpu0.kern.callpal::imb 136 0.10% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 129578 # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2652 1.92% 1.99% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.04% 2.03% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.01% 2.04% # number of callpals executed +system.cpu0.kern.callpal::swpipl 124030 89.84% 91.88% # number of callpals executed +system.cpu0.kern.callpal::rdps 6358 4.61% 96.48% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.48% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.49% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.49% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.50% # number of callpals executed +system.cpu0.kern.callpal::rti 4305 3.12% 99.61% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.29% 99.90% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.10% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 138052 # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 144417 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 4856 # number of quiesce instructions executed -system.cpu0.kern.ipl_count::0 47763 39.05% 39.05% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 239 0.20% 39.25% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1931 1.58% 40.83% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 17 0.01% 40.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 72358 59.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 122308 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 47113 48.87% 48.87% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 239 0.25% 49.12% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1931 2.00% 51.13% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 17 0.02% 51.14% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 47097 48.86% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 96397 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1871606920000 98.13% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 101495000 0.01% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 398001000 0.02% 98.16% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 9331000 0.00% 98.16% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 35173046500 1.84% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1907288793500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.986391 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.hwrei 153418 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 4853 # number of quiesce instructions executed +system.cpu0.kern.ipl_count::0 51417 39.39% 39.39% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 237 0.18% 39.58% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1931 1.48% 41.06% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 41.07% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 76919 58.93% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 130520 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 50665 48.95% 48.95% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 237 0.23% 49.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1931 1.87% 51.05% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.02% 51.06% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 50649 48.94% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 103498 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1871325988500 98.09% 98.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 101211000 0.01% 98.10% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 398014500 0.02% 98.12% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 8513500 0.00% 98.12% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 35854604500 1.88% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1907688332000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.985374 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.650889 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good::kernel 1283 -system.cpu0.kern.mode_good::user 1283 +system.cpu0.kern.ipl_used::31 0.658472 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good::kernel 1370 +system.cpu0.kern.mode_good::user 1371 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch::kernel 5894 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches +system.cpu0.kern.mode_switch::kernel 6220 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1371 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good::kernel 0.217679 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.220257 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1905143965500 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2121516000 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1905422249500 99.88% 99.88% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2266074500 0.12% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2411 # number of times the context was actually changed -system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed -system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed -system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed -system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 222 # number of syscalls executed -system.cpu0.memDep0.conflictingLoads 2050556 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1832562 # Number of conflicting stores. -system.cpu0.memDep0.insertedLoads 7553743 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 4836003 # Number of stores inserted to the mem dependence unit. -system.cpu0.numCycles 100902023 # number of cpu cycles simulated -system.cpu0.rename.RENAME:BlockCycles 10627685 # Number of cycles rename is blocking -system.cpu0.rename.RENAME:CommittedMaps 27337911 # Number of HB maps that are committed -system.cpu0.rename.RENAME:IQFullEvents 742850 # Number of times rename has blocked due to IQ full -system.cpu0.rename.RENAME:IdleCycles 26930386 # Number of cycles rename is idle -system.cpu0.rename.RENAME:LSQFullEvents 1646609 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RENAME:ROBFullEvents 16617 # Number of times rename has blocked due to ROB full -system.cpu0.rename.RENAME:RenameLookups 58880297 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 48158408 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 32535845 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 9104791 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 1094070 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 3612728 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 5197934 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:serializeStallCycles 19157121 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RENAME:serializingInsts 1163461 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 8536823 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 181475 # count of temporary serializing insts renamed -system.cpu0.timesIdled 904727 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.kern.swap_context 2653 # number of times the context was actually changed +system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed +system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed +system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed +system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed +system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed +system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 234 # number of syscalls executed +system.cpu0.memDep0.conflictingLoads 2188476 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1997712 # Number of conflicting stores. +system.cpu0.memDep0.insertedLoads 8008916 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5151785 # Number of stores inserted to the mem dependence unit. +system.cpu0.numCycles 105688118 # number of cpu cycles simulated +system.cpu0.rename.RENAME:BlockCycles 11112209 # Number of cycles rename is blocking +system.cpu0.rename.RENAME:CommittedMaps 28779848 # Number of HB maps that are committed +system.cpu0.rename.RENAME:IQFullEvents 792454 # Number of times rename has blocked due to IQ full +system.cpu0.rename.RENAME:IdleCycles 28590888 # Number of cycles rename is idle +system.cpu0.rename.RENAME:LSQFullEvents 1753238 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RENAME:ROBFullEvents 16675 # Number of times rename has blocked due to ROB full +system.cpu0.rename.RENAME:RenameLookups 62049686 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 50763826 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 34216131 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 9514762 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 1147003 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 3857610 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 5436281 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:serializeStallCycles 20589712 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 1236784 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 9152277 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 192000 # count of temporary serializing insts renamed +system.cpu0.timesIdled 961954 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.BTBHits 2271371 # Number of BTB hits -system.cpu1.BPredUnit.BTBLookups 5052294 # Number of BTB lookups -system.cpu1.BPredUnit.RASInCorrect 16405 # Number of incorrect RAS predictions. -system.cpu1.BPredUnit.condIncorrect 327507 # Number of conditional branches incorrect -system.cpu1.BPredUnit.condPredicted 4551940 # Number of conditional branches predicted -system.cpu1.BPredUnit.lookups 5538388 # Number of BP lookups -system.cpu1.BPredUnit.usedRAS 417428 # Number of times the RAS was used to get a target. -system.cpu1.commit.COM:branches 2947825 # Number of branches committed -system.cpu1.commit.COM:bw_lim_events 401526 # number cycles where commit BW limit reached +system.cpu1.BPredUnit.BTBHits 1953599 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 4355656 # Number of BTB lookups +system.cpu1.BPredUnit.RASInCorrect 14923 # Number of incorrect RAS predictions. +system.cpu1.BPredUnit.condIncorrect 286606 # Number of conditional branches incorrect +system.cpu1.BPredUnit.condPredicted 4049478 # Number of conditional branches predicted +system.cpu1.BPredUnit.lookups 4938226 # Number of BP lookups +system.cpu1.BPredUnit.usedRAS 376891 # Number of times the RAS was used to get a target. +system.cpu1.commit.COM:branches 2617539 # Number of branches committed +system.cpu1.commit.COM:bw_lim_events 356362 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.COM:committed_per_cycle::samples 37477420 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::mean 0.524684 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::stdev 1.336555 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::samples 33118489 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::mean 0.526612 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::stdev 1.338198 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::0-1 29419430 78.50% 78.50% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::1-2 3577485 9.55% 88.04% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::2-3 1728132 4.61% 92.66% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::3-4 1049887 2.80% 95.46% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::4-5 708572 1.89% 97.35% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::5-6 265966 0.71% 98.06% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::6-7 180885 0.48% 98.54% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::7-8 145537 0.39% 98.93% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::8 401526 1.07% 100.00% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::0-1 25969028 78.41% 78.41% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::1-2 3179753 9.60% 88.01% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::2-3 1522948 4.60% 92.61% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::3-4 936064 2.83% 95.44% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::4-5 628296 1.90% 97.34% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::5-6 237537 0.72% 98.05% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::6-7 164527 0.50% 98.55% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::7-8 123974 0.37% 98.92% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::8 356362 1.08% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::total 37477420 # Number of insts commited each cycle -system.cpu1.commit.COM:count 19663805 # Number of instructions committed -system.cpu1.commit.COM:loads 3551077 # Number of loads committed -system.cpu1.commit.COM:membars 87378 # Number of memory barriers committed -system.cpu1.commit.COM:refs 5861573 # Number of memory references committed +system.cpu1.commit.COM:committed_per_cycle::total 33118489 # Number of insts commited each cycle +system.cpu1.commit.COM:count 17440586 # Number of instructions committed +system.cpu1.commit.COM:loads 3166581 # Number of loads committed +system.cpu1.commit.COM:membars 77258 # Number of memory barriers committed +system.cpu1.commit.COM:refs 5179825 # Number of memory references committed system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.branchMispredicts 311117 # The number of times a branch was mispredicted -system.cpu1.commit.commitCommittedInsts 19663805 # The number of committed instructions -system.cpu1.commit.commitNonSpecStalls 255745 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 3737019 # The number of squashed insts skipped by commit -system.cpu1.committedInsts 18529870 # Number of Instructions Simulated -system.cpu1.committedInsts_total 18529870 # Number of Instructions Simulated -system.cpu1.cpi 2.312190 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.312190 # CPI: Total CPI of All Threads -system.cpu1.dcache.LoadLockedReq_accesses::0 72126 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 72126 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 14445.783133 # average LoadLockedReq miss latency +system.cpu1.commit.branchMispredicts 272102 # The number of times a branch was mispredicted +system.cpu1.commit.commitCommittedInsts 17440586 # The number of committed instructions +system.cpu1.commit.commitNonSpecStalls 227930 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.commitSquashedInsts 3329840 # The number of squashed insts skipped by commit +system.cpu1.committedInsts 16438996 # Number of Instructions Simulated +system.cpu1.committedInsts_total 16438996 # Number of Instructions Simulated +system.cpu1.cpi 2.304097 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.304097 # CPI: Total CPI of All Threads +system.cpu1.dcache.LoadLockedReq_accesses::0 63271 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 63271 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 14821.069300 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11202.181535 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits::0 59842 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 59842 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 177452000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.170313 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses::0 12284 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 12284 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_hits 2016 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 115024000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.142362 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11124.971610 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits::0 52535 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 52535 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 159119000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.169683 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses::0 10736 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 10736 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_hits 1930 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 97966500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.139179 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 10268 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses::0 3589394 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3589394 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency::0 15546.336868 # average ReadReq miss latency +system.cpu1.dcache.LoadLockedReq_mshr_misses 8806 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses::0 3203716 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3203716 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency::0 15842.853412 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12022.349090 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12100.517465 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits::0 2947184 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2947184 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 9984013000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate::0 0.178919 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses::0 642210 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 642210 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 211141 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 5182462000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.120095 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_hits::0 2644617 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2644617 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 8857723500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate::0 0.174516 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses::0 559099 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 559099 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_hits 185547 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency 4520172500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.116600 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 431069 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 298578500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses::0 68169 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 68169 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 54676.100066 # average StoreCondReq miss latency +system.cpu1.dcache.ReadReq_mshr_misses 373552 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 298583500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.StoreCondReq_accesses::0 59498 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 59498 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 54415.622389 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 51676.100066 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits::0 51420 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 51420 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 915770000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.245698 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses::0 16749 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 16749 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 865523000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.245698 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 51415.622389 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits::0 45134 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 45134 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 781626000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.241420 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses::0 14364 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 14364 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 738534000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.241420 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 16749 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses::0 2234886 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2234886 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency::0 49366.459666 # average WriteReq miss latency +system.cpu1.dcache.StoreCondReq_mshr_misses 14364 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses::0 1946502 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1946502 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency::0 49498.272766 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54247.809571 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54160.909528 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits::0 1540754 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1540754 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 34266839381 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate::0 0.310589 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses::0 694132 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 694132 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_hits 551528 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 7735954636 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.063808 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_hits::0 1381655 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1381655 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 27958950877 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate::0 0.290186 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses::0 564847 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 564847 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_hits 446490 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_miss_latency 6410322769 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.060805 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 142604 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 526038500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13994.026145 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 5000 # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 8.879077 # Average number of references to valid blocks. -system.cpu1.dcache.blocked::no_mshrs 31364 # number of cycles access was blocked +system.cpu1.dcache.WriteReq_mshr_misses 118357 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 526362000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13351.888091 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 18500 # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 9.264017 # Average number of references to valid blocks. +system.cpu1.dcache.blocked::no_mshrs 24797 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_mshrs 438908636 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5000 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 331086769 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 18500 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses::0 5824280 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::0 5150218 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 5824280 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency::0 33113.418856 # average overall miss latency +system.cpu1.dcache.demand_accesses::total 5150218 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency::0 32756.622095 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 22518.780971 # average overall mshr miss latency -system.cpu1.dcache.demand_hits::0 4487938 # number of demand (read+write) hits +system.cpu1.dcache.demand_avg_mshr_miss_latency 22220.563700 # average overall mshr miss latency +system.cpu1.dcache.demand_hits::0 4026272 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4487938 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 44250852381 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate::0 0.229443 # miss rate for demand accesses +system.cpu1.dcache.demand_hits::total 4026272 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 36816674377 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate::0 0.218233 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.demand_misses::0 1336342 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::0 1123946 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1336342 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 762669 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 12918416636 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate::0 0.098497 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_misses::total 1123946 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 632037 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 10930495269 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate::0 0.095512 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 573673 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses 491909 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.953247 # Average percentage of cache occupancy -system.cpu1.dcache.occ_%::1 -0.003823 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 488.062339 # Average occupied blocks per context -system.cpu1.dcache.occ_blocks::1 -1.957577 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses::0 5824280 # number of overall (read+write) accesses +system.cpu1.dcache.occ_%::0 0.951616 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 487.227171 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses::0 5150218 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 5824280 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency::0 33113.418856 # average overall miss latency +system.cpu1.dcache.overall_accesses::total 5150218 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency::0 32756.622095 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 22518.780971 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 22220.563700 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits::0 4487938 # number of overall hits +system.cpu1.dcache.overall_hits::0 4026272 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 4487938 # number of overall hits -system.cpu1.dcache.overall_miss_latency 44250852381 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate::0 0.229443 # miss rate for overall accesses +system.cpu1.dcache.overall_hits::total 4026272 # number of overall hits +system.cpu1.dcache.overall_miss_latency 36816674377 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate::0 0.218233 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.overall_misses::0 1336342 # number of overall misses +system.cpu1.dcache.overall_misses::0 1123946 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 1336342 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 762669 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 12918416636 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate::0 0.098497 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_misses::total 1123946 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 632037 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 10930495269 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate::0 0.095512 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 573673 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 824617000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_misses 491909 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 824945500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.replacements 531784 # number of replacements -system.cpu1.dcache.sampled_refs 532296 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 455363 # number of replacements +system.cpu1.dcache.sampled_refs 455691 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 487.083551 # Cycle average of tags in use -system.cpu1.dcache.total_refs 4726297 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 39405720000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 158239 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 17789619 # Number of cycles decode is blocked -system.cpu1.decode.DECODE:BranchMispred 18017 # Number of times decode detected a branch misprediction -system.cpu1.decode.DECODE:BranchResolved 246499 # Number of times decode resolved a branch -system.cpu1.decode.DECODE:DecodedInsts 26253455 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 14731428 # Number of cycles decode is idle -system.cpu1.decode.DECODE:RunCycles 4724231 # Number of cycles decode is running -system.cpu1.decode.DECODE:SquashCycles 641523 # Number of cycles decode is squashing -system.cpu1.decode.DECODE:SquashedInsts 52769 # Number of squashed instructions handled by decode -system.cpu1.decode.DECODE:UnblockCycles 232141 # Number of cycles decode is unblocking -system.cpu1.dtb.data_accesses 433929 # DTB accesses -system.cpu1.dtb.data_acv 77 # DTB access violations -system.cpu1.dtb.data_hits 6280304 # DTB hits -system.cpu1.dtb.data_misses 17153 # DTB misses +system.cpu1.dcache.tagsinuse 487.227171 # Cycle average of tags in use +system.cpu1.dcache.total_refs 4221529 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 41371153000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 131807 # number of writebacks +system.cpu1.decode.DECODE:BlockedCycles 15690044 # Number of cycles decode is blocked +system.cpu1.decode.DECODE:BranchMispred 15658 # Number of times decode detected a branch misprediction +system.cpu1.decode.DECODE:BranchResolved 221514 # Number of times decode resolved a branch +system.cpu1.decode.DECODE:DecodedInsts 23293804 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 13052984 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 4174567 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 566096 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:SquashedInsts 47077 # Number of squashed instructions handled by decode +system.cpu1.decode.DECODE:UnblockCycles 200893 # Number of cycles decode is unblocking +system.cpu1.dtb.data_accesses 379955 # DTB accesses +system.cpu1.dtb.data_acv 65 # DTB access violations +system.cpu1.dtb.data_hits 5542909 # DTB hits +system.cpu1.dtb.data_misses 13981 # DTB misses system.cpu1.dtb.fetch_accesses 0 # ITB accesses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.read_accesses 314117 # DTB read accesses -system.cpu1.dtb.read_acv 13 # DTB read access violations -system.cpu1.dtb.read_hits 3872751 # DTB read hits -system.cpu1.dtb.read_misses 13436 # DTB read misses -system.cpu1.dtb.write_accesses 119812 # DTB write accesses -system.cpu1.dtb.write_acv 64 # DTB write access violations -system.cpu1.dtb.write_hits 2407553 # DTB write hits -system.cpu1.dtb.write_misses 3717 # DTB write misses -system.cpu1.fetch.Branches 5538388 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 3089103 # Number of cache lines fetched -system.cpu1.fetch.Cycles 8137045 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 192731 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 26826558 # Number of instructions fetch has processed -system.cpu1.fetch.MiscStallCycles 1090 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.SquashCycles 373512 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.129267 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 3089103 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 2688799 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 0.626137 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist::samples 38118943 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.703759 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.021088 # Number of instructions fetched each cycle (Total) +system.cpu1.dtb.read_accesses 276518 # DTB read accesses +system.cpu1.dtb.read_acv 12 # DTB read access violations +system.cpu1.dtb.read_hits 3445692 # DTB read hits +system.cpu1.dtb.read_misses 11718 # DTB read misses +system.cpu1.dtb.write_accesses 103437 # DTB write accesses +system.cpu1.dtb.write_acv 53 # DTB write access violations +system.cpu1.dtb.write_hits 2097217 # DTB write hits +system.cpu1.dtb.write_misses 2263 # DTB write misses +system.cpu1.fetch.Branches 4938226 # Number of branches that fetch encountered +system.cpu1.fetch.CacheLines 2741713 # Number of cache lines fetched +system.cpu1.fetch.Cycles 7194016 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 172775 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 23780795 # Number of instructions fetch has processed +system.cpu1.fetch.MiscStallCycles 714 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.SquashCycles 326197 # Number of cycles fetch has spent squashing +system.cpu1.fetch.branchRate 0.130375 # Number of branch fetches per cycle +system.cpu1.fetch.icacheStallCycles 2741713 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.predictedBranches 2330490 # Number of branches that fetch has predicted taken +system.cpu1.fetch.rate 0.627842 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist::samples 33684585 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.705985 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.028331 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0-1 33077920 86.78% 86.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1-2 338218 0.89% 87.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2-3 684572 1.80% 89.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3-4 401329 1.05% 90.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4-5 792382 2.08% 92.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5-6 254420 0.67% 93.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6-7 341251 0.90% 94.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7-8 404733 1.06% 95.21% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1824118 4.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0-1 29238127 86.80% 86.80% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1-2 297283 0.88% 87.68% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2-3 597287 1.77% 89.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3-4 350001 1.04% 90.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4-5 693611 2.06% 92.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5-6 228580 0.68% 93.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6-7 280979 0.83% 94.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7-8 354019 1.05% 95.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1644698 4.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 38118943 # Number of instructions fetched each cycle (Total) -system.cpu1.icache.ReadReq_accesses::0 3089103 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 3089103 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency::0 14554.957905 # average ReadReq miss latency +system.cpu1.fetch.rateDist::total 33684585 # Number of instructions fetched each cycle (Total) +system.cpu1.icache.ReadReq_accesses::0 2741713 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 2741713 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency::0 14618.155893 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11604.745633 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits::0 2620972 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 2620972 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 6813626999 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate::0 0.151543 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses::0 468131 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 468131 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_hits 20962 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 5189282500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.144757 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11660.018500 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits::0 2328949 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 2328949 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 6033848499 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate::0 0.150550 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses::0 412764 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 412764 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_hits 18169 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_miss_latency 4600985000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.143923 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 447169 # number of ReadReq MSHR misses -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11057.692308 # average number of cycles each access was blocked +system.cpu1.icache.ReadReq_mshr_misses 394595 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11340.909091 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 5.861938 # Average number of references to valid blocks. -system.cpu1.icache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu1.icache.avg_refs 5.902933 # Average number of references to valid blocks. +system.cpu1.icache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_mshrs 287500 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 249500 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses::0 3089103 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::0 2741713 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 3089103 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency::0 14554.957905 # average overall miss latency +system.cpu1.icache.demand_accesses::total 2741713 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency::0 14618.155893 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11604.745633 # average overall mshr miss latency -system.cpu1.icache.demand_hits::0 2620972 # number of demand (read+write) hits +system.cpu1.icache.demand_avg_mshr_miss_latency 11660.018500 # average overall mshr miss latency +system.cpu1.icache.demand_hits::0 2328949 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 2620972 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 6813626999 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate::0 0.151543 # miss rate for demand accesses +system.cpu1.icache.demand_hits::total 2328949 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 6033848499 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate::0 0.150550 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.demand_misses::0 468131 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::0 412764 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 468131 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 20962 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 5189282500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate::0 0.144757 # mshr miss rate for demand accesses +system.cpu1.icache.demand_misses::total 412764 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 18169 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 4600985000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate::0 0.143923 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 447169 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses 394595 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.985305 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 504.476148 # Average occupied blocks per context -system.cpu1.icache.overall_accesses::0 3089103 # number of overall (read+write) accesses +system.cpu1.icache.occ_%::0 0.984930 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 504.284109 # Average occupied blocks per context +system.cpu1.icache.overall_accesses::0 2741713 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 3089103 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency::0 14554.957905 # average overall miss latency +system.cpu1.icache.overall_accesses::total 2741713 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency::0 14618.155893 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11604.745633 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11660.018500 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits::0 2620972 # number of overall hits +system.cpu1.icache.overall_hits::0 2328949 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 2620972 # number of overall hits -system.cpu1.icache.overall_miss_latency 6813626999 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate::0 0.151543 # miss rate for overall accesses +system.cpu1.icache.overall_hits::total 2328949 # number of overall hits +system.cpu1.icache.overall_miss_latency 6033848499 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate::0 0.150550 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.overall_misses::0 468131 # number of overall misses +system.cpu1.icache.overall_misses::0 412764 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 468131 # number of overall misses -system.cpu1.icache.overall_mshr_hits 20962 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 5189282500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate::0 0.144757 # mshr miss rate for overall accesses +system.cpu1.icache.overall_misses::total 412764 # number of overall misses +system.cpu1.icache.overall_mshr_hits 18169 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 4600985000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate::0 0.143923 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 447169 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses 394595 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 446606 # number of replacements -system.cpu1.icache.sampled_refs 447117 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 394030 # number of replacements +system.cpu1.icache.sampled_refs 394541 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 504.476148 # Cycle average of tags in use -system.cpu1.icache.total_refs 2620972 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 54243392000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tagsinuse 504.284109 # Cycle average of tags in use +system.cpu1.icache.total_refs 2328949 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 54145022000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idleCycles 4725629 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.EXEC:branches 3215720 # Number of branches executed -system.cpu1.iew.EXEC:nop 1316352 # number of nop insts executed -system.cpu1.iew.EXEC:rate 0.474690 # Inst execution rate -system.cpu1.iew.EXEC:refs 6453151 # number of memory reference insts executed -system.cpu1.iew.EXEC:stores 2418978 # Number of stores executed +system.cpu1.idleCycles 4192462 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 2856676 # Number of branches executed +system.cpu1.iew.EXEC:nop 1154303 # number of nop insts executed +system.cpu1.iew.EXEC:rate 0.475940 # Inst execution rate +system.cpu1.iew.EXEC:refs 5695199 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 2106410 # Number of stores executed system.cpu1.iew.EXEC:swp 0 # number of swp insts executed -system.cpu1.iew.WB:consumers 12377931 # num instructions consuming a value -system.cpu1.iew.WB:count 20081292 # cumulative count of insts written-back -system.cpu1.iew.WB:fanout 0.731656 # average fanout of values written-back +system.cpu1.iew.WB:consumers 11059026 # num instructions consuming a value +system.cpu1.iew.WB:count 17811363 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.729393 # average fanout of values written-back system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.WB:producers 9056386 # num instructions producing a value -system.cpu1.iew.WB:rate 0.468701 # insts written-back per cycle -system.cpu1.iew.WB:sent 20123893 # cumulative count of insts sent to commit -system.cpu1.iew.branchMispredicts 338961 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewBlockCycles 2501197 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 4247431 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 782465 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 352902 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 2557372 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 23476845 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 4034173 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 224909 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 20337896 # Number of executed instructions -system.cpu1.iew.iewIQFullEvents 13271 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.WB:producers 8066373 # num instructions producing a value +system.cpu1.iew.WB:rate 0.470242 # insts written-back per cycle +system.cpu1.iew.WB:sent 17846809 # cumulative count of insts sent to commit +system.cpu1.iew.branchMispredicts 295481 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewBlockCycles 2247167 # Number of cycles IEW is blocking +system.cpu1.iew.iewDispLoadInsts 3784809 # Number of dispatched load instructions +system.cpu1.iew.iewDispNonSpecInsts 705322 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewDispSquashedInsts 304722 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispStoreInsts 2229881 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 20840957 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 3588789 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 201614 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 18027204 # Number of executed instructions +system.cpu1.iew.iewIQFullEvents 12484 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewLSQFullEvents 2314 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 641523 # Number of cycles IEW is squashing -system.cpu1.iew.iewUnblockCycles 92599 # Number of cycles IEW is unblocking +system.cpu1.iew.iewLSQFullEvents 2361 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 566096 # Number of cycles IEW is squashing +system.cpu1.iew.iewUnblockCycles 83136 # Number of cycles IEW is unblocking system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread.0.cacheBlocked 96430 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 136935 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread.0.ignoredResponses 5812 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread.0.cacheBlocked 73212 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread.0.forwLoads 122514 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread.0.ignoredResponses 3897 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 18287 # Number of memory ordering violations -system.cpu1.iew.lsq.thread.0.rescheduledLoads 7643 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 696354 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 246876 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 18287 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 160561 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 178400 # Number of branches that were predicted taken incorrectly -system.cpu1.ipc 0.432490 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.432490 # IPC: Total IPC of All Threads -system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3984 0.02% 0.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntAlu 13476075 65.54% 65.56% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntMult 28965 0.14% 65.70% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.70% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 13702 0.07% 65.76% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.76% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.76% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.76% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1986 0.01% 65.77% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.77% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemRead 4173782 20.30% 86.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemWrite 2443072 11.88% 97.95% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IprAccess 421241 2.05% 100.00% # Type of FU issued +system.cpu1.iew.lsq.thread.0.memOrderViolation 16678 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.rescheduledLoads 6458 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread.0.squashedLoads 618228 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 216637 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 16678 # Number of memory order violations +system.cpu1.iew.predictedNotTakenIncorrect 152685 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 142796 # Number of branches that were predicted taken incorrectly +system.cpu1.ipc 0.434009 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.434009 # IPC: Total IPC of All Threads +system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3528 0.02% 0.02% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntAlu 11967153 65.65% 65.67% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntMult 27009 0.15% 65.82% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.82% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 12064 0.07% 65.88% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.88% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.88% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.88% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1759 0.01% 65.89% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.89% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemRead 3711124 20.36% 86.25% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemWrite 2127008 11.67% 97.92% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IprAccess 379173 2.08% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::total 20562807 # Type of FU issued -system.cpu1.iq.ISSUE:fu_busy_cnt 221150 # FU busy when requested -system.cpu1.iq.ISSUE:fu_busy_rate 0.010755 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:FU_type_0::total 18228818 # Type of FU issued +system.cpu1.iq.ISSUE:fu_busy_cnt 196946 # FU busy when requested +system.cpu1.iq.ISSUE:fu_busy_rate 0.010804 # FU busy rate (busy events/executed inst) system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntAlu 16139 7.30% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemRead 131899 59.64% 66.94% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemWrite 73112 33.06% 100.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntAlu 13962 7.09% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemRead 116519 59.16% 66.25% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemWrite 66465 33.75% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:issued_per_cycle::samples 38118943 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.539438 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.158785 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::samples 33684585 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.541162 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.162170 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::0-1 28405834 74.52% 74.52% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::1-2 4664798 12.24% 86.76% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::2-3 1989487 5.22% 91.98% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::3-4 1362185 3.57% 95.55% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::4-5 979454 2.57% 98.12% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::5-6 465472 1.22% 99.34% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::6-7 186874 0.49% 99.83% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::7-8 52652 0.14% 99.97% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::8 12187 0.03% 100.00% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::0-1 25088136 74.48% 74.48% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::1-2 4124812 12.25% 86.72% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::2-3 1756786 5.22% 91.94% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::3-4 1209447 3.59% 95.53% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::4-5 865609 2.57% 98.10% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::5-6 413218 1.23% 99.33% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::6-7 164057 0.49% 99.81% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::7-8 50935 0.15% 99.97% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::8 11585 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::total 38118943 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:rate 0.479940 # Inst issue rate -system.cpu1.iq.iqInstsAdded 21283926 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 20562807 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 876567 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 3483517 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedInstsIssued 16728 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 620822 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 1775091 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.ISSUE:issued_per_cycle::total 33684585 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:rate 0.481263 # Inst issue rate +system.cpu1.iq.iqInstsAdded 18897687 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 18228818 # Number of instructions issued +system.cpu1.iq.iqNonSpecInstsAdded 788967 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqSquashedInstsExamined 3125649 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedInstsIssued 15583 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedNonSpecRemoved 561037 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.iqSquashedOperandsExamined 1602623 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_hits 0 # DTB hits system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.fetch_accesses 525294 # ITB accesses -system.cpu1.itb.fetch_acv 109 # ITB acv -system.cpu1.itb.fetch_hits 518481 # ITB hits -system.cpu1.itb.fetch_misses 6813 # ITB misses +system.cpu1.itb.fetch_accesses 472041 # ITB accesses +system.cpu1.itb.fetch_acv 106 # ITB acv +system.cpu1.itb.fetch_hits 466299 # ITB hits +system.cpu1.itb.fetch_misses 5742 # ITB misses system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.read_acv 0 # DTB read access violations system.cpu1.itb.read_hits 0 # DTB read hits @@ -1006,95 +1004,95 @@ system.cpu1.itb.write_acv 0 # DT system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 17 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1838 2.10% 2.13% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 2.13% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.14% # number of callpals executed -system.cpu1.kern.callpal::swpipl 79684 91.22% 93.36% # number of callpals executed -system.cpu1.kern.callpal::rdps 2408 2.76% 96.11% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 96.11% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.00% 96.12% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 96.12% # number of callpals executed -system.cpu1.kern.callpal::rti 3206 3.67% 99.79% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.16% 99.95% # number of callpals executed -system.cpu1.kern.callpal::imb 44 0.05% 100.00% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1586 2.01% 2.04% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 2.04% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.05% # number of callpals executed +system.cpu1.kern.callpal::swpipl 71639 90.87% 92.92% # number of callpals executed +system.cpu1.kern.callpal::rdps 2407 3.05% 95.97% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 95.97% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.00% 95.97% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 95.98% # number of callpals executed +system.cpu1.kern.callpal::rti 3007 3.81% 99.79% # number of callpals executed +system.cpu1.kern.callpal::callsys 121 0.15% 99.95% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.05% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 87355 # number of callpals executed +system.cpu1.kern.callpal::total 78839 # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 93966 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 3806 # number of quiesce instructions executed -system.cpu1.kern.ipl_count::0 34143 40.21% 40.21% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1928 2.27% 42.48% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 96 0.11% 42.59% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 48748 57.41% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 84915 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 33416 48.60% 48.60% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1928 2.80% 51.40% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 96 0.14% 51.54% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 33320 48.46% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 68760 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1871986905500 98.13% 98.13% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 352078000 0.02% 98.15% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 40004500 0.00% 98.15% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 35325543000 1.85% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1907704531000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.978707 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 84815 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 3812 # number of quiesce instructions executed +system.cpu1.kern.ipl_count::0 30474 39.75% 39.75% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1928 2.51% 42.26% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 96 0.13% 42.39% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 44173 57.61% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 76671 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 29849 48.44% 48.44% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1928 3.13% 51.56% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 96 0.16% 51.72% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 29753 48.28% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 61626 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1872267971000 98.16% 98.16% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 351911000 0.02% 98.18% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 40319500 0.00% 98.19% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 34610873000 1.81% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1907271074500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.979491 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.683515 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good::kernel 521 -system.cpu1.kern.mode_good::user 463 +system.cpu1.kern.ipl_used::31 0.673556 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good::kernel 424 +system.cpu1.kern.mode_good::user 366 system.cpu1.kern.mode_good::idle 58 -system.cpu1.kern.mode_switch::kernel 2305 # number of protection mode switches -system.cpu1.kern.mode_switch::user 463 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2035 # number of protection mode switches -system.cpu1.kern.mode_switch_good::kernel 0.226030 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch::kernel 1953 # number of protection mode switches +system.cpu1.kern.mode_switch::user 366 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2037 # number of protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.217102 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.028501 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.254532 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 46750182500 2.45% 2.45% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1015923000 0.05% 2.50% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1859938417500 97.50% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1839 # number of times the context was actually changed -system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed -system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed -system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed -system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed -system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 104 # number of syscalls executed -system.cpu1.memDep0.conflictingLoads 906343 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 817120 # Number of conflicting stores. -system.cpu1.memDep0.insertedLoads 4247431 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 2557372 # Number of stores inserted to the mem dependence unit. -system.cpu1.numCycles 42844572 # number of cpu cycles simulated -system.cpu1.rename.RENAME:BlockCycles 3655833 # Number of cycles rename is blocking -system.cpu1.rename.RENAME:CommittedMaps 13191652 # Number of HB maps that are committed -system.cpu1.rename.RENAME:IQFullEvents 331503 # Number of times rename has blocked due to IQ full -system.cpu1.rename.RENAME:IdleCycles 15199726 # Number of cycles rename is idle -system.cpu1.rename.RENAME:LSQFullEvents 648645 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RENAME:ROBFullEvents 1226 # Number of times rename has blocked due to ROB full -system.cpu1.rename.RENAME:RenameLookups 29419521 # Number of register rename lookups that rename has made -system.cpu1.rename.RENAME:RenamedInsts 24525143 # Number of instructions processed by rename -system.cpu1.rename.RENAME:RenamedOperands 16182603 # Number of destination operands rename has renamed -system.cpu1.rename.RENAME:RunCycles 4333690 # Number of cycles rename is running -system.cpu1.rename.RENAME:SquashCycles 641523 # Number of cycles rename is squashing -system.cpu1.rename.RENAME:UnblockCycles 1812010 # Number of cycles rename is unblocking -system.cpu1.rename.RENAME:UndoneMaps 2990949 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:serializeStallCycles 12476159 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RENAME:serializingInsts 728375 # count of serializing insts renamed -system.cpu1.rename.RENAME:skidInsts 4962161 # count of insts added to the skid buffer -system.cpu1.rename.RENAME:tempSerializingInsts 86287 # count of temporary serializing insts renamed -system.cpu1.timesIdled 480522 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.kern.mode_switch_good::idle 0.028473 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.245575 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 44394454000 2.33% 2.33% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 886105500 0.05% 2.37% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1861549295500 97.63% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1587 # number of times the context was actually changed +system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed +system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed +system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed +system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed +system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 92 # number of syscalls executed +system.cpu1.memDep0.conflictingLoads 820507 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 719564 # Number of conflicting stores. +system.cpu1.memDep0.insertedLoads 3784809 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 2229881 # Number of stores inserted to the mem dependence unit. +system.cpu1.numCycles 37877047 # number of cpu cycles simulated +system.cpu1.rename.RENAME:BlockCycles 3238650 # Number of cycles rename is blocking +system.cpu1.rename.RENAME:CommittedMaps 11736980 # Number of HB maps that are committed +system.cpu1.rename.RENAME:IQFullEvents 293624 # Number of times rename has blocked due to IQ full +system.cpu1.rename.RENAME:IdleCycles 13473240 # Number of cycles rename is idle +system.cpu1.rename.RENAME:LSQFullEvents 554151 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RENAME:ROBFullEvents 942 # Number of times rename has blocked due to ROB full +system.cpu1.rename.RENAME:RenameLookups 26045586 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 21738411 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 14384581 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 3820320 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 566096 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:UnblockCycles 1590671 # Number of cycles rename is unblocking +system.cpu1.rename.RENAME:UndoneMaps 2647601 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:serializeStallCycles 10995606 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializingInsts 652471 # count of serializing insts renamed +system.cpu1.rename.RENAME:skidInsts 4381532 # count of insts added to the skid buffer +system.cpu1.rename.RENAME:tempSerializingInsts 75403 # count of temporary serializing insts renamed +system.cpu1.timesIdled 422616 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1107,262 +1105,262 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses::1 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::1 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115331.417143 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115252.862069 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63331.417143 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 20182998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_mshr_miss_latency 63252.862069 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 20053998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses::1 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 11082998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_misses::1 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.ReadReq_mshr_miss_latency 11005998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_misses 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses 174 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137844.166490 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137849.677657 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85840.579852 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5727700806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85846.237437 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5727929806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3566847774 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3567082858 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6165.982406 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6166.374068 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked::no_mshrs 10458 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64483844 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64487940 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41727 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137749.749658 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137755.447539 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85746.178062 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85752.021665 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5747883804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5747983804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41727 # number of demand (read+write) misses -system.iocache.demand_misses::total 41727 # number of demand (read+write) misses +system.iocache.demand_misses::1 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3577930772 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3578088856 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 41727 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses 41726 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.024239 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 0.387817 # Average occupied blocks per context +system.iocache.occ_%::1 0.028124 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 0.449991 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41727 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137749.749658 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137755.447539 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85746.178062 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85752.021665 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5747883804 # number of overall miss cycles +system.iocache.overall_miss_latency 5747983804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41727 # number of overall misses -system.iocache.overall_misses::total 41727 # number of overall misses +system.iocache.overall_misses::1 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3577930772 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3578088856 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 41727 # number of overall MSHR misses +system.iocache.overall_mshr_misses 41726 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.replacements 41697 # number of replacements -system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. +system.iocache.replacements 41696 # number of replacements +system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.387817 # Cycle average of tags in use +system.iocache.tagsinuse 0.449991 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1717170531000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1717168496000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41522 # number of writebacks -system.l2c.ReadExReq_accesses::0 221647 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 95855 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 317502 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 75026.275109 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 173484.417078 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 236243 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 78291 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 314534 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 69731.847293 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 210415.766819 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40223.037770 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 16629348799 # number of ReadExReq miss cycles +system.l2c.ReadExReq_avg_mshr_miss_latency 40217.604332 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 16473660800 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 221647 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 95855 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 317502 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12770894938 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 1.432467 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 3.312315 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 236243 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 78291 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 314534 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12649803961 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 1.331400 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 4.017499 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 317502 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 1321671 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 883108 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2204779 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 53351.845432 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 2020931.340670 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 314534 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 1423603 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 771316 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2194919 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 53400.832785 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 1985457.471546 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 39977.821348 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 39990.811057 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1018788 # number of ReadReq hits -system.l2c.ReadReq_hits::1 875112 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1893900 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16159367000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.229167 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.009054 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 302883 # number of ReadReq misses -system.l2c.ReadReq_misses::1 7996 # number of ReadReq misses -system.l2c.ReadReq_misses::total 310879 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12427585500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.235204 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.352009 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_hits::0 1119803 # number of ReadReq hits +system.l2c.ReadReq_hits::1 763145 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1882948 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16223173000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.213402 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.010594 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 303800 # number of ReadReq misses +system.l2c.ReadReq_misses::1 8171 # number of ReadReq misses +system.l2c.ReadReq_misses::total 311971 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 12475173500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.219128 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.404440 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 310862 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 840472000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 78396 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 63553 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 141949 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 92463.818205 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 114059.029346 # average UpgradeReq miss latency +system.l2c.ReadReq_mshr_misses 311951 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 839822000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 86460 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 54412 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 140872 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 83177.133796 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 132167.444461 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.290548 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 7248793492 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_avg_mshr_miss_latency 40094.049918 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 7191494988 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 78396 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 63553 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 141949 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5691202500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 1.810666 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 2.233553 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 86460 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 54412 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 140872 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5648129000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 1.629331 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 2.588988 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 141949 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 140872 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1423763998 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 455578 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 455578 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 455578 # number of Writeback hits -system.l2c.Writeback_hits::total 455578 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1423289998 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 451661 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 451661 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 451661 # number of Writeback hits +system.l2c.Writeback_hits::total 451661 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 4.834791 # Average number of references to valid blocks. +system.l2c.avg_refs 4.797703 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 1543318 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 978963 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 1659846 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 849607 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2522281 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 62510.658683 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 315728.455181 # average overall miss latency +system.l2c.demand_accesses::total 2509453 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 60544.871057 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 378164.208554 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40101.725175 # average overall mshr miss latency -system.l2c.demand_hits::0 1018788 # number of demand (read+write) hits -system.l2c.demand_hits::1 875112 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40104.675229 # average overall mshr miss latency +system.l2c.demand_hits::0 1119803 # number of demand (read+write) hits +system.l2c.demand_hits::1 763145 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1893900 # number of demand (read+write) hits -system.l2c.demand_miss_latency 32788715799 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.339872 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.106083 # miss rate for demand accesses +system.l2c.demand_hits::total 1882948 # number of demand (read+write) hits +system.l2c.demand_miss_latency 32696833800 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.325357 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.101767 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 524530 # number of demand (read+write) misses -system.l2c.demand_misses::1 103851 # number of demand (read+write) misses +system.l2c.demand_misses::0 540043 # number of demand (read+write) misses +system.l2c.demand_misses::1 86462 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 628381 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 17 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 25198480438 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.407151 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0.641867 # mshr miss rate for demand accesses +system.l2c.demand_misses::total 626505 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 20 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 25124977461 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.377436 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0.737382 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 628364 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 626485 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.065210 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.029545 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.380758 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 4273.595958 # Average occupied blocks per context -system.l2c.occ_blocks::1 1936.249784 # Average occupied blocks per context -system.l2c.occ_blocks::2 24953.333071 # Average occupied blocks per context -system.l2c.overall_accesses::0 1543318 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 978963 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.066802 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.029576 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.372873 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 4377.904620 # Average occupied blocks per context +system.l2c.occ_blocks::1 1938.298251 # Average occupied blocks per context +system.l2c.occ_blocks::2 24436.623036 # Average occupied blocks per context +system.l2c.overall_accesses::0 1659846 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 849607 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2522281 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 62510.658683 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 315728.455181 # average overall miss latency +system.l2c.overall_accesses::total 2509453 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 60544.871057 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 378164.208554 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40101.725175 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40104.675229 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1018788 # number of overall hits -system.l2c.overall_hits::1 875112 # number of overall hits +system.l2c.overall_hits::0 1119803 # number of overall hits +system.l2c.overall_hits::1 763145 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 1893900 # number of overall hits -system.l2c.overall_miss_latency 32788715799 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.339872 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.106083 # miss rate for overall accesses +system.l2c.overall_hits::total 1882948 # number of overall hits +system.l2c.overall_miss_latency 32696833800 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.325357 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.101767 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 524530 # number of overall misses -system.l2c.overall_misses::1 103851 # number of overall misses +system.l2c.overall_misses::0 540043 # number of overall misses +system.l2c.overall_misses::1 86462 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 628381 # number of overall misses -system.l2c.overall_mshr_hits 17 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 25198480438 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.407151 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0.641867 # mshr miss rate for overall accesses +system.l2c.overall_misses::total 626505 # number of overall misses +system.l2c.overall_mshr_hits 20 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 25124977461 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.377436 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0.737382 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 628364 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2264235998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 626485 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2263111998 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 402142 # number of replacements -system.l2c.sampled_refs 433669 # Sample count of references to valid blocks. +system.l2c.replacements 402176 # number of replacements +system.l2c.sampled_refs 435074 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 31163.178813 # Cycle average of tags in use -system.l2c.total_refs 2096699 # Total number of references to valid blocks. -system.l2c.warmup_cycle 9278348000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 124293 # number of writebacks +system.l2c.tagsinuse 30752.825907 # Cycle average of tags in use +system.l2c.total_refs 2087356 # Total number of references to valid blocks. +system.l2c.warmup_cycle 9278644000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 124146 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 6eea1f6ec..8128ce648 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux mem_mode=timing -pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -355,7 +355,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -375,7 +375,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -501,7 +501,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 00e25aeac..f6482ad23 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:13:04 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 24 2010 23:35:15 -M5 executing on SC2B0619 +M5 compiled May 12 2010 02:36:15 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:37:22 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1867362977500 because m5_exit instruction encountered +Exiting @ tick 1867360295500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 75071ea91..6ec7aca0a 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,447 +1,449 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 86499 # Simulator instruction rate (inst/s) -host_mem_usage 277924 # Number of bytes of host memory used -host_seconds 613.76 # Real time elapsed on the host -host_tick_rate 3042478511 # Simulator tick rate (ticks/s) +host_inst_rate 154746 # Simulator instruction rate (inst/s) +host_mem_usage 291744 # Number of bytes of host memory used +host_seconds 343.04 # Real time elapsed on the host +host_tick_rate 5443609822 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 53090223 # Number of instructions simulated -sim_seconds 1.867363 # Number of seconds simulated -sim_ticks 1867362977500 # Number of ticks simulated +sim_insts 53083414 # Number of instructions simulated +sim_seconds 1.867360 # Number of seconds simulated +sim_ticks 1867360295500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 6932886 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 13334785 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 41560 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 829405 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 12127013 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 14563706 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1034705 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 8461925 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 978098 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 6774596 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 12988394 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 41867 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 814870 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 12133144 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 14563531 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1033178 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 8461193 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 999873 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 100629475 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.559325 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.322901 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 100508484 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.559927 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.327303 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 76387036 75.91% 75.91% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 10760374 10.69% 86.60% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 5981089 5.94% 92.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 2990150 2.97% 95.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 2079430 2.07% 97.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 662647 0.66% 98.24% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 398739 0.40% 98.64% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 391912 0.39% 99.03% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 978098 0.97% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 76371825 75.99% 75.99% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 10652369 10.60% 86.58% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 5995069 5.96% 92.55% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 2948172 2.93% 95.48% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 2094039 2.08% 97.57% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 649751 0.65% 98.21% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 415244 0.41% 98.62% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 382142 0.38% 99.01% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 999873 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 100629475 # Number of insts commited each cycle -system.cpu.commit.COM:count 56284559 # Number of instructions committed -system.cpu.commit.COM:loads 9308572 # Number of loads committed -system.cpu.commit.COM:membars 228000 # Number of memory barriers committed -system.cpu.commit.COM:refs 15700770 # Number of memory references committed +system.cpu.commit.COM:committed_per_cycle::total 100508484 # Number of insts commited each cycle +system.cpu.commit.COM:count 56277376 # Number of instructions committed +system.cpu.commit.COM:loads 9307406 # Number of loads committed +system.cpu.commit.COM:membars 227986 # Number of memory barriers committed +system.cpu.commit.COM:refs 15698987 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 787906 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 56284559 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 667787 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 9472622 # The number of squashed insts skipped by commit -system.cpu.committedInsts 53090223 # Number of Instructions Simulated -system.cpu.committedInsts_total 53090223 # Number of Instructions Simulated -system.cpu.cpi 2.580471 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.580471 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses::0 214422 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 214422 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15515.537615 # average LoadLockedReq miss latency +system.cpu.commit.branchMispredicts 773341 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 56277376 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 667767 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 9507253 # The number of squashed insts skipped by commit +system.cpu.committedInsts 53083414 # Number of Instructions Simulated +system.cpu.committedInsts_total 53083414 # Number of Instructions Simulated +system.cpu.cpi 2.579204 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.579204 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses::0 214827 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 214827 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15515.595548 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11814.147928 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits::0 192250 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 192250 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 344010500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103404 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 22172 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22172 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 4650 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207007500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081717 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11814.625753 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::0 192545 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 192545 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 345718500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103721 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 22282 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22282 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 4847 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 205988000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081158 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17522 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 9342386 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9342386 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 23884.018523 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 17435 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses::0 9344739 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9344739 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 23910.895806 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22765.012818 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22793.768876 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7810012 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7810012 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 36599249000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.164024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 1532374 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1532374 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 447551 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 24696009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7810277 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7810277 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 36690361000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.164206 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 1534462 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1534462 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 450067 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 24717449000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116043 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1084823 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904976000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 219797 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 219797 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56331.488950 # average StoreCondReq miss latency +system.cpu.dcache.ReadReq_mshr_misses 1084395 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904961500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 219814 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 219814 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56332.344016 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.488950 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits::0 189796 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 189796 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 1690001000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate::0 0.136494 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses::0 30001 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 30001 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599998000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.136494 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53332.344016 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::0 189827 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 189827 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 1689238000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate::0 0.136420 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses::0 29987 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 29987 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599277000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.136420 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 30001 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses::0 6157245 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157245 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 49037.572489 # average WriteReq miss latency +system.cpu.dcache.StoreCondReq_mshr_misses 29987 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses::0 6156609 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6156609 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 49095.565499 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54494.404609 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54537.318055 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 3926713 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 3926713 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 109379874638 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.362261 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 2230532 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2230532 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1833591 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 21631063460 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.064467 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 3926536 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 3926536 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 109486695038 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.362224 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 2230073 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2230073 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1833805 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 21611393951 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.064365 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 396941 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235842997 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10022.289139 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16500 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.827872 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 137083 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 1373885462 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 66000 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_misses 396268 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235673497 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9968.474051 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 28333.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 8.834980 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 138443 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 1380065453 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 85000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 15499631 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 15501348 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15499631 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 38794.252006 # average overall miss latency +system.cpu.dcache.demand_accesses::total 15501348 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 38830.043030 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 31264.812048 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 11736725 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 31289.255523 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 11736813 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11736725 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 145979123638 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.242774 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 11736813 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 146177056038 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.242852 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 3762906 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 3764535 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3762906 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2281142 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 46327072960 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.095600 # mshr miss rate for demand accesses +system.cpu.dcache.demand_misses::total 3764535 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2283872 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 46328842951 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.095518 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1481764 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1480663 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 511.995450 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 15499631 # number of overall (read+write) accesses +system.cpu.dcache.occ_%::1 -0.019112 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 511.995421 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::1 -9.785268 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 15501348 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15499631 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 38794.252006 # average overall miss latency +system.cpu.dcache.overall_accesses::total 15501348 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 38830.043030 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 31264.812048 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 31289.255523 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 11736725 # number of overall hits +system.cpu.dcache.overall_hits::0 11736813 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 11736725 # number of overall hits -system.cpu.dcache.overall_miss_latency 145979123638 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.242774 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 11736813 # number of overall hits +system.cpu.dcache.overall_miss_latency 146177056038 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.242852 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 3762906 # number of overall misses +system.cpu.dcache.overall_misses::0 3764535 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3762906 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2281142 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 46327072960 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.095600 # mshr miss rate for overall accesses +system.cpu.dcache.overall_misses::total 3764535 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2283872 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 46328842951 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.095518 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1481764 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2140818997 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 1480663 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2140634997 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1402110 # number of replacements -system.cpu.dcache.sampled_refs 1402622 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1401152 # number of replacements +system.cpu.dcache.sampled_refs 1401664 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.995450 # Cycle average of tags in use -system.cpu.dcache.total_refs 12382168 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 430447 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 48442278 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 42798 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 614586 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 72711050 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 37969720 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 13062350 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1643233 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 134839 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1155126 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 1236133 # DTB accesses +system.cpu.dcache.tagsinuse 507.102797 # Cycle average of tags in use +system.cpu.dcache.total_refs 12383673 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21394000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 430200 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 48440098 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 42540 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 615090 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 72709786 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 37935584 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 12980555 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1639247 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 136073 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1152246 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 1232975 # DTB accesses system.cpu.dtb.data_acv 823 # DTB access violations -system.cpu.dtb.data_hits 16770289 # DTB hits -system.cpu.dtb.data_misses 44393 # DTB misses +system.cpu.dtb.data_hits 16785642 # DTB hits +system.cpu.dtb.data_misses 44486 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 909859 # DTB read accesses -system.cpu.dtb.read_acv 588 # DTB read access violations -system.cpu.dtb.read_hits 10173052 # DTB read hits -system.cpu.dtb.read_misses 36219 # DTB read misses -system.cpu.dtb.write_accesses 326274 # DTB write accesses -system.cpu.dtb.write_acv 235 # DTB write access violations -system.cpu.dtb.write_hits 6597237 # DTB write hits -system.cpu.dtb.write_misses 8174 # DTB write misses -system.cpu.fetch.Branches 14563706 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 8997144 # Number of cache lines fetched -system.cpu.fetch.Cycles 23480265 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 455601 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 74265234 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 2366 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 967433 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.106306 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 8997144 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 7967591 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.542091 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 102272708 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.726149 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.019798 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.read_accesses 911401 # DTB read accesses +system.cpu.dtb.read_acv 582 # DTB read access violations +system.cpu.dtb.read_hits 10188595 # DTB read hits +system.cpu.dtb.read_misses 36193 # DTB read misses +system.cpu.dtb.write_accesses 321574 # DTB write accesses +system.cpu.dtb.write_acv 241 # DTB write access violations +system.cpu.dtb.write_hits 6597047 # DTB write hits +system.cpu.dtb.write_misses 8293 # DTB write misses +system.cpu.fetch.Branches 14563531 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 8983923 # Number of cache lines fetched +system.cpu.fetch.Cycles 23375540 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 455206 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 74277236 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 2199 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 956999 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.106371 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 8983923 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 7807774 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.542514 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 102147731 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.727155 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.025450 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 87829962 85.88% 85.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 1051726 1.03% 86.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 2021481 1.98% 88.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 968950 0.95% 89.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 2998384 2.93% 92.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 688876 0.67% 93.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 831559 0.81% 94.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 1217734 1.19% 95.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4664036 4.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 87794438 85.95% 85.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 1023092 1.00% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 1967534 1.93% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 960313 0.94% 89.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 2993138 2.93% 92.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 661201 0.65% 93.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 802863 0.79% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 1218814 1.19% 95.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4726338 4.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 102272708 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses::0 8997144 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8997144 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14906.743449 # average ReadReq miss latency +system.cpu.fetch.rateDist::total 102147731 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses::0 8983923 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8983923 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14917.128866 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.437092 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::0 7949609 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7949609 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15615335499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.116430 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 1047535 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1047535 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 51877 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11855735000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110664 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11909.331981 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::0 7937479 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7937479 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15609939999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.116480 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 1046444 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1046444 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 50514 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11860861000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110857 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 995658 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs 11545.454545 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_mshr_misses 995930 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs 10883.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 7.985800 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 55 # number of cycles access was blocked +system.cpu.icache.avg_refs 7.971412 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 60 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 635000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 653000 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 8997144 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 8983923 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8997144 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14906.743449 # average overall miss latency +system.cpu.icache.demand_accesses::total 8983923 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14917.128866 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11907.437092 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 7949609 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11909.331981 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 7937479 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7949609 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15615335499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.116430 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 7937479 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15609939999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.116480 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 1047535 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 1046444 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1047535 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 51877 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11855735000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.110664 # mshr miss rate for demand accesses +system.cpu.icache.demand_misses::total 1046444 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 50514 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11860861000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.110857 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 995658 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 995930 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.995649 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 509.772438 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 8997144 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.995671 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 509.783438 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 8983923 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8997144 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14906.743449 # average overall miss latency +system.cpu.icache.overall_accesses::total 8983923 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14917.128866 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11907.437092 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11909.331981 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 7949609 # number of overall hits +system.cpu.icache.overall_hits::0 7937479 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 7949609 # number of overall hits -system.cpu.icache.overall_miss_latency 15615335499 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.116430 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 7937479 # number of overall hits +system.cpu.icache.overall_miss_latency 15609939999 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.116480 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 1047535 # number of overall misses +system.cpu.icache.overall_misses::0 1046444 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1047535 # number of overall misses -system.cpu.icache.overall_mshr_hits 51877 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11855735000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.110664 # mshr miss rate for overall accesses +system.cpu.icache.overall_misses::total 1046444 # number of overall misses +system.cpu.icache.overall_mshr_hits 50514 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11860861000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.110857 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 995658 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 995930 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 994957 # number of replacements -system.cpu.icache.sampled_refs 995468 # Sample count of references to valid blocks. +system.cpu.icache.replacements 995232 # number of replacements +system.cpu.icache.sampled_refs 995743 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 509.772438 # Cycle average of tags in use -system.cpu.icache.total_refs 7949608 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 25306164000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 509.783438 # Cycle average of tags in use +system.cpu.icache.total_refs 7937478 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 25287643000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 34725081 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 9164165 # Number of branches executed -system.cpu.iew.EXEC:nop 3679313 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.420337 # Inst execution rate -system.cpu.iew.EXEC:refs 17053432 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 6620337 # Number of stores executed +system.cpu.idleCycles 34765240 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 9170733 # Number of branches executed +system.cpu.iew.EXEC:nop 3662671 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.420879 # Inst execution rate +system.cpu.iew.EXEC:refs 17068903 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 6620272 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 34505393 # num instructions consuming a value -system.cpu.iew.WB:count 56992809 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.764525 # average fanout of values written-back +system.cpu.iew.WB:consumers 34614422 # num instructions consuming a value +system.cpu.iew.WB:count 57031603 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.763117 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 26380221 # num instructions producing a value -system.cpu.iew.WB:rate 0.416013 # insts written-back per cycle -system.cpu.iew.WB:sent 57095823 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 857525 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 9717535 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 11048107 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1799892 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1045221 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 7018400 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 65886993 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 10433095 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 539578 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 57585192 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 49355 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 26414846 # num instructions producing a value +system.cpu.iew.WB:rate 0.416554 # insts written-back per cycle +system.cpu.iew.WB:sent 57130351 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 839771 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 9768928 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 11058875 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1801420 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1004974 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 7015626 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 65914650 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 10448631 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 528111 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 57623776 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 52093 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 6548 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1643233 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 548828 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 6603 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1639247 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 554420 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 307987 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 427807 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 11074 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 311339 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 434411 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 10284 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 45865 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 15487 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1739535 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 626202 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 45865 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 381050 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 476475 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.387526 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.387526 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7284 0.01% 0.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 39611417 68.15% 68.16% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 62110 0.11% 68.27% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 46318 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 18429 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1751469 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 624045 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 46318 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 408059 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 431712 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.387716 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.387716 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7287 0.01% 0.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 39633385 68.15% 68.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 62109 0.11% 68.27% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25607 0.04% 68.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3636 0.01% 68.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25611 0.04% 68.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3637 0.01% 68.32% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 10788116 18.56% 86.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 6673339 11.48% 98.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 953263 1.64% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 10799740 18.57% 86.90% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 6666948 11.46% 98.36% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 953172 1.64% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 58124772 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 433051 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007450 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 58151889 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 434913 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.007479 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 50716 11.71% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 279321 64.50% 76.21% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 103014 23.79% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 52889 12.16% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 280249 64.44% 76.60% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 101775 23.40% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 102272708 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.568331 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.133996 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 102147731 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.569292 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.137713 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 73147659 71.52% 71.52% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 14648372 14.32% 85.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 6417102 6.27% 92.12% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 3925012 3.84% 95.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 2528533 2.47% 98.43% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 1035489 1.01% 99.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 441110 0.43% 99.87% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 106525 0.10% 99.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 22906 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 73060847 71.52% 71.52% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 14641510 14.33% 85.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 6377407 6.24% 92.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 3918998 3.84% 95.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 2506307 2.45% 98.39% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 1046173 1.02% 99.42% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 456673 0.45% 99.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 116088 0.11% 99.98% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 23728 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 102272708 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.424275 # Inst issue rate -system.cpu.iq.iqInstsAdded 60155940 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 58124772 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 2051740 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8691644 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 34825 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1383953 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4676225 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 102147731 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.424736 # Inst issue rate +system.cpu.iq.iqInstsAdded 60199205 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 58151889 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 2052774 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 8775393 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 35779 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 1385007 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4703772 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1303750 # ITB accesses -system.cpu.itb.fetch_acv 951 # ITB acv -system.cpu.itb.fetch_hits 1264322 # ITB hits -system.cpu.itb.fetch_misses 39428 # ITB misses +system.cpu.itb.fetch_accesses 1302209 # ITB accesses +system.cpu.itb.fetch_acv 948 # ITB acv +system.cpu.itb.fetch_hits 1264828 # ITB hits +system.cpu.itb.fetch_misses 37381 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -457,51 +459,51 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175681 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6794 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175662 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6793 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5221 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5220 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192652 # number of callpals executed +system.cpu.kern.callpal::total 192631 # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211811 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6385 # number of quiesce instructions executed -system.cpu.kern.ipl_count::0 74956 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 211789 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6384 # number of quiesce instructions executed +system.cpu.kern.ipl_count::0 74950 40.95% 40.95% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 237 0.13% 41.08% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1890 1.03% 42.11% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105947 57.89% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183030 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73589 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1889 1.03% 42.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105933 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183009 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73583 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73589 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149305 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1824761131000 97.72% 97.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 102621000 0.01% 97.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 392338000 0.02% 97.75% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 42106013000 2.25% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1867362103000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981763 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1889 1.27% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73583 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149292 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1824774879500 97.72% 97.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 102464000 0.01% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 392165500 0.02% 97.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 42089912000 2.25% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1867359421000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981761 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694583 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 +system.cpu.kern.ipl_used::31 0.694618 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.mode_good::user 1741 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch::kernel 5972 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::kernel 5971 # number of protection mode switches +system.cpu.kern.mode_switch::user 1741 # number of protection mode switches system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu.kern.mode_switch_good::kernel 0.319826 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320047 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.400971 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 31331138500 1.68% 1.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 3191204500 0.17% 1.85% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1832839752000 98.15% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 1.401192 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 31307096500 1.68% 1.68% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 3189085000 0.17% 1.85% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1832863231500 98.15% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed @@ -534,29 +536,29 @@ system.cpu.kern.syscall::132 4 1.23% 98.77% # nu system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed system.cpu.kern.syscall::total 326 # number of syscalls executed -system.cpu.memDep0.conflictingLoads 3077147 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2881540 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 11048107 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7018400 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 136997789 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14285499 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 38258957 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1096982 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 39563718 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2259510 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 15713 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 83436015 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 68679972 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 46025419 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 12707474 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1643233 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 5244444 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7766460 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 28828338 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 1705072 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 12828278 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 257070 # count of temporary serializing insts renamed -system.cpu.timesIdled 1322055 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.memDep0.conflictingLoads 3116609 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2798105 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 11058875 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7015626 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 136912971 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14296513 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 38253474 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1101619 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 39527204 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2223744 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 15702 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 83467187 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 68675679 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 46041377 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 12627654 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1639247 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 5214289 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7787901 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 28842822 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 1704528 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 12805525 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 256634 # count of temporary serializing insts renamed +system.cpu.timesIdled 1324969 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -572,14 +574,14 @@ system.disk2.dma_write_txs 1 # Nu system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115260.104046 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115277.445087 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19939998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_mshr_miss_latency 63277.445087 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19942998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.ReadReq_misses::1 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10943998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10946998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses @@ -587,37 +589,37 @@ system.iocache.ReadReq_mshr_misses 173 # nu system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137794.253129 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137793.747738 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85790.836302 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5725626806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85790.377840 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5725605806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3564780830 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3564761780 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6161.136802 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6164.456543 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked::no_mshrs 10475 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10470 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64537908 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64541860 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137700.822145 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137700.390749 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85697.419485 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85697.034823 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5745566804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5745548804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses @@ -625,7 +627,7 @@ system.iocache.demand_misses::0 0 # nu system.iocache.demand_misses::1 41725 # number of demand (read+write) misses system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3575724828 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3575708778 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses @@ -633,20 +635,20 @@ system.iocache.demand_mshr_misses 41725 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.079213 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 1.267415 # Average occupied blocks per context +system.iocache.occ_%::1 0.079211 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 1.267376 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137700.822145 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137700.390749 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85697.419485 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85697.034823 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5745566804 # number of overall miss cycles +system.iocache.overall_miss_latency 5745548804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses @@ -654,7 +656,7 @@ system.iocache.overall_misses::0 0 # nu system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3575724828 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3575708778 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses @@ -664,137 +666,137 @@ system.iocache.overall_mshr_uncacheable_misses 0 system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.267415 # Cycle average of tags in use +system.iocache.tagsinuse 1.267376 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1716179713000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1716180121000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses::0 300582 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300582 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52361.965557 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 300511 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300511 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52374.719501 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40206.978448 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 15739064331 # number of ReadExReq miss cycles +system.l2c.ReadExReq_avg_mshr_miss_latency 40217.943752 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15739179332 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 300582 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 300582 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12085493996 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses::0 300511 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 300511 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12085934495 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 300582 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 2097743 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2097743 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52046.745492 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 300511 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 2097129 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2097129 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52047.601080 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40015.135689 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40016.046370 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1786590 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1786590 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16194501000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.148328 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 311153 # number of ReadReq misses -system.l2c.ReadReq_misses::total 311153 # number of ReadReq misses +system.l2c.ReadReq_hits::0 1785718 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1785718 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16208195500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.148494 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 311411 # number of ReadReq misses +system.l2c.ReadReq_misses::total 311411 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12450789500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.148327 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12461397000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.148493 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 311152 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 810515500 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 130274 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 130274 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 52273.201045 # average UpgradeReq miss latency +system.l2c.ReadReq_mshr_misses 311410 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 810521500 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 130096 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 130096 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 52274.462658 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.567435 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 6809838993 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.358873 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 6800698494 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 130274 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 130274 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5223670500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses::0 130096 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 130096 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5216506000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 130274 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 130096 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1116273498 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 430447 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 430447 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 430447 # number of Writeback hits -system.l2c.Writeback_hits::total 430447 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1116126498 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 430200 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 430200 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 430200 # number of Writeback hits +system.l2c.Writeback_hits::total 430200 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 4.597861 # Average number of references to valid blocks. +system.l2c.avg_refs 4.595902 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2398325 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2397640 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2398325 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52201.631966 # average overall miss latency +system.l2c.demand_accesses::total 2397640 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52208.246855 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40109.399667 # average overall mshr miss latency -system.l2c.demand_hits::0 1786590 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40115.197052 # average overall mshr miss latency +system.l2c.demand_hits::0 1785718 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1786590 # number of demand (read+write) hits -system.l2c.demand_miss_latency 31933565331 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.255068 # miss rate for demand accesses +system.l2c.demand_hits::total 1785718 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31947374832 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.255218 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 611735 # number of demand (read+write) misses +system.l2c.demand_misses::0 611922 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 611735 # number of demand (read+write) misses +system.l2c.demand_misses::total 611922 # number of demand (read+write) misses system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24536283496 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.255067 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_latency 24547331495 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.255218 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 611734 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 611921 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.090392 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.377907 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5923.908547 # Average occupied blocks per context -system.l2c.occ_blocks::1 24766.488602 # Average occupied blocks per context -system.l2c.overall_accesses::0 2398325 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.090196 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.378860 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5911.076462 # Average occupied blocks per context +system.l2c.occ_blocks::1 24828.993432 # Average occupied blocks per context +system.l2c.overall_accesses::0 2397640 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2398325 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52201.631966 # average overall miss latency +system.l2c.overall_accesses::total 2397640 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52208.246855 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40109.399667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40115.197052 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1786590 # number of overall hits +system.l2c.overall_hits::0 1785718 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1786590 # number of overall hits -system.l2c.overall_miss_latency 31933565331 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.255068 # miss rate for overall accesses +system.l2c.overall_hits::total 1785718 # number of overall hits +system.l2c.overall_miss_latency 31947374832 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.255218 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 611735 # number of overall misses +system.l2c.overall_misses::0 611922 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 611735 # number of overall misses +system.l2c.overall_misses::total 611922 # number of overall misses system.l2c.overall_mshr_hits 1 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24536283496 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.255067 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency 24547331495 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.255218 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 611734 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1926788998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 611921 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1926647998 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 396039 # number of replacements -system.l2c.sampled_refs 427720 # Sample count of references to valid blocks. +system.l2c.replacements 396067 # number of replacements +system.l2c.sampled_refs 427735 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30690.397149 # Cycle average of tags in use -system.l2c.total_refs 1966597 # Total number of references to valid blocks. -system.l2c.warmup_cycle 5645091000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119094 # number of writebacks +system.l2c.tagsinuse 30740.069893 # Cycle average of tags in use +system.l2c.total_refs 1965828 # Total number of references to valid blocks. +system.l2c.warmup_cycle 5645113000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 119080 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index ef5381d49..c1d630de3 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -353,12 +353,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE_MOESI_hammer/tests/fast/long/30.eon/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/eon +executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout index 84704aca2..d81198635 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:54 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:18:35 -M5 executing on SC2B0619 -command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/long/30.eon/alpha/tru64/o3-timing +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:43:41 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 86e5c6d82..ca20bd45c 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,340 +1,340 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 119207 # Simulator instruction rate (inst/s) -host_mem_usage 198920 # Number of bytes of host memory used -host_seconds 3150.62 # Real time elapsed on the host -host_tick_rate 42847667 # Simulator tick rate (ticks/s) +host_inst_rate 229808 # Simulator instruction rate (inst/s) +host_mem_usage 213388 # Number of bytes of host memory used +host_seconds 1634.30 # Real time elapsed on the host +host_tick_rate 82387662 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 375574819 # Number of instructions simulated -sim_seconds 0.134997 # Number of seconds simulated -sim_ticks 134996684500 # Number of ticks simulated +sim_seconds 0.134646 # Number of seconds simulated +sim_ticks 134646047500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 38296034 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 45834466 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 1077 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 5781170 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 35418150 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 62209737 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 12344504 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 35411688 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 43873215 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 1393 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 5500503 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 35240813 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 62127254 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 12478438 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 44587532 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 13163574 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 13023462 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 254545673 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.566181 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.242361 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 253935739 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.569943 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.243237 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 123085210 48.35% 48.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 50466868 19.83% 68.18% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 18758377 7.37% 75.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 19955031 7.84% 83.39% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 11844121 4.65% 88.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 8478667 3.33% 91.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 5819307 2.29% 93.66% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 2974518 1.17% 94.83% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 13163574 5.17% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 122688628 48.31% 48.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 50190176 19.76% 68.08% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 18710011 7.37% 75.45% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 19547996 7.70% 83.15% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 12735073 5.02% 88.16% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 8256826 3.25% 91.41% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 5486679 2.16% 93.57% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 3296888 1.30% 94.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 13023462 5.13% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 254545673 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 253935739 # Number of insts commited each cycle system.cpu.commit.COM:count 398664594 # Number of instructions committed system.cpu.commit.COM:loads 100651995 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 174183397 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 5776994 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 5496166 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 94782663 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 95019473 # The number of squashed insts skipped by commit system.cpu.committedInsts 375574819 # Number of Instructions Simulated system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated -system.cpu.cpi 0.718880 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.718880 # CPI: Total CPI of All Threads +system.cpu.cpi 0.717013 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.717013 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 95501309 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33016.637478 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31966.971545 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 95499596 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 56557500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses 95369422 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33035.714286 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31908.121827 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 95367714 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 56425000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1713 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 729 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 31455500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 1708 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 723 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 31429500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 984 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 985 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 30310.747349 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36196.886371 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73502716 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 545987492 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000245 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 18013 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 14704 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 119775497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 30397.287074 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36179.950785 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73502664 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 549126991 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000246 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 18065 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 14753 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 119827997 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 3309 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3249.700000 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 3312 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3499.727273 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40460.272684 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.dcache.avg_refs 40390.006697 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 32497 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 38497 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 169022038 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 30545.726047 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency -system.cpu.dcache.demand_hits 169002312 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 602544992 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 168890151 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 30625.195519 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35200.720735 # average overall mshr miss latency +system.cpu.dcache.demand_hits 168870378 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 605551991 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000117 # miss rate for demand accesses -system.cpu.dcache.demand_misses 19726 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 15433 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 151230997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_misses 19773 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 15476 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 151257497 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4293 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 4297 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.804192 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 3293.970402 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 169022038 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 30545.726047 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.804196 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 3293.985737 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 168890151 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 30625.195519 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35200.720735 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 169002312 # number of overall hits -system.cpu.dcache.overall_miss_latency 602544992 # number of overall miss cycles +system.cpu.dcache.overall_hits 168870378 # number of overall hits +system.cpu.dcache.overall_miss_latency 605551991 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000117 # miss rate for overall accesses -system.cpu.dcache.overall_misses 19726 # number of overall misses -system.cpu.dcache.overall_mshr_hits 15433 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 151230997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_misses 19773 # number of overall misses +system.cpu.dcache.overall_mshr_hits 15476 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 151257497 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4293 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 4297 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 782 # number of replacements -system.cpu.dcache.sampled_refs 4177 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 786 # number of replacements +system.cpu.dcache.sampled_refs 4181 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3293.970402 # Cycle average of tags in use -system.cpu.dcache.total_refs 169002559 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3293.985737 # Cycle average of tags in use +system.cpu.dcache.total_refs 168870618 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 635 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 18875032 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 4277 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 11323346 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 531939828 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 132443197 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 101952317 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 15306974 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 12561 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1275127 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 185115437 # DTB accesses +system.cpu.dcache.writebacks 639 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 20455851 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 4411 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 11313984 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 531721678 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 132373008 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 100014717 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 15215664 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 13188 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1092163 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 184984239 # DTB accesses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_hits 185076670 # DTB hits -system.cpu.dtb.data_misses 38767 # DTB misses +system.cpu.dtb.data_hits 184965275 # DTB hits +system.cpu.dtb.data_misses 18964 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 104449499 # DTB read accesses +system.cpu.dtb.read_accesses 104315848 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 104412186 # DTB read hits -system.cpu.dtb.read_misses 37313 # DTB read misses -system.cpu.dtb.write_accesses 80665938 # DTB write accesses +system.cpu.dtb.read_hits 104298344 # DTB read hits +system.cpu.dtb.read_misses 17504 # DTB read misses +system.cpu.dtb.write_accesses 80668391 # DTB write accesses system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_hits 80664484 # DTB write hits -system.cpu.dtb.write_misses 1454 # DTB write misses -system.cpu.fetch.Branches 62209737 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 63866189 # Number of cache lines fetched -system.cpu.fetch.Cycles 169616790 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1519057 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 544903543 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 6123542 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.230412 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 63866189 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 50640538 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.018211 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 269852647 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.019263 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.001909 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 80666931 # DTB write hits +system.cpu.dtb.write_misses 1460 # DTB write misses +system.cpu.fetch.Branches 62127254 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 63793845 # Number of cache lines fetched +system.cpu.fetch.Cycles 167246591 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1555705 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 544184292 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 5877257 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.230706 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 63793845 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 47890126 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.020796 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 269151403 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.021852 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.019136 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 164102333 60.81% 60.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 12367121 4.58% 65.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 12410556 4.60% 69.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 6615129 2.45% 72.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 15923029 5.90% 78.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 8709903 3.23% 81.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 6580254 2.44% 84.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 4007808 1.49% 85.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 39136514 14.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 165698966 61.56% 61.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 11106934 4.13% 65.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 11530416 4.28% 69.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 6307474 2.34% 72.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 14437862 5.36% 77.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 9686725 3.60% 81.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 7134176 2.65% 83.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 3886825 1.44% 85.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 39362025 14.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269852647 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 63866189 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 32249.018798 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 30883.598563 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 63861348 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 156117500 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 269151403 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 63793845 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 32214.491857 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 30831.032720 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 63788994 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 156272500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 4841 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 945 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 120322500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 4851 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 939 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 120611000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3896 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 3912 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 16391.516427 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 16305.980061 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 63866189 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 32249.018798 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 30883.598563 # average overall mshr miss latency -system.cpu.icache.demand_hits 63861348 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 156117500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 63793845 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 32214.491857 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 30831.032720 # average overall mshr miss latency +system.cpu.icache.demand_hits 63788994 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 156272500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses -system.cpu.icache.demand_misses 4841 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 945 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 120322500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 4851 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 939 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 120611000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3896 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 3912 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.890401 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1823.540410 # Average occupied blocks per context -system.cpu.icache.overall_accesses 63866189 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 32249.018798 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 30883.598563 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.890533 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1823.811736 # Average occupied blocks per context +system.cpu.icache.overall_accesses 63793845 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 32214.491857 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 30831.032720 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 63861348 # number of overall hits -system.cpu.icache.overall_miss_latency 156117500 # number of overall miss cycles +system.cpu.icache.overall_hits 63788994 # number of overall hits +system.cpu.icache.overall_miss_latency 156272500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses -system.cpu.icache.overall_misses 4841 # number of overall misses -system.cpu.icache.overall_mshr_hits 945 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 120322500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 4851 # number of overall misses +system.cpu.icache.overall_mshr_hits 939 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 120611000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3896 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 3912 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 1975 # number of replacements -system.cpu.icache.sampled_refs 3896 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1991 # number of replacements +system.cpu.icache.sampled_refs 3912 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1823.540410 # Cycle average of tags in use -system.cpu.icache.total_refs 63861348 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1823.811736 # Cycle average of tags in use +system.cpu.icache.total_refs 63788994 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 140725 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 50976851 # Number of branches executed -system.cpu.iew.EXEC:nop 27164335 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.553144 # Inst execution rate -system.cpu.iew.EXEC:refs 191842297 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 80676625 # Number of stores executed +system.cpu.idleCycles 140695 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 51026412 # Number of branches executed +system.cpu.iew.EXEC:nop 27112711 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.557485 # Inst execution rate +system.cpu.iew.EXEC:refs 191688570 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 80679099 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 285463485 # num instructions consuming a value -system.cpu.iew.WB:count 415481237 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.703314 # average fanout of values written-back +system.cpu.iew.WB:consumers 288216530 # num instructions consuming a value +system.cpu.iew.WB:count 415792778 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.699054 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 200770520 # num instructions producing a value -system.cpu.iew.WB:rate 1.538857 # insts written-back per cycle -system.cpu.iew.WB:sent 416287464 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 6390313 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2178518 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 124841223 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 6302760 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 92324076 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 493447669 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 111165672 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10261544 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 419338652 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 25079 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 201478800 # num instructions producing a value +system.cpu.iew.WB:rate 1.544021 # insts written-back per cycle +system.cpu.iew.WB:sent 416379790 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 6053312 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2368258 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 124922222 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 241 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 6336167 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 92376215 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 493684492 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 111009471 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9414741 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 419418502 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 122120 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 23746 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 15306974 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 341836 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 26143 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 15215664 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 517890 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 8734674 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2193 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 33 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 8752772 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 41071 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 436213 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 176181 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 24189228 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 18792674 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 436213 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 847804 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 5542509 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.391052 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.391052 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 605872 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 176126 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 24270227 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 18844813 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 605872 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1054390 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 4998922 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.394674 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.394674 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 166319014 38.71% 38.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 2152935 0.50% 39.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 39.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 35077566 8.17% 47.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 7830879 1.82% 49.21% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2898460 0.67% 49.89% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 16788316 3.91% 53.79% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 1569716 0.37% 54.16% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.16% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 113503270 26.42% 80.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 83426459 19.42% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 166405736 38.80% 38.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 2152798 0.50% 39.31% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 34694447 8.09% 47.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 7781263 1.81% 49.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2950957 0.69% 49.91% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 16800389 3.92% 53.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 1571056 0.37% 54.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 113131674 26.38% 80.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 83311342 19.43% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 429600196 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 10457046 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.024341 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 428833243 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 10058147 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.023455 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 40640 0.39% 0.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 76056 0.73% 1.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 13381 0.13% 1.24% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 12891 0.12% 1.37% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 1723474 16.48% 17.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 1473560 14.09% 31.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 31.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 5907144 56.49% 88.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 1209900 11.57% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 25860 0.26% 0.26% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.26% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.26% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 93260 0.93% 1.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 5650 0.06% 1.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 7446 0.07% 1.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 1317455 13.10% 14.41% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 1454078 14.46% 28.87% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 28.87% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 5920939 58.87% 87.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 1233459 12.26% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 269852647 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.591981 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.720906 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 269151403 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.593279 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.717169 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 99465935 36.86% 36.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 57766030 21.41% 58.27% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 39984554 14.82% 73.08% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 29664959 10.99% 84.08% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 23966120 8.88% 92.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 10452563 3.87% 96.83% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 5712016 2.12% 98.95% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 2252970 0.83% 99.78% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 587500 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 98731931 36.68% 36.68% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 57661044 21.42% 58.11% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 40586976 15.08% 73.19% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 29421704 10.93% 84.12% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 23908046 8.88% 93.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 10239078 3.80% 96.80% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 5871323 2.18% 98.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 2172785 0.81% 99.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 558516 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 269852647 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.591151 # Inst issue rate -system.cpu.iq.iqInstsAdded 466283095 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 429600196 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 89615992 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 918381 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 68228113 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 269151403 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.592446 # Inst issue rate +system.cpu.iq.iqInstsAdded 466571540 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 428833243 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 241 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 89966373 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 863763 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 26 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 69307198 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 63866476 # ITB accesses +system.cpu.itb.fetch_accesses 63794154 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 63866189 # ITB hits -system.cpu.itb.fetch_misses 287 # ITB misses +system.cpu.itb.fetch_hits 63793845 # ITB hits +system.cpu.itb.fetch_misses 309 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -343,106 +343,106 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 3197 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34596.340006 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31467.625899 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 110604499 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 3200 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34587.968437 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31457.812500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 110681499 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 3197 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 100602000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 3200 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 100665000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 3197 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 4876 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34359.867330 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31168.325041 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 655 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 145033000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.865669 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4221 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 131561500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.865669 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4221 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 3200 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 4893 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34357.615894 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31171.594134 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 665 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 145264000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.864092 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4228 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 131793500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.864092 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 4228 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 119 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34441.176471 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31285.714286 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 4098500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34466.386555 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31289.915966 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 4101500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 119 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3723000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3723500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 119 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 635 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 635 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3000 # average number of cycles each access was blocked +system.cpu.l2cache.Writeback_accesses 639 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 639 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2666.666667 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.130240 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 0.131910 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 6000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 8000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 8073 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34461.782017 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31297.317336 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 655 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 255637499 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.918865 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7418 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 8093 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34456.852316 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31294.897684 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 665 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 255945499 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.917830 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7428 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 232163500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.918865 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7418 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 232458500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.917830 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7428 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.106709 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.011557 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 3496.652993 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 378.690415 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 8073 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34461.782017 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31297.317336 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.106843 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.011587 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 3501.040941 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 379.684950 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 8093 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34456.852316 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31294.897684 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 655 # number of overall hits -system.cpu.l2cache.overall_miss_latency 255637499 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.918865 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7418 # number of overall misses +system.cpu.l2cache.overall_hits 665 # number of overall hits +system.cpu.l2cache.overall_miss_latency 255945499 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.917830 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7428 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 232163500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.918865 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7418 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 232458500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.917830 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7428 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 14 # number of replacements -system.cpu.l2cache.sampled_refs 4676 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 15 # number of replacements +system.cpu.l2cache.sampled_refs 4685 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3875.343408 # Cycle average of tags in use -system.cpu.l2cache.total_refs 609 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3880.725891 # Cycle average of tags in use +system.cpu.l2cache.total_refs 618 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 73961217 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 54131405 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 124841223 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 92324076 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 269993372 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 8452992 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingLoads 74849853 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 55363768 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 124922222 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 92376215 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 269292098 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 9673248 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1780176 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 137359458 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 7392558 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:IQFullEvents 1504479 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 137416112 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 8012015 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 684397837 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 518816398 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 335732022 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 97960614 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 15306974 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 10399659 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 76199681 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 372950 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 37950 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 22290547 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 251 # count of temporary serializing insts renamed -system.cpu.timesIdled 3086 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:RenameLookups 682754738 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 518229128 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 335302113 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 95729398 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 15215664 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 10747190 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 75769772 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 369791 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 37587 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 23404736 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 258 # count of temporary serializing insts renamed +system.cpu.timesIdled 3105 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index a58d921a8..cbeb23be8 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/perlbmk +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 6590e3c76..4e9d17041 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:45:31 -M5 executing on SC2B0619 +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:44:11 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 6efaa543d..88b7dc5dd 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,295 +1,295 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 178423 # Simulator instruction rate (inst/s) -host_mem_usage 199584 # Number of bytes of host memory used -host_seconds 10217.56 # Real time elapsed on the host -host_tick_rate 69014447 # Simulator tick rate (ticks/s) +host_inst_rate 173583 # Simulator instruction rate (inst/s) +host_mem_usage 213764 # Number of bytes of host memory used +host_seconds 10502.41 # Real time elapsed on the host +host_tick_rate 66694888 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1823043370 # Number of instructions simulated -sim_seconds 0.705159 # Number of seconds simulated -sim_ticks 705159454500 # Number of ticks simulated +sim_seconds 0.700457 # Number of seconds simulated +sim_ticks 700456762500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 240462096 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 294213603 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 3593 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 29107758 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 233918302 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 349424731 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 49888256 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 237313176 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 290294551 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 3578 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 28357853 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 231827098 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 346133867 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 49328779 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 266706457 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 68860244 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 69311011 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1310002801 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.533575 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.199105 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1302157693 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.542814 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.203929 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 603585597 46.08% 46.08% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 273587005 20.88% 66.96% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 174037133 13.29% 80.24% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 65399708 4.99% 85.24% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 48333001 3.69% 88.93% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 34003110 2.60% 91.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 18481318 1.41% 92.93% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 23715685 1.81% 94.74% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 68860244 5.26% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 596380613 45.80% 45.80% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 273242120 20.98% 66.78% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 173533589 13.33% 80.11% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 65306568 5.02% 85.13% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 48690140 3.74% 88.86% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 33944722 2.61% 91.47% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 18456166 1.42% 92.89% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 23292764 1.79% 94.68% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 69311011 5.32% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1310002801 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1302157693 # Number of insts commited each cycle system.cpu.commit.COM:count 2008987604 # Number of instructions committed system.cpu.commit.COM:loads 511595302 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 722390433 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 29095954 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 28346017 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 696013930 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 686852992 # The number of squashed insts skipped by commit system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.773607 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.773607 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 6 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 465737269 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 37550.774879 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34829.991989 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 463802710 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 72644189500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.004154 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1934559 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 475266 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 50827163500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003133 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1459293 # number of ReadReq MSHR misses +system.cpu.cpi 0.768448 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.768448 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 9 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 463363512 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 37524.078898 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34794.219854 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 461428955 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 72592469500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.004175 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1934557 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 475286 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 50774196000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003149 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1459271 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 38583.618605 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36524.752250 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 210235541 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 21581939985 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 38582.382670 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36523.414699 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 210235446 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 21584913985 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.002654 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 559355 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 484574 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2731357498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 559450 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 484668 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2731293998 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 74781 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5124.928571 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 440.284636 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_misses 74782 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4879.241379 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 14500 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 438.740100 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 29 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 143498 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 18000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 141498 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 14500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 676532165 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 37782.429340 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency -system.cpu.dcache.demand_hits 674038251 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 94226129485 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.003686 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2493914 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 959840 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 53558520998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002268 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1534074 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 674158408 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 37761.475202 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34878.514626 # average overall mshr miss latency +system.cpu.dcache.demand_hits 671664401 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 94177383485 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.003699 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2494007 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 959954 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 53505489998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002276 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1534053 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999781 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4095.104513 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 676532165 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 37782.429340 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999780 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4095.099733 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 674158408 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 37761.475202 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34878.514626 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 674038251 # number of overall hits -system.cpu.dcache.overall_miss_latency 94226129485 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.003686 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2493914 # number of overall misses -system.cpu.dcache.overall_mshr_hits 959840 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 53558520998 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002268 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1534074 # number of overall MSHR misses +system.cpu.dcache.overall_hits 671664401 # number of overall hits +system.cpu.dcache.overall_miss_latency 94177383485 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.003699 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2494007 # number of overall misses +system.cpu.dcache.overall_mshr_hits 959954 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 53505489998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002276 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1534053 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1526847 # number of replacements -system.cpu.dcache.sampled_refs 1530943 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1526826 # number of replacements +system.cpu.dcache.sampled_refs 1530922 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.104513 # Cycle average of tags in use -system.cpu.dcache.total_refs 674050682 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 274499000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tagsinuse 4095.099733 # Cycle average of tags in use +system.cpu.dcache.total_refs 671676872 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 274383000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 74589 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 32190527 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 12129 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 30585324 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2936172402 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 716337474 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 561391036 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 100159084 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 45706 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 83764 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 775959987 # DTB accesses +system.cpu.decode.DECODE:BlockedCycles 32140341 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 12074 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 30417175 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 2923062124 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 711773443 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 558159581 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 98598096 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 45812 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 84328 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 772918649 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 775335043 # DTB hits -system.cpu.dtb.data_misses 624944 # DTB misses +system.cpu.dtb.data_hits 772293170 # DTB hits +system.cpu.dtb.data_misses 625479 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 516992085 # DTB read accesses +system.cpu.dtb.read_accesses 514591069 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 516404963 # DTB read hits -system.cpu.dtb.read_misses 587122 # DTB read misses -system.cpu.dtb.write_accesses 258967902 # DTB write accesses +system.cpu.dtb.read_hits 514003488 # DTB read hits +system.cpu.dtb.read_misses 587581 # DTB read misses +system.cpu.dtb.write_accesses 258327580 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 258930080 # DTB write hits -system.cpu.dtb.write_misses 37822 # DTB write misses -system.cpu.fetch.Branches 349424731 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 348447899 # Number of cache lines fetched -system.cpu.fetch.Cycles 928021937 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 4387629 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 3030218619 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 29544621 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.247763 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 348447899 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 290350352 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.148605 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1410161885 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.148845 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.029305 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 258289682 # DTB write hits +system.cpu.dtb.write_misses 37898 # DTB write misses +system.cpu.fetch.Branches 346133867 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 346369631 # Number of cache lines fetched +system.cpu.fetch.Cycles 922290632 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 4326238 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 3015904698 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 28794725 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.247077 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 346369631 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 286641955 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.152813 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1400755789 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.153055 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.032526 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 830588040 58.90% 58.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 53463106 3.79% 62.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 39766072 2.82% 65.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 63538024 4.51% 70.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 121390719 8.61% 78.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 35256321 2.50% 81.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 38761682 2.75% 83.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 6988644 0.50% 84.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 220409277 15.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 824834992 58.88% 58.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 53206817 3.80% 62.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 38924738 2.78% 65.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 62366133 4.45% 69.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 120532729 8.60% 78.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 35808657 2.56% 81.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 38526871 2.75% 83.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 7024237 0.50% 84.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 219530615 15.67% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1410161885 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 348447899 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 15851.065828 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.513514 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 348437250 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 168798000 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 1400755789 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 346369631 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 15843.963981 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11642.396973 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 346358970 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 168912500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000031 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 10649 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 881 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 113685000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 10661 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 882 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 113851000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000028 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 9768 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 9779 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 35671.299140 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 35418.649146 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 348447899 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 15851.065828 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11638.513514 # average overall mshr miss latency -system.cpu.icache.demand_hits 348437250 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 168798000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 346369631 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 15843.963981 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11642.396973 # average overall mshr miss latency +system.cpu.icache.demand_hits 346358970 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 168912500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000031 # miss rate for demand accesses -system.cpu.icache.demand_misses 10649 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 881 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 113685000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 10661 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 882 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 113851000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 9768 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 9779 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.788136 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1614.102824 # Average occupied blocks per context -system.cpu.icache.overall_accesses 348447899 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 15851.065828 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11638.513514 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.788131 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1614.092315 # Average occupied blocks per context +system.cpu.icache.overall_accesses 346369631 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 15843.963981 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11642.396973 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 348437250 # number of overall hits -system.cpu.icache.overall_miss_latency 168798000 # number of overall miss cycles +system.cpu.icache.overall_hits 346358970 # number of overall hits +system.cpu.icache.overall_miss_latency 168912500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000031 # miss rate for overall accesses -system.cpu.icache.overall_misses 10649 # number of overall misses -system.cpu.icache.overall_mshr_hits 881 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 113685000 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 10661 # number of overall misses +system.cpu.icache.overall_mshr_hits 882 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 113851000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 9768 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 9779 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 8097 # number of replacements -system.cpu.icache.sampled_refs 9768 # Sample count of references to valid blocks. +system.cpu.icache.replacements 8106 # number of replacements +system.cpu.icache.sampled_refs 9779 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1614.102824 # Cycle average of tags in use -system.cpu.icache.total_refs 348437250 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1614.092315 # Cycle average of tags in use +system.cpu.icache.total_refs 346358970 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 157025 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 274534145 # Number of branches executed -system.cpu.iew.EXEC:nop 329178061 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.421117 # Inst execution rate -system.cpu.iew.EXEC:refs 776495503 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 258968900 # Number of stores executed +system.cpu.idleCycles 157737 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 273840918 # Number of branches executed +system.cpu.iew.EXEC:nop 328413541 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.427157 # Inst execution rate +system.cpu.iew.EXEC:refs 773454371 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 258328581 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1631503179 # num instructions consuming a value -system.cpu.iew.WB:count 2002130585 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.696431 # average fanout of values written-back +system.cpu.iew.WB:consumers 1628963056 # num instructions consuming a value +system.cpu.iew.WB:count 1998305294 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.696273 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1136229268 # num instructions producing a value -system.cpu.iew.WB:rate 1.419630 # insts written-back per cycle -system.cpu.iew.WB:sent 2003425032 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 31680133 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 3459468 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 655954745 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 57 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 62130 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 303651290 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2715209778 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 517526603 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 85279852 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2004227953 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 131519 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1134203072 # num instructions producing a value +system.cpu.iew.WB:rate 1.426430 # insts written-back per cycle +system.cpu.iew.WB:sent 1999262446 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 30877558 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 3458881 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 652332333 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 67 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 52328 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 302847672 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2706062248 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 515125790 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 84024827 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1999323821 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 131467 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 3361 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 100159084 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 141229 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 2941 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 98598096 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 141241 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 64 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 50663539 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 152 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 63 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 50635810 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 214 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 3589 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 4102 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 144359443 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 92856159 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 3589 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 816990 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 30863143 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.292646 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.292646 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 3618 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 4111 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 140737031 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 92052541 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 3618 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 787831 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 30089727 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.301325 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.301325 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1204412678 57.64% 57.64% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 17591 0.00% 57.64% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.64% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 27851349 1.33% 58.97% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 8254694 0.40% 59.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204646 0.34% 59.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 59.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 557993260 26.70% 86.42% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 283770831 13.58% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1201800948 57.69% 57.69% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 17591 0.00% 57.69% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.69% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 27851361 1.34% 59.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 8254692 0.40% 59.42% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204646 0.35% 59.77% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 59.77% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.77% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.77% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 555085010 26.64% 86.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 283131644 13.59% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 2089507805 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 37093546 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.017752 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 2083348648 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 37044117 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.017781 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 8291 0.02% 0.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 7263 0.02% 0.02% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.02% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.02% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.02% # attempts to use FU when none available @@ -298,43 +298,43 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.02% # at system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.02% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.02% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 28032977 75.57% 75.60% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 9052278 24.40% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 27908776 75.34% 75.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 9128078 24.64% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1410161885 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.481750 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.637343 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1400755789 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.487303 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.636763 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 537278436 38.10% 38.10% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 285217724 20.23% 58.33% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 273546804 19.40% 77.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 154810620 10.98% 88.70% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 63341841 4.49% 93.19% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 51438515 3.65% 96.84% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 32491109 2.30% 99.15% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 9036668 0.64% 99.79% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 3000168 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 530170444 37.85% 37.85% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 284246633 20.29% 58.14% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 272843485 19.48% 77.62% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 155156600 11.08% 88.70% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 63055400 4.50% 93.20% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 50914622 3.63% 96.83% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 32393130 2.31% 99.15% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 9012045 0.64% 99.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 2963430 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1410161885 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.481585 # Inst issue rate -system.cpu.iq.iqInstsAdded 2386031660 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2089507805 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 562621267 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 12403599 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 516017454 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 1400755789 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.487136 # Inst issue rate +system.cpu.iq.iqInstsAdded 2377648640 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2083348648 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 67 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 554578210 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 12403574 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 512095612 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 348448092 # ITB accesses +system.cpu.itb.fetch_accesses 346369835 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 348447899 # ITB hits -system.cpu.itb.fetch_misses 193 # ITB misses +system.cpu.itb.fetch_hits 346369631 # ITB hits +system.cpu.itb.fetch_misses 204 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -343,106 +343,106 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 71650 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 35090.990928 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32065.847872 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2514269500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 71651 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 35090.884984 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32065.644583 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2514297000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 71650 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297518000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 71651 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297535500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 71650 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1469061 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34325.576147 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.455515 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 28934 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 49433189000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.980304 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1440127 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 44644593000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980304 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1440127 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 3137 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34069.333758 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31036.659229 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 106875500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 71651 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1469050 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34290.352977 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.454128 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 28927 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 49382326000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.980309 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1440123 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 44644467000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980309 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1440123 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 3136 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34061.702806 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31036.830357 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 106817500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 3137 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 97362000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 3136 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 97331500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 3137 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 3136 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 74589 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8187.500000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6458.333333 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.023462 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 0.023460 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 65500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 77500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 1540711 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34361.852641 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.949313 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 28934 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 51947458500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.981220 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 1511777 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 1540701 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34328.294441 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.939162 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 28927 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 51896623000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.981225 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1511774 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 46942111000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981220 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 1511777 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 46942002500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981225 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1511774 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.927694 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.046416 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 30398.691034 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1520.954518 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 1540711 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34361.852641 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.949313 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.927763 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.046370 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 30400.923469 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 1519.457016 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 1540701 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34328.294441 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.939162 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 28934 # number of overall hits -system.cpu.l2cache.overall_miss_latency 51947458500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.981220 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 1511777 # number of overall misses +system.cpu.l2cache.overall_hits 28927 # number of overall hits +system.cpu.l2cache.overall_miss_latency 51896623000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.981225 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1511774 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 46942111000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981220 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 1511777 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 46942002500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981225 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1511774 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 1474251 # number of replacements -system.cpu.l2cache.sampled_refs 1506809 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 1474248 # number of replacements +system.cpu.l2cache.sampled_refs 1506806 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31919.645552 # Cycle average of tags in use -system.cpu.l2cache.total_refs 35353 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 31920.380484 # Cycle average of tags in use +system.cpu.l2cache.total_refs 35349 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 66899 # number of writebacks -system.cpu.memDep0.conflictingLoads 118847053 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 21034746 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 655954745 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 303651290 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 1410318910 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 20063964 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingLoads 118618588 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21042992 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 652332333 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 302847672 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 1400913526 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 20115016 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 687776 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 730652071 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 11530186 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 16 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 3303379014 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2836019296 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1886227369 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 545599397 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 100159084 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 13665899 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 501258299 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 21470 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 2842 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 27803045 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 61 # count of temporary serializing insts renamed -system.cpu.timesIdled 4055 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 673890 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 725392322 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 11324949 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 18 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 3294871470 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2827359257 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 1880881832 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 543088621 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 98598096 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 13538505 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 495912762 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 23229 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 2930 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 27590681 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 73 # count of temporary serializing insts renamed +system.cpu.timesIdled 4075 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout index 0d46bf33c..19b19681f 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 10 2010 23:43:53 -M5 revision 1633bdfc3b0a+ 7062+ default qtip regression_update tip -M5 started Apr 10 2010 23:43:54 -M5 executing on zooks +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:54:51 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index c2f55abfb..f3687e9fd 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,60 +1,60 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 44191 # Simulator instruction rate (inst/s) -host_mem_usage 166876 # Number of bytes of host memory used -host_seconds 1999.07 # Real time elapsed on the host -host_tick_rate 53020649 # Simulator tick rate (ticks/s) +host_inst_rate 55482 # Simulator instruction rate (inst/s) +host_mem_usage 223108 # Number of bytes of host memory used +host_seconds 1592.24 # Real time elapsed on the host +host_tick_rate 66617861 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated -sim_seconds 0.105992 # Number of seconds simulated -sim_ticks 105992011500 # Number of ticks simulated +sim_seconds 0.106071 # Number of seconds simulated +sim_ticks 106071426500 # Number of ticks simulated system.cpu.AGEN-Unit.instReqsProcessed 35224018 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.BTBHits 4998012 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 12031092 # Number of BTB lookups -system.cpu.Branch-Predictor.RASInCorrect 1659840 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 10756510 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 8920903 # Number of conditional branches predicted -system.cpu.Branch-Predictor.instReqsProcessed 88349561 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.lookups 13755144 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 5445744 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 8309400 # Number of Branches Predicted As Taken (True). -system.cpu.Branch-Predictor.usedRAS 1659840 # Number of times the RAS was used to get a target. -system.cpu.Decode-Unit.instReqsProcessed 88349561 # Number of Instructions Requests that completed in this resource. +system.cpu.Branch-Predictor.BTBHits 4715785 # Number of BTB hits +system.cpu.Branch-Predictor.BTBLookups 11658962 # Number of BTB lookups +system.cpu.Branch-Predictor.RASInCorrect 1659877 # Number of incorrect RAS predictions. +system.cpu.Branch-Predictor.condIncorrect 10683155 # Number of conditional branches incorrect +system.cpu.Branch-Predictor.condPredicted 8920904 # Number of conditional branches predicted +system.cpu.Branch-Predictor.instReqsProcessed 88352585 # Number of Instructions Requests that completed in this resource. +system.cpu.Branch-Predictor.lookups 13755709 # Number of BP lookups +system.cpu.Branch-Predictor.predictedNotTaken 5728293 # Number of Branches Predicted As Not Taken (False). +system.cpu.Branch-Predictor.predictedTaken 8027416 # Number of Branches Predicted As Taken (True). +system.cpu.Branch-Predictor.usedRAS 1659877 # Number of times the RAS was used to get a target. +system.cpu.Decode-Unit.instReqsProcessed 88352585 # Number of Instructions Requests that completed in this resource. system.cpu.Execution-Unit.cyclesExecuted 53070972 # Number of Cycles Execution Unit was used. system.cpu.Execution-Unit.instReqsProcessed 53075554 # Number of Instructions Requests that completed in this resource. -system.cpu.Execution-Unit.predictedNotTakenIncorrect 147919 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 2299191 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Execution-Unit.utilization 0.250354 # Utilization of Execution Unit (cycles / totalCycles). -system.cpu.Fetch-Seq-Unit.instReqsProcessed 187445797 # Number of Instructions Requests that completed in this resource. +system.cpu.Execution-Unit.predictedNotTakenIncorrect 393312 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedTakenIncorrect 2262427 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.Execution-Unit.utilization 0.250166 # Utilization of Execution Unit (cycles / totalCycles). +system.cpu.Fetch-Seq-Unit.instReqsProcessed 187375293 # Number of Instructions Requests that completed in this resource. system.cpu.Graduation-Unit.instReqsProcessed 88340673 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.divInstReqsProcessed 0 # Number of Divide Requests Processed. system.cpu.Mult-Div-Unit.instReqsProcessed 82202 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.multInstReqsProcessed 41101 # Number of Multiply Requests Processed. -system.cpu.RegFile-Manager.instReqsProcessed 165543786 # Number of Instructions Requests that completed in this resource. -system.cpu.activity 85.618119 # Percentage of cycles cpu is active +system.cpu.RegFile-Manager.instReqsProcessed 165543836 # Number of Instructions Requests that completed in this resource. +system.cpu.activity 85.696841 # Percentage of cycles cpu is active system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 2.399619 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 2.399620 # CPI: Total CPI of All Threads +system.cpu.cpi 2.401417 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 2.401418 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 38174.521937 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35069.282164 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 38148.092683 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35044.037784 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2319713000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 2318107000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2131020000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2129486000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56457.935284 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53457.935284 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56431.835934 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53431.835934 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 8457003500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 8453094000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 8007624500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8003715000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -66,31 +66,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 51181.457454 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 48151.085919 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 51155.262895 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 48125.233308 # average overall mshr miss latency system.cpu.dcache.demand_hits 34679456 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10776716500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 10771201000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses system.cpu.dcache.demand_misses 210559 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 10138644500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10133201000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 210559 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995315 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4076.810579 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.995316 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4076.814935 # Average occupied blocks per context system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 51181.457454 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 48151.085919 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 51155.262895 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 48125.233308 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 34679456 # number of overall hits -system.cpu.dcache.overall_miss_latency 10776716500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 10771201000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses system.cpu.dcache.overall_misses 210559 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 10138644500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10133201000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 210559 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -98,9 +98,9 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 200248 # number of replacements system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4076.810579 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4076.814935 # Cycle average of tags in use system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 842828000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 843108000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147714 # number of writebacks system.cpu.dcache_port.instReqsProcessed 35224018 # Number of Instructions Requests that completed in this resource. system.cpu.dtb.data_accesses 34987415 # DTB accesses @@ -119,74 +119,74 @@ system.cpu.dtb.write_accesses 14620629 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 14613377 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses -system.cpu.icache.ReadReq_accesses 99095978 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 18966.643194 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 15796.304290 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 99013611 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1562225500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 99022487 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 18976.095303 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 15795.359051 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 98940181 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1561846500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000831 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 82367 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 3600 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1244227500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000795 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 78767 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_misses 82306 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 3529 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1244311000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000796 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 78777 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 10833.333333 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1257.044333 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles::no_targets 10666.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1255.952638 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 32500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 32000 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 99095978 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 18966.643194 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 15796.304290 # average overall mshr miss latency -system.cpu.icache.demand_hits 99013611 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1562225500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 99022487 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 18976.095303 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 15795.359051 # average overall mshr miss latency +system.cpu.icache.demand_hits 98940181 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1561846500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000831 # miss rate for demand accesses -system.cpu.icache.demand_misses 82367 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 3600 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1244227500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000795 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 78767 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_misses 82306 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 3529 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1244311000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 78777 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.914749 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1873.406096 # Average occupied blocks per context -system.cpu.icache.overall_accesses 99095978 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 18966.643194 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 15796.304290 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.914772 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1873.453452 # Average occupied blocks per context +system.cpu.icache.overall_accesses 99022487 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 18976.095303 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 15795.359051 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 99013611 # number of overall hits -system.cpu.icache.overall_miss_latency 1562225500 # number of overall miss cycles +system.cpu.icache.overall_hits 98940181 # number of overall hits +system.cpu.icache.overall_miss_latency 1561846500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000831 # miss rate for overall accesses -system.cpu.icache.overall_misses 82367 # number of overall misses -system.cpu.icache.overall_mshr_hits 3600 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1244227500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000795 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 78767 # number of overall MSHR misses +system.cpu.icache.overall_misses 82306 # number of overall misses +system.cpu.icache.overall_mshr_hits 3529 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1244311000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 78777 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 76721 # number of replacements -system.cpu.icache.sampled_refs 78767 # Sample count of references to valid blocks. +system.cpu.icache.replacements 76731 # number of replacements +system.cpu.icache.sampled_refs 78777 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1873.406096 # Cycle average of tags in use -system.cpu.icache.total_refs 99013611 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1873.453452 # Cycle average of tags in use +system.cpu.icache.total_refs 98940181 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache_port.instReqsProcessed 99096235 # Number of Instructions Requests that completed in this resource. -system.cpu.idleCycles 30487290 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.416733 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.416733 # IPC: Total IPC of All Threads +system.cpu.icache_port.instReqsProcessed 99022707 # Number of Instructions Requests that completed in this resource. +system.cpu.idleCycles 30343130 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.416421 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.416421 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 99100019 # ITB accesses +system.cpu.itb.fetch_accesses 99026503 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 99095980 # ITB hits -system.cpu.itb.fetch_misses 4039 # ITB misses +system.cpu.itb.fetch_hits 99022489 # ITB hits +system.cpu.itb.fetch_misses 4014 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -196,28 +196,28 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52468.598950 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52441.606653 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.219393 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 7533336500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 7529461000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743151500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 139533 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52305.583032 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_accesses 139543 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52270.364151 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40004.968830 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 96062 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2273776000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.311546 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_hits 96072 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 2272245000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.311524 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 43471 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 1739056000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.311546 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.311524 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 43471 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51892.920354 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51886.725664 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40002.654867 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 322514500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 322476000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248616500 # number of UpgradeReq MSHR miss cycles @@ -227,73 +227,73 @@ system.cpu.l2cache.Writeback_accesses 147714 # nu system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.642674 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.642732 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 283111 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52430.713342 # average overall miss latency +system.cpu.l2cache.demand_accesses 283121 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52401.809152 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40001.323183 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 96062 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9807112500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.660691 # miss rate for demand accesses +system.cpu.l2cache.demand_hits 96072 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 9801706000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.660668 # miss rate for demand accesses system.cpu.l2cache.demand_misses 187049 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_miss_latency 7482207500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.660691 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.660668 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 187049 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.occ_%::0 0.083121 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.474048 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2723.711212 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15533.588628 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 283111 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52430.713342 # average overall miss latency +system.cpu.l2cache.occ_%::1 0.474053 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2723.703646 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15533.764861 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 283121 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52401.809152 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40001.323183 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 96062 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9807112500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.660691 # miss rate for overall accesses +system.cpu.l2cache.overall_hits 96072 # number of overall hits +system.cpu.l2cache.overall_miss_latency 9801706000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.660668 # miss rate for overall accesses system.cpu.l2cache.overall_misses 187049 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_miss_latency 7482207500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.660691 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.660668 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 187049 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 147734 # number of replacements system.cpu.l2cache.sampled_refs 172940 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18257.299840 # Cycle average of tags in use -system.cpu.l2cache.total_refs 111144 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18257.468506 # Cycle average of tags in use +system.cpu.l2cache.total_refs 111154 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 120636 # number of writebacks -system.cpu.numCycles 211984025 # number of cpu cycles simulated -system.cpu.runCycles 181496735 # Number of cycles cpu stages are processed. +system.cpu.numCycles 212142855 # number of cpu cycles simulated +system.cpu.runCycles 181799725 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 112884006 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 99100019 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 46.748815 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 123634464 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 88349561 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 41.677462 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 122168239 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 113116352 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 99026503 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 46.679160 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 123790270 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 88352585 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 41.647684 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 122327069 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 89815786 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 42.369129 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 176752755 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.utilization 42.337408 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 176911585 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 35231270 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 16.619776 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 123643352 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 16.607333 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 123802182 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 88340673 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 41.673269 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 211983985 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-4.utilization 41.642069 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 212142815 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.timesIdled 1 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 821bc3ec9..978c677a5 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout index dddba13b1..361003678 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:28:19 -M5 executing on SC2B0619 +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:52:23 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index d2ad10f5b..182c67d63 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,340 +1,340 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 172212 # Simulator instruction rate (inst/s) -host_mem_usage 201796 # Number of bytes of host memory used -host_seconds 462.17 # Real time elapsed on the host -host_tick_rate 58711424 # Simulator tick rate (ticks/s) +host_inst_rate 184348 # Simulator instruction rate (inst/s) +host_mem_usage 216288 # Number of bytes of host memory used +host_seconds 431.75 # Real time elapsed on the host +host_tick_rate 62947203 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated -sim_seconds 0.027135 # Number of seconds simulated -sim_ticks 27134794500 # Number of ticks simulated +sim_seconds 0.027177 # Number of seconds simulated +sim_ticks 27177245500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 8039250 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 14256744 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 34579 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 452707 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 10551565 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 16249463 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 8069483 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 14149168 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 34397 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 454823 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 10566027 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 16273288 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1942431 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3320894 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 3319944 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 51751169 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.707028 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.326549 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 51827032 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.704529 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.326613 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 22506446 43.49% 43.49% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 11357579 21.95% 65.44% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 5114502 9.88% 75.32% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 3560855 6.88% 82.20% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 2552504 4.93% 87.13% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 1532717 2.96% 90.09% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 1008933 1.95% 92.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 796739 1.54% 93.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 3320894 6.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 22597378 43.60% 43.60% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 11350095 21.90% 65.50% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 5102840 9.85% 75.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 3559000 6.87% 82.21% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 2567186 4.95% 87.17% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 1515845 2.92% 90.09% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 1002832 1.93% 92.03% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 811912 1.57% 93.59% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 3319944 6.41% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 51751169 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 51827032 # Number of insts commited each cycle system.cpu.commit.COM:count 88340672 # Number of instructions committed system.cpu.commit.COM:loads 20379399 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 35224018 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 358406 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 359545 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8296858 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8408904 # The number of squashed insts skipped by commit system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.681849 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.681849 # CPI: Total CPI of All Threads +system.cpu.cpi 0.682916 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.682916 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 20425513 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 30386.330224 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20952.491225 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20275869 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4547132000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.007326 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 149644 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 88108 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1289332500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003013 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61536 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_accesses 20447523 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 30372.255855 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20950.835512 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 20297704 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4550341000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007327 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 149819 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 88240 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1290131500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 61579 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 32256.481584 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35750.692621 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 13563056 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 33879659994 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.071874 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1050321 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 900532 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 5355060497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 32253.546396 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35751.235092 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 13562946 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 33880124994 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.071881 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1050431 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 900647 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 5354962997 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 149789 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3166.333333 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 149784 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3083 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 165.103737 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 165.176300 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 18998 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 18498 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 35038890 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 32023.260673 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency -system.cpu.dcache.demand_hits 33838925 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 38426791994 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.034247 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1199965 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 988640 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 6644392997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.006031 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 211325 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 35060900 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32018.717762 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 31439.251416 # average overall mshr miss latency +system.cpu.dcache.demand_hits 33860650 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 38430465994 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.034233 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1200250 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 988887 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 6645094497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.006028 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 211363 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995440 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4077.324152 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 35038890 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 32023.260673 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.995485 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4077.505020 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 35060900 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32018.717762 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 31439.251416 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 33838925 # number of overall hits -system.cpu.dcache.overall_miss_latency 38426791994 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.034247 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1199965 # number of overall misses -system.cpu.dcache.overall_mshr_hits 988640 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 6644392997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.006031 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 211325 # number of overall MSHR misses +system.cpu.dcache.overall_hits 33860650 # number of overall hits +system.cpu.dcache.overall_miss_latency 38430465994 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.034233 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1200250 # number of overall misses +system.cpu.dcache.overall_mshr_hits 988887 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 6645094497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.006028 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 211363 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 200933 # number of replacements -system.cpu.dcache.sampled_refs 205029 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 200975 # number of replacements +system.cpu.dcache.sampled_refs 205071 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4077.324152 # Cycle average of tags in use -system.cpu.dcache.total_refs 33851054 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 183223000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 147760 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 3553993 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 95125 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3655575 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 101758318 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 28531763 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 19520694 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1290101 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 284696 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 144719 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 36599689 # DTB accesses -system.cpu.dtb.data_acv 39 # DTB access violations -system.cpu.dtb.data_hits 36425481 # DTB hits -system.cpu.dtb.data_misses 174208 # DTB misses +system.cpu.dcache.tagsinuse 4077.505020 # Cycle average of tags in use +system.cpu.dcache.total_refs 33872869 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 182118000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147751 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 3544786 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 96141 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3662025 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 101883380 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 28549595 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 19586782 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1306643 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 281833 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 145869 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 36634667 # DTB accesses +system.cpu.dtb.data_acv 32 # DTB access violations +system.cpu.dtb.data_hits 36459913 # DTB hits +system.cpu.dtb.data_misses 174754 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 21541288 # DTB read accesses -system.cpu.dtb.read_acv 37 # DTB read access violations -system.cpu.dtb.read_hits 21383020 # DTB read hits -system.cpu.dtb.read_misses 158268 # DTB read misses -system.cpu.dtb.write_accesses 15058401 # DTB write accesses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_hits 15042461 # DTB write hits -system.cpu.dtb.write_misses 15940 # DTB write misses -system.cpu.fetch.Branches 16249463 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 13386072 # Number of cache lines fetched -system.cpu.fetch.Cycles 33247230 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 153162 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 103308065 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 567637 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.299421 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 13386072 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 9981179 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.903609 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 53041270 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.947692 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.940902 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.read_accesses 21560876 # DTB read accesses +system.cpu.dtb.read_acv 29 # DTB read access violations +system.cpu.dtb.read_hits 21402283 # DTB read hits +system.cpu.dtb.read_misses 158593 # DTB read misses +system.cpu.dtb.write_accesses 15073791 # DTB write accesses +system.cpu.dtb.write_acv 3 # DTB write access violations +system.cpu.dtb.write_hits 15057630 # DTB write hits +system.cpu.dtb.write_misses 16161 # DTB write misses +system.cpu.fetch.Branches 16273288 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 13390069 # Number of cache lines fetched +system.cpu.fetch.Cycles 33318554 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 152706 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 103441312 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 571617 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.299392 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 13390069 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 10011914 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.903087 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 53133675 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.946813 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.939021 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 33206277 62.60% 62.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 1871594 3.53% 66.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 1529415 2.88% 69.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 1809626 3.41% 72.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 3985239 7.51% 79.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 1867239 3.52% 83.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 695846 1.31% 84.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 1111736 2.10% 86.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6964298 13.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 33232285 62.54% 62.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 1906283 3.59% 66.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 1507954 2.84% 68.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 1896878 3.57% 72.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 3940139 7.42% 79.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 1882924 3.54% 83.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 690153 1.30% 84.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 1104079 2.08% 86.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6972980 13.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53041270 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 13386072 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9527.179672 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6037.865388 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 13297366 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 845118000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.006627 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 88706 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 2770 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 518870000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006420 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 85936 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 53133675 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 13390069 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 9552.030813 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 6056.454886 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 13301016 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 850637000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.006651 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 89053 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 2816 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 522290500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.006440 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 86237 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 154.737488 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 154.239714 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 13386072 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9527.179672 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency -system.cpu.icache.demand_hits 13297366 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 845118000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.006627 # miss rate for demand accesses -system.cpu.icache.demand_misses 88706 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 2770 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 518870000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.006420 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 85936 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 13390069 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 9552.030813 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 6056.454886 # average overall mshr miss latency +system.cpu.icache.demand_hits 13301016 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 850637000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.006651 # miss rate for demand accesses +system.cpu.icache.demand_misses 89053 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 2816 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 522290500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.006440 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 86237 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.936032 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1916.994169 # Average occupied blocks per context -system.cpu.icache.overall_accesses 13386072 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9527.179672 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.936831 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1918.630870 # Average occupied blocks per context +system.cpu.icache.overall_accesses 13390069 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 9552.030813 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 6056.454886 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 13297366 # number of overall hits -system.cpu.icache.overall_miss_latency 845118000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.006627 # miss rate for overall accesses -system.cpu.icache.overall_misses 88706 # number of overall misses -system.cpu.icache.overall_mshr_hits 2770 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 518870000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.006420 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 85936 # number of overall MSHR misses +system.cpu.icache.overall_hits 13301016 # number of overall hits +system.cpu.icache.overall_miss_latency 850637000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.006651 # miss rate for overall accesses +system.cpu.icache.overall_misses 89053 # number of overall misses +system.cpu.icache.overall_mshr_hits 2816 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 522290500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.006440 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 86237 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 83888 # number of replacements -system.cpu.icache.sampled_refs 85935 # Sample count of references to valid blocks. +system.cpu.icache.replacements 84189 # number of replacements +system.cpu.icache.sampled_refs 86236 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1916.994169 # Cycle average of tags in use -system.cpu.icache.total_refs 13297366 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1918.630870 # Cycle average of tags in use +system.cpu.icache.total_refs 13301016 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1228320 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14745486 # Number of branches executed -system.cpu.iew.EXEC:nop 9395656 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.562957 # Inst execution rate -system.cpu.iew.EXEC:refs 36941993 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15291392 # Number of stores executed +system.cpu.idleCycles 1220817 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14763362 # Number of branches executed +system.cpu.iew.EXEC:nop 9403936 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.562245 # Inst execution rate +system.cpu.iew.EXEC:refs 36977571 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15306943 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 42302279 # num instructions consuming a value -system.cpu.iew.WB:count 84351875 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.765845 # average fanout of values written-back +system.cpu.iew.WB:consumers 42200934 # num instructions consuming a value +system.cpu.iew.WB:count 84440980 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.765693 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 32396987 # num instructions producing a value -system.cpu.iew.WB:rate 1.554312 # insts written-back per cycle -system.cpu.iew.WB:sent 84585274 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 398232 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 627293 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 23001213 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 5004 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 362338 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 16328872 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 98972097 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 21650601 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 525286 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 84821059 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 11758 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 32312963 # num instructions producing a value +system.cpu.iew.WB:rate 1.553523 # insts written-back per cycle +system.cpu.iew.WB:sent 84676788 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 400577 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 625766 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 23022182 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 5008 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 344811 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 16353481 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 99092373 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 21670628 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 531948 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 84915051 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 11175 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 8922 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1290101 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 44031 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 9016 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1306643 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 43564 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 956127 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 709 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 953335 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 730 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 16859 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1313 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2621814 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1484253 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 16859 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 106828 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 291404 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.466600 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.466600 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 19282 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1358 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 2642783 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1508862 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 19282 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 131988 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 268589 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.464309 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.464309 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 47898565 56.12% 56.12% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 42953 0.05% 56.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 47956060 56.12% 56.12% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 42959 0.05% 56.17% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 121655 0.14% 56.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 88 0.00% 56.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122104 0.14% 56.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 53 0.00% 56.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38535 0.05% 56.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 21753622 25.49% 81.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 15368770 18.01% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 122263 0.14% 56.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 86 0.00% 56.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122397 0.14% 56.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 52 0.00% 56.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38515 0.05% 56.51% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.51% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 21777529 25.49% 81.99% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 15387138 18.01% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 85346345 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 979640 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011478 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 85446999 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 982918 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011503 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 97100 9.91% 9.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 9.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 9.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 9.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 9.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 9.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 9.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 9.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 9.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 470602 48.04% 57.95% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 411938 42.05% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 100696 10.24% 10.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 10.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 446429 45.42% 55.66% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 435793 44.34% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 53041270 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.609055 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.711333 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 53133675 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.608151 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.716289 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 17563410 33.11% 33.11% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 13937999 26.28% 59.39% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 8266125 15.58% 74.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 4784809 9.02% 84.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 4627568 8.72% 92.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 2066740 3.90% 96.62% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 1112374 2.10% 98.71% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 454507 0.86% 99.57% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 227738 0.43% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 17599811 33.12% 33.12% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 14135768 26.60% 59.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 8101815 15.25% 74.98% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 4767583 8.97% 83.95% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 4587960 8.63% 92.58% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 2114458 3.98% 96.56% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 1132800 2.13% 98.69% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 463918 0.87% 99.57% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 229562 0.43% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 53041270 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.572637 # Inst issue rate -system.cpu.iq.iqInstsAdded 89571437 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 85346345 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 5004 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 9777311 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 49841 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 421 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 6793875 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 53133675 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.572032 # Inst issue rate +system.cpu.iq.iqInstsAdded 89683429 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 85446999 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 5008 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 9879316 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 48902 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 425 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 6828439 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 13412237 # ITB accesses +system.cpu.itb.fetch_accesses 13417164 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 13386072 # ITB hits -system.cpu.itb.fetch_misses 26165 # ITB misses +system.cpu.itb.fetch_hits 13390069 # ITB hits +system.cpu.itb.fetch_misses 27095 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -343,106 +343,106 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 143494 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.379953 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31233.455754 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 4927207999 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 143493 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34335.441443 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31231.837093 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 4926895499 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 143494 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4481813500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 143493 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4481550000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 143494 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 147471 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34138.973013 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.569397 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 102894 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1521813000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.302276 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 44577 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1383428000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.302276 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 44577 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 6344 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34041.535309 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31034.914880 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 215959500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 143493 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 147815 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34139.493240 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31035.309786 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 103139 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1525216000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.302243 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 44676 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1386533500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.302243 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 44676 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 6336 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34034.485480 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31031.960227 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 215642500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 6344 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 196885500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 6336 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 196618500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 6344 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 147760 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 147760 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 6336 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 147751 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 147751 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.678680 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.679657 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 2000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 290965 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34290.353106 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 102894 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6449020999 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.646370 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 188071 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 291308 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34288.918467 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31185.176623 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 103139 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 6452111499 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.645945 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 188169 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 5865241500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.646370 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 188071 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 5868083500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.645945 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 188169 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.089962 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.474123 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2947.876007 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15536.049051 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 290965 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34290.353106 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.090420 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.474090 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2962.888778 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15534.990261 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 291308 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34288.918467 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31185.176623 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 102894 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6449020999 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.646370 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 188071 # number of overall misses +system.cpu.l2cache.overall_hits 103139 # number of overall hits +system.cpu.l2cache.overall_miss_latency 6452111499 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.645945 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 188169 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 5865241500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.646370 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 188071 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 5868083500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.645945 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 188169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 148779 # number of replacements -system.cpu.l2cache.sampled_refs 173998 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 148882 # number of replacements +system.cpu.l2cache.sampled_refs 174101 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18483.925058 # Cycle average of tags in use -system.cpu.l2cache.total_refs 118089 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18497.879039 # Cycle average of tags in use +system.cpu.l2cache.total_refs 118329 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 120647 # number of writebacks -system.cpu.memDep0.conflictingLoads 12835812 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11558188 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 23001213 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16328872 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 54269590 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 2047052 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 120652 # number of writebacks +system.cpu.memDep0.conflictingLoads 12671277 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11281308 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 23022182 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16353481 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 54354492 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 2040280 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 64606 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 28934151 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1281103 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 21 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 121625306 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 100952091 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 60736832 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 19265135 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1290101 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1421430 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 8189951 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 83401 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 5265 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2801993 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 5263 # count of temporary serializing insts renamed -system.cpu.timesIdled 42538 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 60824 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 28947603 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1285549 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 34 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 121774399 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 101069730 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 60794101 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 19336245 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1306643 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1420628 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 8247220 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 82276 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 5281 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 2797354 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 5278 # count of temporary serializing insts renamed +system.cpu.timesIdled 42409 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout index 0f49fe322..c38fd9b15 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -5,11 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 10 2010 23:44:54 -M5 revision 1633bdfc3b0a+ 7062+ default qtip regression_update tip -M5 started Apr 10 2010 23:44:56 -M5 executing on zooks +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:53:58 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 3d8fcc484..bfc24ccd9 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,60 +1,60 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 45830 # Simulator instruction rate (inst/s) -host_mem_usage 156280 # Number of bytes of host memory used -host_seconds 2005.28 # Real time elapsed on the host -host_tick_rate 49263361 # Simulator tick rate (ticks/s) +host_inst_rate 58773 # Simulator instruction rate (inst/s) +host_mem_usage 210528 # Number of bytes of host memory used +host_seconds 1563.70 # Real time elapsed on the host +host_tick_rate 63236927 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated -sim_seconds 0.098787 # Number of seconds simulated -sim_ticks 98787075000 # Number of ticks simulated +sim_seconds 0.098884 # Number of seconds simulated +sim_ticks 98883816000 # Number of ticks simulated system.cpu.AGEN-Unit.instReqsProcessed 26537108 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.BTBHits 5943749 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 9141724 # Number of BTB lookups +system.cpu.Branch-Predictor.BTBHits 5701477 # Number of BTB hits +system.cpu.Branch-Predictor.BTBLookups 8843835 # Number of BTB lookups system.cpu.Branch-Predictor.RASInCorrect 1029596 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 11377435 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 7465155 # Number of conditional branches predicted -system.cpu.Branch-Predictor.instReqsProcessed 92001832 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.lookups 10240963 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 2255511 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 7985452 # Number of Branches Predicted As Taken (True). +system.cpu.Branch-Predictor.condIncorrect 11272469 # Number of conditional branches incorrect +system.cpu.Branch-Predictor.condPredicted 7465254 # Number of conditional branches predicted +system.cpu.Branch-Predictor.instReqsProcessed 92102614 # Number of Instructions Requests that completed in this resource. +system.cpu.Branch-Predictor.lookups 10241221 # Number of BP lookups +system.cpu.Branch-Predictor.predictedNotTaken 2498039 # Number of Branches Predicted As Not Taken (False). +system.cpu.Branch-Predictor.predictedTaken 7743182 # Number of Branches Predicted As Taken (True). system.cpu.Branch-Predictor.usedRAS 1029596 # Number of times the RAS was used to get a target. -system.cpu.Decode-Unit.instReqsProcessed 92001832 # Number of Instructions Requests that completed in this resource. +system.cpu.Decode-Unit.instReqsProcessed 92102614 # Number of Instructions Requests that completed in this resource. system.cpu.Execution-Unit.cyclesExecuted 64907308 # Number of Cycles Execution Unit was used. system.cpu.Execution-Unit.instReqsProcessed 64907696 # Number of Instructions Requests that completed in this resource. -system.cpu.Execution-Unit.predictedNotTakenIncorrect 78179 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 3313804 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Execution-Unit.utilization 0.328521 # Utilization of Execution Unit (cycles / totalCycles). -system.cpu.Fetch-Seq-Unit.instReqsProcessed 195282323 # Number of Instructions Requests that completed in this resource. +system.cpu.Execution-Unit.predictedNotTakenIncorrect 267967 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedTakenIncorrect 3261320 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.Execution-Unit.utilization 0.328200 # Utilization of Execution Unit (cycles / totalCycles). +system.cpu.Fetch-Seq-Unit.instReqsProcessed 195278137 # Number of Instructions Requests that completed in this resource. system.cpu.Graduation-Unit.instReqsProcessed 91903056 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.divInstReqsProcessed 0 # Number of Divide Requests Processed. system.cpu.Mult-Div-Unit.instReqsProcessed 916504 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.multInstReqsProcessed 458252 # Number of Multiply Requests Processed. -system.cpu.RegFile-Manager.instReqsProcessed 196150553 # Number of Instructions Requests that completed in this resource. -system.cpu.activity 96.136450 # Percentage of cycles cpu is active +system.cpu.RegFile-Manager.instReqsProcessed 196150546 # Number of Instructions Requests that completed in this resource. +system.cpu.activity 96.104408 # Percentage of cycles cpu is active system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 2.149810 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 2.149810 # CPI: Total CPI of All Threads +system.cpu.cpi 2.151916 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 2.151916 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 51560 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48531.578947 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 51575.789474 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48548.421053 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 24491000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 24498500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 23052500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 23060500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56135.825713 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53135.825713 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56234.265734 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53234.265734 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 104356500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 104539500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 98779500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 98962500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -66,31 +66,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55204.584404 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52198.800343 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 55286.203942 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52280.634105 # average overall mshr miss latency system.cpu.dcache.demand_hits 26494967 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 128847500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 129038000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses system.cpu.dcache.demand_misses 2334 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 121832000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 122023000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 2334 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.352013 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1441.845036 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.352005 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1441.813640 # Average occupied blocks per context system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55204.584404 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52198.800343 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55286.203942 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52280.634105 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 26494967 # number of overall hits -system.cpu.dcache.overall_miss_latency 128847500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 129038000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses system.cpu.dcache.overall_misses 2334 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 121832000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 122023000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 2334 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -98,7 +98,7 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1441.845036 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1441.813640 # Cycle average of tags in use system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 104 # number of writebacks @@ -119,73 +119,73 @@ system.cpu.dtb.write_accesses 6501126 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 6501103 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses -system.cpu.icache.ReadReq_accesses 103280491 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 27107.378354 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23969.601677 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 103271695 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 238436500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 103175523 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 27130.157283 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23970.529994 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 103166749 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 238040000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000085 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 8796 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 210 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 205803000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 8774 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 189 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 205787000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000083 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 8586 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 8585 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 2500 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 12027.916958 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 12017.093652 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 2500 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 103280491 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 27107.378354 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23969.601677 # average overall mshr miss latency -system.cpu.icache.demand_hits 103271695 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 238436500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 103175523 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 27130.157283 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23970.529994 # average overall mshr miss latency +system.cpu.icache.demand_hits 103166749 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 238040000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000085 # miss rate for demand accesses -system.cpu.icache.demand_misses 8796 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 210 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 205803000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 8774 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 189 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 205787000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000083 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 8586 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 8585 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.697585 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1428.655102 # Average occupied blocks per context -system.cpu.icache.overall_accesses 103280491 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 27107.378354 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23969.601677 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.697574 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1428.631049 # Average occupied blocks per context +system.cpu.icache.overall_accesses 103175523 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 27130.157283 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23970.529994 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 103271695 # number of overall hits -system.cpu.icache.overall_miss_latency 238436500 # number of overall miss cycles +system.cpu.icache.overall_hits 103166749 # number of overall hits +system.cpu.icache.overall_miss_latency 238040000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000085 # miss rate for overall accesses -system.cpu.icache.overall_misses 8796 # number of overall misses -system.cpu.icache.overall_mshr_hits 210 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 205803000 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 8774 # number of overall misses +system.cpu.icache.overall_mshr_hits 189 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 205787000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000083 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 8586 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 8585 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 6752 # number of replacements -system.cpu.icache.sampled_refs 8586 # Sample count of references to valid blocks. +system.cpu.icache.replacements 6751 # number of replacements +system.cpu.icache.sampled_refs 8585 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1428.655102 # Cycle average of tags in use -system.cpu.icache.total_refs 103271695 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1428.631049 # Cycle average of tags in use +system.cpu.icache.total_refs 103166749 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache_port.instReqsProcessed 103280490 # Number of Instructions Requests that completed in this resource. -system.cpu.idleCycles 7633377 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.465157 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.465157 # IPC: Total IPC of All Threads +system.cpu.icache_port.instReqsProcessed 103175522 # Number of Instructions Requests that completed in this resource. +system.cpu.idleCycles 7704221 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.464702 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.464702 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 103280539 # ITB accesses +system.cpu.itb.fetch_accesses 103175571 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 103280492 # ITB hits +system.cpu.itb.fetch_hits 103175524 # ITB hits system.cpu.itb.fetch_misses 47 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -196,28 +196,28 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52126.144165 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52230.263158 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40005.720824 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 91116500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 91298500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 69930000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 9061 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52164.544564 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40020.078355 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5998 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 159780000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.338042 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_accesses 9060 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52165.034280 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40019.915116 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5997 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 159781500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.338079 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 3063 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 122581500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338042 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency 122581000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338079 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 3063 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52220.720721 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52229.729730 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40009.009009 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 5796500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 5797500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4441000 # number of UpgradeReq MSHR miss cycles @@ -227,73 +227,73 @@ system.cpu.l2cache.Writeback_accesses 104 # nu system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.974917 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.974587 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 10809 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52150.592392 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40014.861775 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5998 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 250896500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.445092 # miss rate for demand accesses +system.cpu.l2cache.demand_accesses 10808 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52188.734151 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40014.757847 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 5997 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 251080000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.445133 # miss rate for demand accesses system.cpu.l2cache.demand_misses 4811 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 192511500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.445092 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_latency 192511000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.445133 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 4811 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.061820 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::0 0.061819 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.000419 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2025.719647 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13.727958 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 10809 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52150.592392 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40014.861775 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 2025.680452 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13.727236 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 10808 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52188.734151 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40014.757847 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5998 # number of overall hits -system.cpu.l2cache.overall_miss_latency 250896500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.445092 # miss rate for overall accesses +system.cpu.l2cache.overall_hits 5997 # number of overall hits +system.cpu.l2cache.overall_miss_latency 251080000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.445133 # miss rate for overall accesses system.cpu.l2cache.overall_misses 4811 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 192511500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.445092 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_latency 192511000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.445133 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 4811 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3030 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2039.447605 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5984 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2039.407688 # Cycle average of tags in use +system.cpu.l2cache.total_refs 5983 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 197574151 # number of cpu cycles simulated -system.cpu.runCycles 189940774 # Number of cycles cpu stages are processed. +system.cpu.numCycles 197767633 # number of cpu cycles simulated +system.cpu.runCycles 190063412 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 94293612 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 103280539 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 52.274318 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 105572319 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 92001832 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 46.565723 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 104081667 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 94592062 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 103175571 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 52.170100 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 105665019 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 92102614 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 46.571126 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 104275149 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 93492484 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 47.320200 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 171037020 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.utilization 47.273906 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 171230502 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 26537131 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 13.431479 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 105671095 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 13.418339 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 105864577 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 91903056 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 46.515729 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 197574151 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-4.utilization 46.470221 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 197767633 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 5dc5abaaf..0b7fa9656 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/twolf +executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index ce84b73e7..6a7caf9b4 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:44:07 -M5 executing on SC2B0619 +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:45:37 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 96c3646b7..92d71f0ba 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,340 +1,340 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 80276 # Simulator instruction rate (inst/s) -host_mem_usage 196620 # Number of bytes of host memory used -host_seconds 1048.63 # Real time elapsed on the host -host_tick_rate 38925589 # Simulator tick rate (ticks/s) +host_inst_rate 153450 # Simulator instruction rate (inst/s) +host_mem_usage 210984 # Number of bytes of host memory used +host_seconds 548.58 # Real time elapsed on the host +host_tick_rate 73456175 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated -sim_seconds 0.040819 # Number of seconds simulated -sim_ticks 40818658500 # Number of ticks simulated +sim_seconds 0.040297 # Number of seconds simulated +sim_ticks 40296654500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 13008791 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 16964874 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 1204 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 1946248 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 14605230 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 19468548 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1719783 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 11897638 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 15852760 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 1209 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 1887267 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 14560688 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 19536875 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1737186 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2855802 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 2907966 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 73457197 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.251110 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.949680 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 72454759 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.268420 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.963909 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 36278942 49.39% 49.39% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 18156304 24.72% 74.10% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 7455517 10.15% 84.25% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 3880419 5.28% 89.54% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 2046448 2.79% 92.32% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 1301140 1.77% 94.09% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 721823 0.98% 95.08% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 760802 1.04% 96.11% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 2855802 3.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 35335976 48.77% 48.77% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 18219580 25.15% 73.92% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 7350657 10.15% 84.06% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 3843959 5.31% 89.37% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 2026400 2.80% 92.16% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 1285963 1.77% 93.94% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 738665 1.02% 94.96% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 745593 1.03% 95.99% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 2907966 4.01% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 73457197 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 72454759 # Number of insts commited each cycle system.cpu.commit.COM:count 91903055 # Number of instructions committed system.cpu.commit.COM:loads 20034413 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 26537108 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1933797 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1874087 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 56152215 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 55786698 # The number of squashed insts skipped by commit system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.969798 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.969798 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 23402422 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 30623.414072 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32082.015810 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 23401555 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 26550500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000037 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 867 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 361 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 16233500 # number of ReadReq MSHR miss cycles +system.cpu.cpi 0.957396 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.957396 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 11 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 23323647 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 30060.090703 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32045.634921 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23322765 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 26513000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 882 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 378 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 16151000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 504 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35738.919918 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36175.579146 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6492799 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 296775991 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001277 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 8304 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 6453 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 66960997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 35743.318729 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36228.400108 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6492795 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 296955492 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001278 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 8308 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 6456 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 67094997 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000285 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1851 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2649.700000 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 1852 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4187.125000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13345.816518 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.dcache.avg_refs 13310.644643 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 26497 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 33497 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 29903525 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 35255.314688 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency -system.cpu.dcache.demand_hits 29894354 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 323326491 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000307 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9171 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6814 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 83194497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 29824750 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 35197.877258 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35333.615025 # average overall mshr miss latency +system.cpu.dcache.demand_hits 29815560 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 323468492 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000308 # miss rate for demand accesses +system.cpu.dcache.demand_misses 9190 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 6834 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 83245997 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2357 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 2356 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.356054 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1458.398369 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 29903525 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 35255.314688 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.356016 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1458.239906 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 29824750 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 35197.877258 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35333.615025 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 29894354 # number of overall hits -system.cpu.dcache.overall_miss_latency 323326491 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000307 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9171 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6814 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 83194497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 29815560 # number of overall hits +system.cpu.dcache.overall_miss_latency 323468492 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000308 # miss rate for overall accesses +system.cpu.dcache.overall_misses 9190 # number of overall misses +system.cpu.dcache.overall_mshr_hits 6834 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 83245997 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2357 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 2356 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 159 # number of replacements +system.cpu.dcache.replacements 160 # number of replacements system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1458.398369 # Cycle average of tags in use -system.cpu.dcache.total_refs 29894629 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1458.239906 # Cycle average of tags in use +system.cpu.dcache.total_refs 29815844 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 105 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 3781084 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 12597 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3039308 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 162679523 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 39569074 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 29917869 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 8071146 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 45156 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 189170 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 31911121 # DTB accesses +system.cpu.dcache.writebacks 106 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 3560307 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 13329 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3136527 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 162153476 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 39273061 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 29418237 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 8029960 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 48947 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 203154 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 31794123 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 31454022 # DTB hits -system.cpu.dtb.data_misses 457099 # DTB misses +system.cpu.dtb.data_hits 31394253 # DTB hits +system.cpu.dtb.data_misses 399870 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 24718123 # DTB read accesses +system.cpu.dtb.read_accesses 24584547 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 24262026 # DTB read hits -system.cpu.dtb.read_misses 456097 # DTB read misses -system.cpu.dtb.write_accesses 7192998 # DTB write accesses +system.cpu.dtb.read_hits 24185700 # DTB read hits +system.cpu.dtb.read_misses 398847 # DTB read misses +system.cpu.dtb.write_accesses 7209576 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 7191996 # DTB write hits -system.cpu.dtb.write_misses 1002 # DTB write misses -system.cpu.fetch.Branches 19468548 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 19230003 # Number of cache lines fetched -system.cpu.fetch.Cycles 50198038 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 519723 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 167554902 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2079596 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.238476 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 19230003 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 14728574 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.052430 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 81528343 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.055174 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.061669 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 7208553 # DTB write hits +system.cpu.dtb.write_misses 1023 # DTB write misses +system.cpu.fetch.Branches 19536875 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 19049745 # Number of cache lines fetched +system.cpu.fetch.Cycles 49533111 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 485697 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 167120080 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2034068 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.242413 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 19049745 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 13634824 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.073622 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 80484719 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.076420 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.094224 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 50560378 62.02% 62.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 3114212 3.82% 65.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 2012618 2.47% 68.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 3505366 4.30% 72.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 4590613 5.63% 78.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 1506961 1.85% 80.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 2028359 2.49% 82.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 1846743 2.27% 84.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 12363093 15.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 50001427 62.13% 62.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 3132178 3.89% 66.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 1884597 2.34% 68.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 3228306 4.01% 72.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 4370184 5.43% 77.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 1507606 1.87% 79.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 1854945 2.30% 81.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 1658454 2.06% 84.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 12847022 15.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81528343 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 19230003 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 15782.750498 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11914.180589 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 19218965 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 174210000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000574 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 11038 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 982 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 119809000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000523 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10056 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 80484719 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 19049745 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 15752.064632 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11876.097465 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 19038605 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 175478000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000585 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 11140 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 1003 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 120388000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000532 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 10137 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1911.193815 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1878.130117 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 19230003 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 15782.750498 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency -system.cpu.icache.demand_hits 19218965 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 174210000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000574 # miss rate for demand accesses -system.cpu.icache.demand_misses 11038 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 982 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 119809000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000523 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10056 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 19049745 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 15752.064632 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11876.097465 # average overall mshr miss latency +system.cpu.icache.demand_hits 19038605 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 175478000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000585 # miss rate for demand accesses +system.cpu.icache.demand_misses 11140 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 1003 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 120388000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000532 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 10137 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.753902 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1543.991602 # Average occupied blocks per context -system.cpu.icache.overall_accesses 19230003 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 15782.750498 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.755796 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1547.870707 # Average occupied blocks per context +system.cpu.icache.overall_accesses 19049745 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 15752.064632 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11876.097465 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 19218965 # number of overall hits -system.cpu.icache.overall_miss_latency 174210000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000574 # miss rate for overall accesses -system.cpu.icache.overall_misses 11038 # number of overall misses -system.cpu.icache.overall_mshr_hits 982 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 119809000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000523 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10056 # number of overall MSHR misses +system.cpu.icache.overall_hits 19038605 # number of overall hits +system.cpu.icache.overall_miss_latency 175478000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000585 # miss rate for overall accesses +system.cpu.icache.overall_misses 11140 # number of overall misses +system.cpu.icache.overall_mshr_hits 1003 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 120388000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000532 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 10137 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 8143 # number of replacements -system.cpu.icache.sampled_refs 10056 # Sample count of references to valid blocks. +system.cpu.icache.replacements 8223 # number of replacements +system.cpu.icache.sampled_refs 10137 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1543.991602 # Cycle average of tags in use -system.cpu.icache.total_refs 19218965 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1547.870707 # Cycle average of tags in use +system.cpu.icache.total_refs 19038605 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 108975 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 12812003 # Number of branches executed -system.cpu.iew.EXEC:nop 12599027 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.247521 # Inst execution rate -system.cpu.iew.EXEC:refs 31962516 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7194632 # Number of stores executed +system.cpu.idleCycles 108591 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 12897175 # Number of branches executed +system.cpu.iew.EXEC:nop 12739019 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.262855 # Inst execution rate +system.cpu.iew.EXEC:refs 31847616 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7211217 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 90937302 # num instructions consuming a value -system.cpu.iew.WB:count 99943821 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.723990 # average fanout of values written-back +system.cpu.iew.WB:consumers 91218394 # num instructions consuming a value +system.cpu.iew.WB:count 99932054 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.721984 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 65837672 # num instructions producing a value -system.cpu.iew.WB:rate 1.224242 # insts written-back per cycle -system.cpu.iew.WB:sent 100859242 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2125730 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 254811 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 33976826 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 426 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1734651 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 10628051 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 148053720 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 24767884 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2184370 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 101844271 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 121216 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 65858228 # num instructions producing a value +system.cpu.iew.WB:rate 1.239955 # insts written-back per cycle +system.cpu.iew.WB:sent 100793715 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2037312 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 220727 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 33778811 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 434 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1499848 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 10610374 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 147688610 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 24636399 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2142931 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 101777656 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 90810 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 222 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 8071146 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 160195 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 223 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 8029960 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 123733 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 849805 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2830 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 852201 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 2584 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 248254 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9784 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 13942413 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 4125356 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 248254 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 218646 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1907084 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.031143 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.031143 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 270101 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 9831 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 13744398 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 4107679 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 270101 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 440641 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1596671 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.044500 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.044500 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 64430040 61.93% 61.93% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 475055 0.46% 62.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2782164 2.67% 65.07% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 115645 0.11% 65.18% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2377276 2.29% 67.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 305748 0.29% 67.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 755245 0.73% 68.48% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 323 0.00% 68.48% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 25462424 24.48% 92.96% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 7324714 7.04% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 64410892 61.98% 61.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 474451 0.46% 62.44% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.44% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2784957 2.68% 65.12% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 114528 0.11% 65.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2385482 2.30% 67.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 305123 0.29% 67.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 755228 0.73% 68.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 324 0.00% 68.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 25350766 24.39% 92.94% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 7338829 7.06% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 104028641 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1933128 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.018583 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 103920587 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 1852625 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.017827 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 274346 14.19% 14.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 14.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 14.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 31 0.00% 14.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 14.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 6547 0.34% 14.53% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 2333 0.12% 14.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 832912 43.09% 57.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 57.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 743147 38.44% 96.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 73812 3.82% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 210356 11.35% 11.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 363 0.02% 11.37% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 3342 0.18% 11.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 2324 0.13% 11.68% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 819264 44.22% 55.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 55.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 748090 40.38% 96.28% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 68886 3.72% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 81528343 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.275981 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.540298 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 80484719 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.291184 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.543424 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 35305774 43.30% 43.30% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 18904885 23.19% 66.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 11574997 14.20% 80.69% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 6762756 8.29% 88.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 5075415 6.23% 95.21% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 2394533 2.94% 98.15% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 1208963 1.48% 99.63% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 250769 0.31% 99.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 50251 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 34420666 42.77% 42.77% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 18632497 23.15% 65.92% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 11734091 14.58% 80.50% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 6720766 8.35% 88.85% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 5079668 6.31% 95.16% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 2378591 2.96% 98.11% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 1227784 1.53% 99.64% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 245969 0.31% 99.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 44687 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 81528343 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.274278 # Inst issue rate -system.cpu.iq.iqInstsAdded 135454267 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 104028641 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 426 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 50669408 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 244059 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 47385393 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 80484719 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.289444 # Inst issue rate +system.cpu.iq.iqInstsAdded 134949157 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 103920587 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 434 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 50119883 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 297027 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 46887079 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 19230073 # ITB accesses +system.cpu.itb.fetch_accesses 19049819 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 19230003 # ITB hits -system.cpu.itb.fetch_misses 70 # ITB misses +system.cpu.itb.fetch_hits 19049745 # ITB hits +system.cpu.itb.fetch_misses 74 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -343,105 +343,105 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 1735 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34685.302594 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31521.902017 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 60179000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 1736 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34694.700461 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31523.329493 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 60230000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1735 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 54690500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 1736 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 54724500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1735 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 10561 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34278.222222 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7186 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 115689000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.319572 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3375 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 104895000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319572 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3375 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1736 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 10641 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34281.074697 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31079.421317 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7254 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 116110000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.318297 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3387 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 105266000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318297 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3387 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34390.243902 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31260.162602 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 4230000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34414.634146 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31256.097561 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 4233000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 123 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3845000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3844500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 123 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked +system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 106 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 4333.333333 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.152807 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 2.165420 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 3000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 13000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 12296 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34416.438356 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7186 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 175868000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.415582 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5110 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 12377 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34421.237556 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31229.845793 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7254 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 176340000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.413913 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5123 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 159585500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.415582 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5110 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 159990500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.413913 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5123 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.068091 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::0 0.068298 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.000414 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2231.205034 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13.564546 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 12296 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34416.438356 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 2237.998108 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13.556876 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 12377 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34421.237556 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31229.845793 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 7186 # number of overall hits -system.cpu.l2cache.overall_miss_latency 175868000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.415582 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5110 # number of overall misses +system.cpu.l2cache.overall_hits 7254 # number of overall hits +system.cpu.l2cache.overall_miss_latency 176340000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.413913 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5123 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 159585500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.415582 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5110 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 159990500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.413913 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5123 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3331 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3343 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2244.769579 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7171 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2251.554984 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7239 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 17216078 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5041116 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 33976826 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10628051 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 81637318 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 1761024 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingLoads 17229574 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5033996 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 33778811 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10610374 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 80593310 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 1589033 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 964182 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 40833183 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 973065 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 202958583 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 157334532 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 115929564 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 28833296 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 8071146 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 2024389 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 47502203 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 5305 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 457 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4572167 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 446 # count of temporary serializing insts renamed -system.cpu.timesIdled 2428 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 926186 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 40466713 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 962025 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 202340521 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 157033543 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 115331786 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 28409670 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 8029960 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1983994 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 46904425 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 5349 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 467 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 4530466 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 456 # count of temporary serializing insts renamed +system.cpu.timesIdled 2422 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- |