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| author | Korey Sewell <ksewell@umich.edu> | 2011-02-12 10:14:52 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-02-12 10:14:52 -0500 |
| commit | 2971b8401a4a76a774962900d9aed6e9eb4b2950 (patch) | |
| tree | 7d340ad8093c6dc68395cf209baa0785348137e5 /tests/long | |
| parent | 470aa289da4ca2d6564db76b30355a527c65347d (diff) | |
| download | gem5-2971b8401a4a76a774962900d9aed6e9eb4b2950.tar.xz | |
inorder:regress: host-inst-rate improved ~58%
there are still only a few inorder benchmark but for the lengthier benchmarks (twolf and vortext)
the latest changes to how instruction scheduling (how instructions figure out what they want to
do on each pipeline stage in the inorder model) were able to improve performance by a nice
amount... The latest results for the inorder model process about 100k insts/second
(note: 58% is over the last time run on 64-bit pool machines at UM)
Diffstat (limited to 'tests/long')
| -rw-r--r-- | tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt | 8 | ||||
| -rw-r--r-- | tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index d26ecb349..5d00e7290 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 27953 # Simulator instruction rate (inst/s) -host_mem_usage 1692040 # Number of bytes of host memory used -host_seconds 3160.33 # Real time elapsed on the host -host_tick_rate 13823537 # Simulator tick rate (ticks/s) +host_inst_rate 106274 # Simulator instruction rate (inst/s) +host_mem_usage 1642336 # Number of bytes of host memory used +host_seconds 831.26 # Real time elapsed on the host +host_tick_rate 52555245 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340674 # Number of instructions simulated sim_seconds 0.043687 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index bb16b8b96..e197ea18e 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 25888 # Simulator instruction rate (inst/s) -host_mem_usage 1480704 # Number of bytes of host memory used -host_seconds 3550.03 # Real time elapsed on the host -host_tick_rate 11417230 # Simulator tick rate (ticks/s) +host_inst_rate 105929 # Simulator instruction rate (inst/s) +host_mem_usage 1434716 # Number of bytes of host memory used +host_seconds 867.59 # Real time elapsed on the host +host_tick_rate 46717114 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903057 # Number of instructions simulated sim_seconds 0.040531 # Number of seconds simulated |