diff options
| author | Steve Reinhardt <stever@gmail.com> | 2008-02-16 14:58:37 -0500 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2008-02-16 14:58:37 -0500 |
| commit | 3204f968091d32846a59c0666157c6c8946842d1 (patch) | |
| tree | 497c84fa2634b7bcd6c0a5ab03e6d602c264fd07 /tests/long | |
| parent | 4597a71cef808969c442fca73ae662efe75550d7 (diff) | |
| download | gem5-3204f968091d32846a59c0666157c6c8946842d1.tar.xz | |
Update stats for new writeback behavior.
--HG--
extra : convert_revision : 3e932b5773f5fb9a119822d5bf497f61e9409c14
Diffstat (limited to 'tests/long')
38 files changed, 2228 insertions, 2264 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt index 556d1aafa..0aa6cb0e2 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 65678614 # Number of BTB hits -global.BPredUnit.BTBLookups 73159194 # Number of BTB lookups -global.BPredUnit.RASInCorrect 166 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 4207497 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 70088421 # Number of conditional branches predicted -global.BPredUnit.lookups 76016982 # Number of BP lookups -global.BPredUnit.usedRAS 1692931 # Number of times the RAS was used to get a target. -host_inst_rate 138315 # Simulator instruction rate (inst/s) -host_mem_usage 152792 # Number of bytes of host memory used -host_seconds 4088.86 # Real time elapsed on the host -host_tick_rate 39750263 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 16723579 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 11643802 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 126745064 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 43041730 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 65654561 # Number of BTB hits +global.BPredUnit.BTBLookups 73151995 # Number of BTB lookups +global.BPredUnit.RASInCorrect 169 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 4205600 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 70082652 # Number of conditional branches predicted +global.BPredUnit.lookups 76008681 # Number of BP lookups +global.BPredUnit.usedRAS 1691598 # Number of times the RAS was used to get a target. +host_inst_rate 128115 # Simulator instruction rate (inst/s) +host_mem_usage 179076 # Number of bytes of host memory used +host_seconds 4414.41 # Real time elapsed on the host +host_tick_rate 36753376 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 16547976 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 11089768 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 126749521 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 43031323 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated -sim_seconds 0.162533 # Number of seconds simulated -sim_ticks 162533215000 # Number of ticks simulated +sim_seconds 0.162244 # Number of seconds simulated +sim_ticks 162244431000 # Number of ticks simulated system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 20239745 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 20224381 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 315318492 +system.cpu.commit.COM:committed_per_cycle.samples 314748435 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 101802812 3228.57% - 1 100686151 3193.16% - 2 36607100 1160.96% - 3 9845619 312.24% - 4 9755343 309.38% - 5 22233236 705.10% - 6 12725159 403.57% - 7 1423327 45.14% - 8 20239745 641.88% + 0 101194182 3215.08% + 1 100733142 3200.43% + 2 36585553 1162.37% + 3 9846995 312.85% + 4 9788938 311.01% + 5 22215967 705.83% + 6 12733844 404.57% + 7 1425433 45.29% + 8 20224381 642.56% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 115049510 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 154862033 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4206873 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 4204974 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 60366337 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 60291190 # The number of squashed insts skipped by commit system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.574777 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.574777 # CPI: Total CPI of All Threads +system.cpu.cpi 0.573756 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.573756 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 111194956 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 32075.834031 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5025.008210 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 110978747 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 6935084000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.001944 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 216209 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 901399 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1086452000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001944 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 216209 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 37821036 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 31686.400975 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5378.935827 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 37483793 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10686016924 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.008917 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 337243 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1630285 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1814008455 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.008917 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 337243 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_accesses 111502528 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 18844.916681 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2949.400439 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 111286370 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4073479500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.001939 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 216158 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 638347 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 637536500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001939 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 216158 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 37793986 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 31985.983848 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5397.978661 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 37456762 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 10786441417 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.008923 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 337224 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1657335 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1820327956 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.008923 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 337224 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs 500 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 1750 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 314.127662 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 314.756278 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 4 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 7000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 149015992 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 31838.535092 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5240.672100 # average overall mshr miss latency -system.cpu.dcache.demand_hits 148462540 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 17621100924 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.003714 # miss rate for demand accesses -system.cpu.dcache.demand_misses 553452 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2531684 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 2900460455 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003714 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 553452 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 149296514 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 26852.917003 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4441.533075 # average overall mshr miss latency +system.cpu.dcache.demand_hits 148743132 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 14859920917 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.003707 # miss rate for demand accesses +system.cpu.dcache.demand_misses 553382 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2295682 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 2457864456 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003707 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 553382 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 149015992 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 31838.535092 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5240.672100 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 149296514 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 26852.917003 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4441.533075 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 148462540 # number of overall hits -system.cpu.dcache.overall_miss_latency 17621100924 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.003714 # miss rate for overall accesses -system.cpu.dcache.overall_misses 553452 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2531684 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 2900460455 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003714 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 553452 # number of overall MSHR misses +system.cpu.dcache.overall_hits 148743132 # number of overall hits +system.cpu.dcache.overall_miss_latency 14859920917 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.003707 # miss rate for overall accesses +system.cpu.dcache.overall_misses 553382 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2295682 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 2457864456 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003707 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 553382 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -120,102 +120,102 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 468779 # number of replacements -system.cpu.dcache.sampled_refs 472875 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 468726 # number of replacements +system.cpu.dcache.sampled_refs 472822 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.311897 # Cycle average of tags in use -system.cpu.dcache.total_refs 148543118 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 41066000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 334108 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 42961752 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 653 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4159719 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 688664661 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 143214202 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 123678077 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 9747660 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 1998 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 5464462 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 162980626 # DTB accesses +system.cpu.dcache.tagsinuse 4095.314104 # Cycle average of tags in use +system.cpu.dcache.total_refs 148823693 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 40784000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 334059 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 42566270 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 654 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 4158683 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 688606993 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 143063088 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 123633498 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 9740149 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 1993 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 5485580 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 162949466 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 162934426 # DTB hits -system.cpu.dtb.misses 46200 # DTB misses -system.cpu.dtb.read_accesses 122208799 # DTB read accesses +system.cpu.dtb.hits 162906256 # DTB hits +system.cpu.dtb.misses 43210 # DTB misses +system.cpu.dtb.read_accesses 122197654 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 122187421 # DTB read hits -system.cpu.dtb.read_misses 21378 # DTB read misses -system.cpu.dtb.write_accesses 40771827 # DTB write accesses +system.cpu.dtb.read_hits 122179184 # DTB read hits +system.cpu.dtb.read_misses 18470 # DTB read misses +system.cpu.dtb.write_accesses 40751812 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 40747005 # DTB write hits -system.cpu.dtb.write_misses 24822 # DTB write misses -system.cpu.fetch.Branches 76016982 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 65923476 # Number of cache lines fetched -system.cpu.fetch.Cycles 196873041 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1349337 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 697858040 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 4233176 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.233851 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 65923476 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 67371545 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.146817 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 40727072 # DTB write hits +system.cpu.dtb.write_misses 24740 # DTB write misses +system.cpu.fetch.Branches 76008681 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 65896748 # Number of cache lines fetched +system.cpu.fetch.Cycles 196824794 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1364007 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 697754611 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 4231353 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.234241 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 65896748 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 67346159 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.150319 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 325066153 +system.cpu.fetch.rateDist.samples 324488585 system.cpu.fetch.rateDist.min_value 0 - 0 194116627 5971.60% - 1 10367231 318.93% - 2 15852568 487.67% - 3 14603242 449.24% - 4 12321166 379.04% - 5 14797813 455.22% - 6 6009182 184.86% - 7 3339466 102.73% - 8 53658858 1650.71% + 0 193560578 5965.10% + 1 10362197 319.34% + 2 15850739 488.48% + 3 14596639 449.84% + 4 12316094 379.55% + 5 14809266 456.39% + 6 6007554 185.14% + 7 3339155 102.91% + 8 53646363 1653.26% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 65923389 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 7895 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5473.888889 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 65922489 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 7105500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 65896658 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 7912.777778 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 5485 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 65895758 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 7121500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 900 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 87 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 4926500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits 90 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 4936500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 900 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 73247.210000 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 73217.508889 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 65923389 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 7895 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5473.888889 # average overall mshr miss latency -system.cpu.icache.demand_hits 65922489 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 7105500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 65896658 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 7912.777778 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 5485 # average overall mshr miss latency +system.cpu.icache.demand_hits 65895758 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 7121500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000014 # miss rate for demand accesses system.cpu.icache.demand_misses 900 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 87 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 4926500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_hits 90 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 4936500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 900 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 65923389 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 7895 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5473.888889 # average overall mshr miss latency +system.cpu.icache.overall_accesses 65896658 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 7912.777778 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 5485 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 65922489 # number of overall hits -system.cpu.icache.overall_miss_latency 7105500 # number of overall miss cycles +system.cpu.icache.overall_hits 65895758 # number of overall hits +system.cpu.icache.overall_miss_latency 7121500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000014 # miss rate for overall accesses system.cpu.icache.overall_misses 900 # number of overall misses -system.cpu.icache.overall_mshr_hits 87 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 4926500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_hits 90 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 4936500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 900 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -229,63 +229,63 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 32 # number of replacements +system.cpu.icache.replacements 33 # number of replacements system.cpu.icache.sampled_refs 900 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 770.534648 # Cycle average of tags in use -system.cpu.icache.total_refs 65922489 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 768.164023 # Cycle average of tags in use +system.cpu.icache.total_refs 65895758 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 278 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 67319887 # Number of branches executed -system.cpu.iew.EXEC:nop 42990354 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.842336 # Inst execution rate -system.cpu.iew.EXEC:refs 163919489 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 41167987 # Number of stores executed +system.cpu.iew.EXEC:branches 67308634 # Number of branches executed +system.cpu.iew.EXEC:nop 42970883 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.845233 # Inst execution rate +system.cpu.iew.EXEC:refs 163887352 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 41147603 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 490978856 # num instructions consuming a value -system.cpu.iew.WB:count 595734223 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.805928 # average fanout of values written-back +system.cpu.iew.WB:consumers 489989790 # num instructions consuming a value +system.cpu.iew.WB:count 595601295 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.806975 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 395693750 # num instructions producing a value -system.cpu.iew.WB:rate 1.832654 # insts written-back per cycle -system.cpu.iew.WB:sent 596899727 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4672210 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 212004 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 126745064 # Number of dispatched load instructions +system.cpu.iew.WB:producers 395409527 # num instructions producing a value +system.cpu.iew.WB:rate 1.835506 # insts written-back per cycle +system.cpu.iew.WB:sent 596765761 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4670315 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 16012 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 126749521 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3267944 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 43041730 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 662372892 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 122751502 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6416138 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 598881635 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 1312 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 3266921 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 43031323 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 662307026 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 122739749 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6453693 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 598757600 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 772 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 9747660 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 36859 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 9740149 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 3730 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 103 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 10085137 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 15442 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 110 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 10032402 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 14046 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 28688 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5905 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 11695554 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 3229207 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 28688 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 540377 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 4131833 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.739806 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.739806 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 605297773 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 28615 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 5883 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 11700011 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 3218800 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 28615 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 540218 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 4130097 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.742902 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.742902 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 605211293 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 438526975 72.45% # Type of FU issued - IntMult 6523 0.00% # Type of FU issued + IntAlu 438467789 72.45% # Type of FU issued + IntMult 6519 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 29 0.00% # Type of FU issued FloatCmp 5 0.00% # Type of FU issued @@ -293,17 +293,17 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 4 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 124782414 20.62% # Type of FU issued - MemWrite 41981818 6.94% # Type of FU issued + MemRead 124761442 20.61% # Type of FU issued + MemWrite 41975500 6.94% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 6685852 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011046 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 6453084 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.010663 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 5359505 80.16% # attempts to use FU when none available - IntMult 67 0.00% # attempts to use FU when none available + IntAlu 5357187 83.02% # attempts to use FU when none available + IntMult 62 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available @@ -311,105 +311,102 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 838830 12.55% # attempts to use FU when none available - MemWrite 487450 7.29% # attempts to use FU when none available + MemRead 719041 11.14% # attempts to use FU when none available + MemWrite 376794 5.84% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 325066153 +system.cpu.iq.ISSUE:issued_per_cycle.samples 324488585 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 85827750 2640.32% - 1 67513195 2076.91% - 2 80091695 2463.86% - 3 31532922 970.05% - 4 32017064 984.94% - 5 15691258 482.71% - 6 10782100 331.69% - 7 1096076 33.72% - 8 514093 15.82% + 0 85242339 2626.97% + 1 67499921 2080.19% + 2 79976954 2464.71% + 3 31584556 973.36% + 4 32202311 992.40% + 5 15755227 485.54% + 6 10683294 329.23% + 7 1033211 31.84% + 8 510772 15.74% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.862074 # Inst issue rate -system.cpu.iq.iqInstsAdded 619382516 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 605297773 # Number of instructions issued +system.cpu.iq.ISSUE:rate 1.865122 # Inst issue rate +system.cpu.iq.iqInstsAdded 619336121 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 605211293 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 52509276 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 11692 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 52474081 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 8223 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 28325149 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 65923515 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 28423624 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 65896787 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 65923476 # ITB hits +system.cpu.itb.hits 65896748 # ITB hits system.cpu.itb.misses 39 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 256666 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 4174.356946 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2174.356946 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1071415500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 256664 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 4133.853988 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2133.853988 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 1061011500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 256666 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 558083500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 256664 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 547683500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 256666 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 217109 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4357.887472 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2357.887472 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 30915 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 811412500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.857606 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 186194 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 439024500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.857606 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 186194 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 80608 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 4188.213329 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2188.213329 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 337603500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 256664 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 217058 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4373.107225 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2373.107225 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 181264 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 156531000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.164905 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 35794 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 84943000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.164905 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 35794 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 80561 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 4159.357505 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2159.630590 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 335082000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 80608 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 176387500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 80561 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 173982000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 80608 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 334108 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 334108 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 334108 # number of Writeback MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 80561 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 334059 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 334059 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.193877 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.721530 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 473775 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4251.519668 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2251.519668 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 30915 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1882828000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.934748 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 442860 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 473722 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4163.136245 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2163.136245 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 181264 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1217542500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.617362 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 292458 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 997108000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.934748 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 442860 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 632626500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.617362 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 292458 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 473775 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4251.519668 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2251.519668 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 473722 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4163.136245 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2163.136245 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 30915 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1882828000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.934748 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 442860 # number of overall misses +system.cpu.l2cache.overall_hits 181264 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1217542500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.617362 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 292458 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 997108000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.934748 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 442860 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 632626500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.617362 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 292458 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -421,31 +418,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 14216 # number of replacements -system.cpu.l2cache.sampled_refs 15711 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 85254 # number of replacements +system.cpu.l2cache.sampled_refs 100887 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8150.478384 # Cycle average of tags in use -system.cpu.l2cache.total_refs 65890 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16349.255755 # Cycle average of tags in use +system.cpu.l2cache.total_refs 375454 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 325066431 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 11040761 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 63238 # number of writebacks +system.cpu.numCycles 324488863 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 10819068 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 31586128 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 150557906 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 290343 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 895274322 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 679363736 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 518608699 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 116562402 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 9747660 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 37157110 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 54753810 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 314 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IQFullEvents 31586159 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 150406554 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 152123 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 894972185 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 679108412 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 518438219 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 116538783 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 9740149 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 36983719 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 54583330 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 312 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 72001236 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 71524705 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 25 # count of temporary serializing insts renamed -system.cpu.timesIdled 103 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 101 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 21fbe2323..b25116443 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -169,6 +169,7 @@ euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt index 9e54c6441..1a22ca151 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,21 +1,21 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1400395 # Simulator instruction rate (inst/s) -host_mem_usage 199872 # Number of bytes of host memory used -host_seconds 429.78 # Real time elapsed on the host -host_tick_rate 1787654853 # Simulator tick rate (ticks/s) +host_inst_rate 991240 # Simulator instruction rate (inst/s) +host_mem_usage 177788 # Number of bytes of host memory used +host_seconds 607.18 # Real time elapsed on the host +host_tick_rate 1262504824 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated -sim_seconds 0.768293 # Number of seconds simulated -sim_ticks 768292872000 # Number of ticks simulated +sim_seconds 0.766562 # Number of seconds simulated +sim_ticks 766562460000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 23626.361612 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21626.361612 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 15027.272004 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13027.272004 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4754380000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 3023968000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 4351916000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2621504000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 24478.573840 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22478.573840 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 21214.403072 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19214.403072 # average overall mshr miss latency system.cpu.dcache.demand_hits 153435240 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 12976655000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 11246243000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.003443 # miss rate for demand accesses system.cpu.dcache.demand_misses 530123 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 11916409000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10185997000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.003443 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 530123 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 24478.573840 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22478.573840 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 21214.403072 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 19214.403072 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 153435240 # number of overall hits -system.cpu.dcache.overall_miss_latency 12976655000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 11246243000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.003443 # miss rate for overall accesses system.cpu.dcache.overall_misses 530123 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 11916409000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10185997000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.003443 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 530123 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,9 +76,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.968001 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.968634 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 343385000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 342269000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 325723 # number of writebacks system.cpu.dtb.accesses 153970296 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 673.685273 # Cycle average of tags in use +system.cpu.icache.tagsinuse 673.730766 # Cycle average of tags in use system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -171,30 +171,27 @@ system.cpu.l2cache.ReadExReq_mshr_misses 254163 # nu system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 23035 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 3937824000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.885981 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 178992 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1968912000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.885981 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 178992 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_hits 167236 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 765402000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.172210 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 34791 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 382701000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.172210 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 34791 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 74728 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 21998.527995 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1644016000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 1643906000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 74728 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 822008000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 74728 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 325723 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 325723 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_hits 325723 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.500034 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.519863 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -203,14 +200,14 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 23035 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9529410000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.949506 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 433155 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 167236 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 6356988000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.633407 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 288954 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4764705000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.949506 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 433155 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 3178494000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.633407 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 288954 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate @@ -218,14 +215,14 @@ system.cpu.l2cache.overall_accesses 456190 # nu system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 23035 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9529410000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.949506 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 433155 # number of overall misses +system.cpu.l2cache.overall_hits 167236 # number of overall hits +system.cpu.l2cache.overall_miss_latency 6356988000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.633407 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 288954 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4764705000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.949506 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 433155 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 3178494000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.633407 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 288954 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -237,15 +234,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 13394 # number of replacements -system.cpu.l2cache.sampled_refs 14881 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 84513 # number of replacements +system.cpu.l2cache.sampled_refs 100134 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8423.428104 # Cycle average of tags in use -system.cpu.l2cache.total_refs 52084 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16358.690190 # Cycle average of tags in use +system.cpu.l2cache.total_refs 352458 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.writebacks 63194 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1536585744 # number of cpu cycles simulated +system.cpu.numCycles 1533124920 # number of cpu cycles simulated system.cpu.num_insts 601856964 # Number of instructions executed system.cpu.num_refs 154866966 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr index f33d007a7..5992f7131 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr @@ -1,2 +1,3 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt index d1cd0392d..3e584c89f 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 183466846 # Number of BTB hits -global.BPredUnit.BTBLookups 207793260 # Number of BTB lookups +global.BPredUnit.BTBHits 185907621 # Number of BTB hits +global.BPredUnit.BTBLookups 211172077 # Number of BTB lookups global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 83278105 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 256324661 # Number of conditional branches predicted -global.BPredUnit.lookups 256324661 # Number of BP lookups +global.BPredUnit.condIncorrect 84388329 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 259737867 # Number of conditional branches predicted +global.BPredUnit.lookups 259737867 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 134979 # Simulator instruction rate (inst/s) -host_mem_usage 184868 # Number of bytes of host memory used -host_seconds 10413.54 # Real time elapsed on the host -host_tick_rate 105577175 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 466269652 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 147193104 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 745571091 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 302033091 # Number of stores inserted to the mem dependence unit. +host_inst_rate 60132 # Simulator instruction rate (inst/s) +host_mem_usage 181784 # Number of bytes of host memory used +host_seconds 23375.38 # Real time elapsed on the host +host_tick_rate 47481565 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 469164607 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 147914514 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 750060478 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 305538857 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1405610551 # Number of instructions simulated -sim_seconds 1.099432 # Number of seconds simulated -sim_ticks 1099431876500 # Number of ticks simulated +sim_seconds 1.109900 # Number of seconds simulated +sim_ticks 1109899556500 # Number of ticks simulated system.cpu.commit.COM:branches 86246390 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 8078603 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 8131436 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 1959484906 +system.cpu.commit.COM:committed_per_cycle.samples 1976139127 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 1081809823 5520.89% - 1 578489124 2952.25% - 2 119799391 611.38% - 3 120342305 614.15% - 4 28015342 142.97% - 5 8264992 42.18% - 6 10398281 53.07% - 7 4287045 21.88% - 8 8078603 41.23% + 0 1095749998 5544.90% + 1 581465878 2942.43% + 2 120709498 610.84% + 3 119935544 606.92% + 4 28050272 141.94% + 5 7339488 37.14% + 6 10411639 52.69% + 7 4345374 21.99% + 8 8131436 41.15% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,80 +43,80 @@ system.cpu.commit.COM:loads 402516087 # Nu system.cpu.commit.COM:membars 51356 # Number of memory barriers committed system.cpu.commit.COM:refs 569373869 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 83278105 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 84388329 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1489528974 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 2243501 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1400697440 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1415029138 # The number of squashed insts skipped by commit system.cpu.committedInsts 1405610551 # Number of Instructions Simulated system.cpu.committedInsts_total 1405610551 # Number of Instructions Simulated -system.cpu.cpi 1.564348 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.564348 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 419995861 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 23168.139352 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4590.459997 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 419768838 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5259700500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000541 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 227023 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 708214 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1042140000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000541 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 227023 # number of ReadReq MSHR misses +system.cpu.cpi 1.579242 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.579242 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 423053343 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 15772.083502 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2729.132935 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 422816175 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3740633500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000561 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 237168 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 599122 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 647263000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000561 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 237168 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 7075 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 5075 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 7087.500000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 5087.500000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 283000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 283500 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 203000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 203500 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 165070864 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 45748.072998 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5912.450070 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 164728882 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 15645017500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.002072 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 341982 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1785592 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2021951500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.002072 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 341982 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_accesses 165053818 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 45542.600793 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5916.879810 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 164707416 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 15776048000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.002099 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 346402 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1802638 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2049619000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.002099 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 346402 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1170.889248 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1146.620565 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 585066725 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 36739.076107 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5384.999253 # average overall mshr miss latency -system.cpu.dcache.demand_hits 584497720 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 20904718000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000973 # miss rate for demand accesses -system.cpu.dcache.demand_misses 569005 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2493806 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3064091500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000973 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 569005 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 588107161 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 33443.599740 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4621.351337 # average overall mshr miss latency +system.cpu.dcache.demand_hits 587523591 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 19516681500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000992 # miss rate for demand accesses +system.cpu.dcache.demand_misses 583570 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2401760 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 2696882000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000992 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 583570 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 585066725 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 36739.076107 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5384.999253 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 588107161 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 33443.599740 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4621.351337 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 584497720 # number of overall hits -system.cpu.dcache.overall_miss_latency 20904718000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000973 # miss rate for overall accesses -system.cpu.dcache.overall_misses 569005 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2493806 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3064091500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000973 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 569005 # number of overall MSHR misses +system.cpu.dcache.overall_hits 587523591 # number of overall hits +system.cpu.dcache.overall_miss_latency 19516681500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000992 # miss rate for overall accesses +system.cpu.dcache.overall_misses 583570 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2401760 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 2696882000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000992 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 583570 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -128,89 +128,89 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 495156 # number of replacements -system.cpu.dcache.sampled_refs 499252 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 508363 # number of replacements +system.cpu.dcache.sampled_refs 512459 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.762604 # Cycle average of tags in use -system.cpu.dcache.total_refs 584568799 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 80527000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 338816 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 411395405 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 3450318732 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 760917725 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 784307506 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 239378692 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 2864270 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 256324661 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 354575767 # Number of cache lines fetched -system.cpu.fetch.Cycles 1200225955 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 10817828 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 3736159022 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 88285851 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.116571 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 354575767 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 183466846 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.699132 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4095.764839 # Cycle average of tags in use +system.cpu.dcache.total_refs 587596028 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 80528000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 343236 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 411423589 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 3483733335 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 768911971 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 792962132 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 243659831 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 2841435 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 259737867 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 358807696 # Number of cache lines fetched +system.cpu.fetch.Cycles 1213889868 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 12053122 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 3775936768 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 90315783 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.117010 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 358807696 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 185907621 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.701026 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 2198863598 +system.cpu.fetch.rateDist.samples 2219798958 system.cpu.fetch.rateDist.min_value 0 - 0 1353213454 6154.15% - 1 256648572 1167.19% - 2 82308171 374.32% - 3 38352394 174.42% - 4 84338167 383.55% - 5 41018803 186.55% - 6 32950598 149.85% - 7 20580857 93.60% - 8 289452582 1316.37% + 0 1364716830 6147.93% + 1 258967518 1166.63% + 2 83143428 374.55% + 3 38353275 172.78% + 4 87812104 395.59% + 5 41187584 185.55% + 6 32935987 148.37% + 7 20637545 92.97% + 8 292044687 1315.64% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 354575701 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 7464.153732 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5301.182557 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 354574348 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 10099000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 358807628 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 7480.059084 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 5308.714919 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 358806274 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 10128000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1353 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 66 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 7172500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 1354 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 68 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 7188000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1353 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 1354 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 262065.297857 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 264997.248154 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 354575701 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 7464.153732 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5301.182557 # average overall mshr miss latency -system.cpu.icache.demand_hits 354574348 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 10099000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 358807628 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 7480.059084 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 5308.714919 # average overall mshr miss latency +system.cpu.icache.demand_hits 358806274 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 10128000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_misses 1353 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 66 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 7172500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 1354 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 68 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 7188000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1353 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 1354 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 354575701 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 7464.153732 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5301.182557 # average overall mshr miss latency +system.cpu.icache.overall_accesses 358807628 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 7480.059084 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 5308.714919 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 354574348 # number of overall hits -system.cpu.icache.overall_miss_latency 10099000 # number of overall miss cycles +system.cpu.icache.overall_hits 358806274 # number of overall hits +system.cpu.icache.overall_miss_latency 10128000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_misses 1353 # number of overall misses -system.cpu.icache.overall_mshr_hits 66 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 7172500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 1354 # number of overall misses +system.cpu.icache.overall_mshr_hits 68 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 7188000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1353 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 1354 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -223,182 +223,179 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 206 # number of replacements -system.cpu.icache.sampled_refs 1353 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 1354 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1042.511733 # Cycle average of tags in use -system.cpu.icache.total_refs 354574348 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1043.219654 # Cycle average of tags in use +system.cpu.icache.total_refs 358806274 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 156 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 126703550 # Number of branches executed -system.cpu.iew.EXEC:nop 354855190 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.857840 # Inst execution rate -system.cpu.iew.EXEC:refs 743977888 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 207424101 # Number of stores executed +system.cpu.iew.EXEC:branches 127603528 # Number of branches executed +system.cpu.iew.EXEC:nop 356521630 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.852457 # Inst execution rate +system.cpu.iew.EXEC:refs 746062439 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 207373942 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1489344820 # num instructions consuming a value -system.cpu.iew.WB:count 1853646743 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.962725 # average fanout of values written-back +system.cpu.iew.WB:consumers 1493031889 # num instructions consuming a value +system.cpu.iew.WB:count 1859658958 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.962656 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1433829937 # num instructions producing a value -system.cpu.iew.WB:rate 0.843002 # insts written-back per cycle -system.cpu.iew.WB:sent 1863156113 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 89061580 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 454846 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 745571091 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21380590 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 17115349 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 302033091 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2890291179 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 536553787 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 102628561 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1886272937 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 61790 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1437276141 # num instructions producing a value +system.cpu.iew.WB:rate 0.837760 # insts written-back per cycle +system.cpu.iew.WB:sent 1869182188 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 90142069 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 426198 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 750060478 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21374388 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 17119395 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 305538857 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2904603510 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 538688497 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 102140333 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1892283108 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 19664 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 9769 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 239378692 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 96720 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 4147 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 243659831 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 32077 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 115831794 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 46103 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 115016780 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 46174 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 5246415 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 32 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 343055004 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 135175309 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 5246415 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1515897 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 87545683 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.639244 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.639244 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 1988901498 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 6167113 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 30 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 347544391 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 138681075 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 6167113 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1511945 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 88630124 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.633215 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.633215 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 1994423441 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 1181296004 59.39% # Type of FU issued + IntAlu 1187879871 59.56% # Type of FU issued IntMult 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 3002910 0.15% # Type of FU issued + FloatAdd 2994707 0.15% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 577085119 29.02% # Type of FU issued - MemWrite 227517465 11.44% # Type of FU issued + MemRead 575372220 28.85% # Type of FU issued + MemWrite 228176643 11.44% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 5041207 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.002535 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 4059109 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.002035 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 143450 2.85% # attempts to use FU when none available + IntAlu 143359 3.53% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 241552 4.79% # attempts to use FU when none available + FloatAdd 223654 5.51% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available FloatCvt 0 0.00% # attempts to use FU when none available FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 4269288 84.69% # attempts to use FU when none available - MemWrite 386917 7.68% # attempts to use FU when none available + MemRead 3316143 81.70% # attempts to use FU when none available + MemWrite 375953 9.26% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 2198863598 +system.cpu.iq.ISSUE:issued_per_cycle.samples 2219798958 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 1077268268 4899.20% - 1 589751497 2682.07% - 2 298052129 1355.48% - 3 161348809 733.78% - 4 50984862 231.87% - 5 14316945 65.11% - 6 6653209 30.26% - 7 347143 1.58% - 8 140736 0.64% + 0 1092127511 4919.94% + 1 592160180 2667.63% + 2 301053468 1356.22% + 3 164170369 739.57% + 4 50664484 228.24% + 5 13356785 60.17% + 6 5787626 26.07% + 7 350679 1.58% + 8 127856 0.58% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.904513 # Inst issue rate -system.cpu.iq.iqInstsAdded 2513738089 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1988901498 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21697900 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1088741621 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1800387 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 19454399 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1337770636 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 272229 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 4890.764761 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2890.764761 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1331408000 # number of ReadExReq miss cycles +system.cpu.iq.ISSUE:rate 0.898470 # Inst issue rate +system.cpu.iq.iqInstsAdded 2526420335 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1994423441 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21661545 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 1099219582 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 637228 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 19418044 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1350410508 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 275291 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 4810.268044 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2810.268044 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 1324223500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 272229 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 786950000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 275291 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 773641500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 272229 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 228376 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4206.281488 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2206.281488 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 48944 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 754741500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.785687 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 179432 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 395877500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.785687 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 179432 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 69800 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 4203.058739 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2203.058739 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 293373500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 275291 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 238522 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4132.403832 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2132.403832 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 203557 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 144489500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.146590 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 34965 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 74559500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146590 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 34965 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 71158 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 4269.526968 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2269.653447 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 303811000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 69800 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 153773500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 71158 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 161504000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 69800 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 338816 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 338816 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 338816 # number of Writeback MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 71158 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 343236 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 343236 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.378074 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.069566 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 500605 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4618.839129 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2618.839129 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 48944 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2086149500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.902230 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 451661 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 513813 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4733.874607 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2733.874607 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 203557 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1468713000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.603831 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 310256 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1182827500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.902230 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 451661 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 848201000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.603831 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 310256 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 500605 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4618.839129 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2618.839129 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 513813 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4733.874607 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2733.874607 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 48944 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2086149500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.902230 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 451661 # number of overall misses +system.cpu.l2cache.overall_hits 203557 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1468713000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.603831 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 310256 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1182827500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.902230 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 451661 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 848201000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.603831 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 310256 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -410,31 +407,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 19383 # number of replacements -system.cpu.l2cache.sampled_refs 20779 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 84454 # number of replacements +system.cpu.l2cache.sampled_refs 99919 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8526.680719 # Cycle average of tags in use -system.cpu.l2cache.total_refs 90972 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16408.026694 # Cycle average of tags in use +system.cpu.l2cache.total_refs 406627 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 2198863754 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14237531 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 61955 # number of writebacks +system.cpu.numCycles 2219799114 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14139757 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1244771059 # Number of HB maps that are committed -system.cpu.rename.RENAME:FullRegisterEvents 16 # Number of times there has been no free registers -system.cpu.rename.RENAME:IQFullEvents 47995 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 823614564 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 22929026 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 4933879352 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 3107597262 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2428032497 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 721097012 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 239378692 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 32149684 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1183261438 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 368386115 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 22018362 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 169719231 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21772913 # count of temporary serializing insts renamed +system.cpu.rename.RENAME:FullRegisterEvents 11 # Number of times there has been no free registers +system.cpu.rename.RENAME:IQFullEvents 15246 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 833407854 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 22992244 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 4967044310 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 3128619871 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2442811426 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 727931337 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 243659831 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 32162189 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1198040367 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 368497990 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 22007928 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 169677376 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21764302 # count of temporary serializing insts renamed system.cpu.timesIdled 35 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 19 # Number of system calls diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr index bb7dd4e98..eb1796ead 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7008 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout index debbd670a..eacf59013 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout @@ -36,9 +36,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 28 2007 18:29:37 -M5 started Wed Nov 28 18:29:38 2007 -M5 executing on nacho +M5 compiled Feb 13 2008 00:33:29 +M5 started Wed Feb 13 10:56:54 2008 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1099431876500 because target called exit() +Exiting @ tick 1109899556500 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt index 7a3645f45..1f2416ce1 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,21 +1,21 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2112807 # Simulator instruction rate (inst/s) -host_mem_usage 183960 # Number of bytes of host memory used -host_seconds 704.99 # Real time elapsed on the host -host_tick_rate 2937444703 # Simulator tick rate (ticks/s) +host_inst_rate 679691 # Simulator instruction rate (inst/s) +host_mem_usage 179024 # Number of bytes of host memory used +host_seconds 2191.46 # Real time elapsed on the host +host_tick_rate 944252368 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489514761 # Number of instructions simulated -sim_seconds 2.070879 # Number of seconds simulated -sim_ticks 2070879278000 # Number of ticks simulated +sim_seconds 2.069290 # Number of seconds simulated +sim_ticks 2069290262000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 23237.386607 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21237.386607 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 15023.869951 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13023.869951 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 402318223 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4495621000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 2906593000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 193465 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 4108691000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2519663000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 193465 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 24335.366840 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22335.366840 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 21238.275015 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19238.275015 # average overall mshr miss latency system.cpu.dcache.demand_hits 568845259 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 12485771000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 10896743000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses system.cpu.dcache.demand_misses 513071 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 11459629000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9870601000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 513071 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 24335.366840 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22335.366840 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 21238.275015 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 19238.275015 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 568845259 # number of overall hits -system.cpu.dcache.overall_miss_latency 12485771000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 10896743000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses system.cpu.dcache.overall_misses 513071 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 11459629000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9870601000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 513071 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 449114 # number of replacements system.cpu.dcache.sampled_refs 453210 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.519523 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.519132 # Cycle average of tags in use system.cpu.dcache.total_refs 568906446 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 358652000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 358664000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 316430 # number of writebacks system.cpu.icache.ReadReq_accesses 1489519635 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 24978.142077 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 22978.142077 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 24989.071038 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 22989.071038 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1489518537 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 27426000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 27438000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 25230000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 25242000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1489519635 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 24978.142077 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 22978.142077 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 24989.071038 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 22989.071038 # average overall mshr miss latency system.cpu.icache.demand_hits 1489518537 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 27426000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 27438000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 25230000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 25242000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 1098 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 1489519635 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 24978.142077 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 22978.142077 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 24989.071038 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 22989.071038 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1489518537 # number of overall hits -system.cpu.icache.overall_miss_latency 27426000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 27438000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 1098 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 25230000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 25242000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 1098 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,7 +148,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 115 # number of replacements system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 891.565977 # Cycle average of tags in use +system.cpu.icache.tagsinuse 891.583823 # Cycle average of tags in use system.cpu.icache.total_refs 1489518537 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -165,30 +165,27 @@ system.cpu.l2cache.ReadExReq_mshr_misses 259745 # nu system.cpu.l2cache.ReadReq_accesses 194563 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 28419 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 3655168000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.853934 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 166144 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1827584000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.853934 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 166144 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_hits 160837 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 741972000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.173342 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33726 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 370986000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173342 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33726 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 59901 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 21999.265455 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1317822000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 1317778000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 59901 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 658911000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 59901 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 316430 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 316430 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 316430 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_hits 316430 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.181781 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.429642 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -197,14 +194,14 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 454308 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 28419 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9369558000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.937446 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 425889 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 160837 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 6456362000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.645974 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 293471 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4684779000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.937446 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 425889 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 3228181000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.645974 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 293471 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate @@ -212,14 +209,14 @@ system.cpu.l2cache.overall_accesses 454308 # nu system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 28419 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9369558000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.937446 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 425889 # number of overall misses +system.cpu.l2cache.overall_hits 160837 # number of overall hits +system.cpu.l2cache.overall_miss_latency 6456362000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.645974 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 293471 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4684779000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.937446 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 425889 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 3228181000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.645974 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 293471 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -231,15 +228,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 18200 # number of replacements -system.cpu.l2cache.sampled_refs 19573 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 82889 # number of replacements +system.cpu.l2cache.sampled_refs 98333 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8449.130406 # Cycle average of tags in use -system.cpu.l2cache.total_refs 62277 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16360.484779 # Cycle average of tags in use +system.cpu.l2cache.total_refs 337247 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.writebacks 61877 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4141758556 # number of cpu cycles simulated +system.cpu.numCycles 4138580524 # number of cpu cycles simulated system.cpu.num_insts 1489514761 # Number of instructions executed system.cpu.num_refs 569364430 # Number of memory references system.cpu.workload.PROG:num_syscalls 19 # Number of system calls diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr index f373aba21..eb1796ead 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7009 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout index c636a4a25..2a9392257 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout @@ -36,9 +36,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 28 2007 18:29:37 -M5 started Wed Nov 28 18:29:38 2007 -M5 executing on nacho +M5 compiled Feb 13 2008 00:33:29 +M5 started Wed Feb 13 17:45:44 2008 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2070879278000 because target called exit() +Exiting @ tick 2069290262000 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt index 433654cb0..f11af3267 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,21 +1,21 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2004505 # Simulator instruction rate (inst/s) -host_mem_usage 316136 # Number of bytes of host memory used -host_seconds 121.64 # Real time elapsed on the host -host_tick_rate 2987214089 # Simulator tick rate (ticks/s) +host_inst_rate 588725 # Simulator instruction rate (inst/s) +host_mem_usage 293504 # Number of bytes of host memory used +host_seconds 414.17 # Real time elapsed on the host +host_tick_rate 875417785 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243829010 # Number of instructions simulated -sim_seconds 0.363367 # Number of seconds simulated -sim_ticks 363367019000 # Number of ticks simulated +sim_seconds 0.362567 # Number of seconds simulated +sim_ticks 362567483000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 82219469 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 13898.235302 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11898.235302 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 13002.741800 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11002.741800 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 81326625 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 12408956000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 11609420000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 892844 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 10623268000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 9823732000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 892844 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses) @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 105121305 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 14965.505407 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 12965.505407 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14156.100331 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12156.100331 # average overall mshr miss latency system.cpu.dcache.demand_hits 104133498 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 14783031000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 13983495000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.009397 # miss rate for demand accesses system.cpu.dcache.demand_misses 987807 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 12807417000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 12007881000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.009397 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 987807 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 105121305 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 14965.505407 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 12965.505407 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14156.100331 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12156.100331 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 104133498 # number of overall hits -system.cpu.dcache.overall_miss_latency 14783031000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 13983495000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.009397 # miss rate for overall accesses system.cpu.dcache.overall_misses 987807 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 12807417000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 12007881000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.009397 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 987807 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,9 +86,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 935465 # number of replacements system.cpu.dcache.sampled_refs 939561 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3566.815369 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3565.653949 # Cycle average of tags in use system.cpu.dcache.total_refs 104185630 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 134193669000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 134187537000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 94875 # number of writebacks system.cpu.icache.ReadReq_accesses 244425341 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 24972.696246 # average ReadReq miss latency @@ -148,7 +148,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 25 # number of replacements system.cpu.icache.sampled_refs 879 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 716.847005 # Cycle average of tags in use +system.cpu.icache.tagsinuse 716.707891 # Cycle average of tags in use system.cpu.icache.total_refs 244424462 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -165,13 +165,13 @@ system.cpu.l2cache.ReadExReq_mshr_misses 46717 # nu system.cpu.l2cache.ReadReq_accesses 893723 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 826014 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1489598000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.075761 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 67709 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 744799000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.075761 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 67709 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_hits 892642 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 23782000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.001210 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1081 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 11891000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001210 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1081 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 48254 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency @@ -182,13 +182,10 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency 530794000 system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 48254 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 94875 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 94875 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 94875 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_hits 94875 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 48.787024 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 51.564846 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -197,14 +194,14 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 940440 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 826014 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2517372000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.121673 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 114426 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 892642 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1051556000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.050825 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 47798 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1258686000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.121673 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 114426 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 525778000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.050825 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 47798 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate @@ -212,14 +209,14 @@ system.cpu.l2cache.overall_accesses 940440 # nu system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 826014 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2517372000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.121673 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 114426 # number of overall misses +system.cpu.l2cache.overall_hits 892642 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1051556000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.050825 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 47798 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1258686000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.121673 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 114426 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 525778000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.050825 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 47798 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -231,15 +228,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 829 # number of replacements -system.cpu.l2cache.sampled_refs 11344 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 877 # number of replacements +system.cpu.l2cache.sampled_refs 15560 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8106.277957 # Cycle average of tags in use -system.cpu.l2cache.total_refs 553440 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 8927.933046 # Cycle average of tags in use +system.cpu.l2cache.total_refs 802349 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.writebacks 41 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 726734038 # number of cpu cycles simulated +system.cpu.numCycles 725134966 # number of cpu cycles simulated system.cpu.num_insts 243829010 # Number of instructions executed system.cpu.num_refs 105710359 # Number of memory references system.cpu.workload.PROG:num_syscalls 428 # Number of system calls diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout index 9e3602fb0..1766c5984 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout @@ -21,9 +21,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 28 2007 18:29:37 -M5 started Wed Nov 28 18:29:38 2007 -M5 executing on nacho +M5 compiled Feb 13 2008 00:33:29 +M5 started Wed Feb 13 18:26:14 2008 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 363367019000 because target called exit() +Exiting @ tick 362567483000 because target called exit() diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt index 083930534..2d330cf2a 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,114 +1,114 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 37379171 # Number of BTB hits -global.BPredUnit.BTBLookups 46054369 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1065 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 5708678 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 35676925 # Number of conditional branches predicted -global.BPredUnit.lookups 62521881 # Number of BP lookups -global.BPredUnit.usedRAS 12341843 # Number of times the RAS was used to get a target. -host_inst_rate 102114 # Simulator instruction rate (inst/s) -host_mem_usage 157724 # Number of bytes of host memory used -host_seconds 3678.00 # Real time elapsed on the host -host_tick_rate 36798411 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 72021924 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 51152813 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 125316087 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 92822357 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 36236154 # Number of BTB hits +global.BPredUnit.BTBLookups 45185962 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1073 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 5716683 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 34971489 # Number of conditional branches predicted +global.BPredUnit.lookups 61628084 # Number of BP lookups +global.BPredUnit.usedRAS 12361715 # Number of times the RAS was used to get a target. +host_inst_rate 99282 # Simulator instruction rate (inst/s) +host_mem_usage 157844 # Number of bytes of host memory used +host_seconds 3782.92 # Real time elapsed on the host +host_tick_rate 35167352 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 72386416 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 49504127 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 123653839 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 91343872 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 375574819 # Number of instructions simulated -sim_seconds 0.135344 # Number of seconds simulated -sim_ticks 135344388000 # Number of ticks simulated -system.cpu.commit.COM:branches 44587532 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 13263433 # number cycles where commit BW limit reached +sim_insts 375574833 # Number of instructions simulated +sim_seconds 0.133035 # Number of seconds simulated +sim_ticks 133035205000 # Number of ticks simulated +system.cpu.commit.COM:branches 44587535 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 13438686 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 255158972 +system.cpu.commit.COM:committed_per_cycle.samples 251297305 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 123402584 4836.30% - 1 50437147 1976.70% - 2 19727704 773.15% - 3 19711791 772.53% - 4 11050231 433.07% - 5 9028978 353.86% - 6 5576340 218.54% - 7 2960764 116.04% - 8 13263433 519.81% + 0 121146881 4820.86% + 1 48729398 1939.11% + 2 18716292 744.79% + 3 21031196 836.90% + 4 10746871 427.66% + 5 8854080 352.33% + 6 5795641 230.63% + 7 2838260 112.94% + 8 13438686 534.77% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 398664594 # Number of instructions committed -system.cpu.commit.COM:loads 100651995 # Number of loads committed +system.cpu.commit.COM:count 398664608 # Number of instructions committed +system.cpu.commit.COM:loads 100651996 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 174183397 # Number of memory references committed +system.cpu.commit.COM:refs 174183399 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 5704488 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions +system.cpu.commit.branchMispredicts 5712494 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 398664608 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 96992012 # The number of squashed insts skipped by commit -system.cpu.committedInsts 375574819 # Number of Instructions Simulated -system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated -system.cpu.cpi 0.720732 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.720732 # CPI: Total CPI of All Threads +system.cpu.commit.commitSquashedInsts 90429807 # The number of squashed insts skipped by commit +system.cpu.committedInsts 375574833 # Number of Instructions Simulated +system.cpu.committedInsts_total 375574833 # Number of Instructions Simulated +system.cpu.cpi 0.708435 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.708435 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 95831633 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 11329.441624 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5804.568528 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 95830648 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 11159500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses 94590513 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 11093.306288 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5614.604462 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 94589527 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 10938000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 985 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 501 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 5717500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 986 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 502 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 5536000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 985 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 73513281 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 23616.163142 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6068.580060 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73509971 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 78169500 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_mshr_misses 986 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 73513283 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 23569.486405 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6046.374622 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73509973 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 78015000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 3310 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 7448 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 20087000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_hits 7447 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 20013500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 3310 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40550.943247 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40244.103424 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 169344914 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 20798.370198 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 6008.032596 # average overall mshr miss latency -system.cpu.dcache.demand_hits 169340619 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 89329000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_misses 4295 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 168103796 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 20706.005587 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 5947.276536 # average overall mshr miss latency +system.cpu.dcache.demand_hits 168099500 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 88953000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000026 # miss rate for demand accesses +system.cpu.dcache.demand_misses 4296 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 7949 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 25804500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4295 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 25549500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 4296 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 169344914 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 20798.370198 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 6008.032596 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 168103796 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 20706.005587 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 5947.276536 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 169340619 # number of overall hits -system.cpu.dcache.overall_miss_latency 89329000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_misses 4295 # number of overall misses +system.cpu.dcache.overall_hits 168099500 # number of overall hits +system.cpu.dcache.overall_miss_latency 88953000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000026 # miss rate for overall accesses +system.cpu.dcache.overall_misses 4296 # number of overall misses system.cpu.dcache.overall_mshr_hits 7949 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 25804500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4295 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 25549500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 4296 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -120,104 +120,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 780 # number of replacements -system.cpu.dcache.sampled_refs 4176 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 781 # number of replacements +system.cpu.dcache.sampled_refs 4177 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3296.898282 # Cycle average of tags in use -system.cpu.dcache.total_refs 169340739 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3296.752220 # Cycle average of tags in use +system.cpu.dcache.total_refs 168099620 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 636 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 19548233 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 4322 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 11389388 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 534561309 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 133040681 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 101286271 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 15528683 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 12726 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1283788 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 185382797 # DTB accesses +system.cpu.decode.DECODE:BlockedCycles 18878594 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 4321 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 11282111 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 527703627 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 131753678 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 99378321 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 14771982 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 12721 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1286713 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 182322311 # DTB accesses system.cpu.dtb.acv 11231 # DTB access violations -system.cpu.dtb.hits 185341833 # DTB hits -system.cpu.dtb.misses 40964 # DTB misses -system.cpu.dtb.read_accesses 104727621 # DTB read accesses +system.cpu.dtb.hits 182284581 # DTB hits +system.cpu.dtb.misses 37730 # DTB misses +system.cpu.dtb.read_accesses 103122587 # DTB read accesses system.cpu.dtb.read_acv 11230 # DTB read access violations -system.cpu.dtb.read_hits 104688206 # DTB read hits -system.cpu.dtb.read_misses 39415 # DTB read misses -system.cpu.dtb.write_accesses 80655176 # DTB write accesses +system.cpu.dtb.read_hits 103086401 # DTB read hits +system.cpu.dtb.read_misses 36186 # DTB read misses +system.cpu.dtb.write_accesses 79199724 # DTB write accesses system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_hits 80653627 # DTB write hits -system.cpu.dtb.write_misses 1549 # DTB write misses -system.cpu.fetch.Branches 62521881 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 63961136 # Number of cache lines fetched -system.cpu.fetch.Cycles 169110905 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1508800 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 548208679 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 6045566 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.230973 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 63961136 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 49721014 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.025236 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 79198180 # DTB write hits +system.cpu.dtb.write_misses 1544 # DTB write misses +system.cpu.fetch.Branches 61628084 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 63320961 # Number of cache lines fetched +system.cpu.fetch.Cycles 166618115 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1484455 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 541175943 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 6060115 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.231623 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 63320961 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 48597869 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.033958 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 270687656 +system.cpu.fetch.rateDist.samples 266069288 system.cpu.fetch.rateDist.min_value 0 - 0 165538187 6115.47% - 1 11382617 420.51% - 2 12322114 455.22% - 3 6555852 242.19% - 4 14993338 553.90% - 5 9782168 361.38% - 6 6628609 244.88% - 7 4019736 148.50% - 8 39465035 1457.95% + 0 162772436 6117.67% + 1 10792214 405.62% + 2 11562978 434.59% + 3 6945740 261.05% + 4 14845221 557.95% + 5 9644746 362.49% + 6 6640124 249.56% + 7 3951437 148.51% + 8 38914392 1462.57% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 63960941 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 7182.726807 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4985.135828 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 63957039 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 28027000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000061 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 3902 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 195 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 19452000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3902 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 63320771 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 7179.953858 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4985.644706 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 63316870 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 28009000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000062 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 3901 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 190 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 19449000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000062 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 3901 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 16390.835213 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 16230.933094 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 63960941 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 7182.726807 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4985.135828 # average overall mshr miss latency -system.cpu.icache.demand_hits 63957039 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 28027000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000061 # miss rate for demand accesses -system.cpu.icache.demand_misses 3902 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 195 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 19452000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3902 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 63320771 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 7179.953858 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4985.644706 # average overall mshr miss latency +system.cpu.icache.demand_hits 63316870 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 28009000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000062 # miss rate for demand accesses +system.cpu.icache.demand_misses 3901 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 190 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 19449000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000062 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 3901 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 63960941 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 7182.726807 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4985.135828 # average overall mshr miss latency +system.cpu.icache.overall_accesses 63320771 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 7179.953858 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4985.644706 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 63957039 # number of overall hits -system.cpu.icache.overall_miss_latency 28027000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000061 # miss rate for overall accesses -system.cpu.icache.overall_misses 3902 # number of overall misses -system.cpu.icache.overall_mshr_hits 195 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 19452000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3902 # number of overall MSHR misses +system.cpu.icache.overall_hits 63316870 # number of overall hits +system.cpu.icache.overall_miss_latency 28009000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000062 # miss rate for overall accesses +system.cpu.icache.overall_misses 3901 # number of overall misses +system.cpu.icache.overall_mshr_hits 190 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 19449000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000062 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 3901 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -229,139 +229,139 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 1978 # number of replacements -system.cpu.icache.sampled_refs 3902 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1979 # number of replacements +system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1827.137830 # Cycle average of tags in use -system.cpu.icache.total_refs 63957039 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1826.105929 # Cycle average of tags in use +system.cpu.icache.total_refs 63316870 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1122 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 51166859 # Number of branches executed -system.cpu.iew.EXEC:nop 27206903 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.553018 # Inst execution rate -system.cpu.iew.EXEC:refs 192096320 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 80665864 # Number of stores executed +system.cpu.idleCycles 1124 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 50342697 # Number of branches executed +system.cpu.iew.EXEC:nop 27143660 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.556730 # Inst execution rate +system.cpu.iew.EXEC:refs 189044982 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 79210411 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 289920934 # num instructions consuming a value -system.cpu.iew.WB:count 416705161 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.697472 # average fanout of values written-back +system.cpu.iew.WB:consumers 284353015 # num instructions consuming a value +system.cpu.iew.WB:count 410949767 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.699040 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 202211776 # num instructions producing a value -system.cpu.iew.WB:rate 1.539425 # insts written-back per cycle -system.cpu.iew.WB:sent 417409880 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 6331816 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2208725 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 125316087 # Number of dispatched load instructions +system.cpu.iew.WB:producers 198774253 # num instructions producing a value +system.cpu.iew.WB:rate 1.544515 # insts written-back per cycle +system.cpu.iew.WB:sent 411560855 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 6153520 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2291780 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 123653839 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 6347988 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 92822357 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 495657556 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 111430456 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9555482 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 420384523 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 154148 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 6328938 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 91343872 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 489095367 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 109834571 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9454650 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 414199709 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 219457 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 22202 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 15528683 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 511247 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 24015 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 14771982 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 586141 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 8679637 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 18577 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 8319023 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 12177 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 404895 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 176434 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 24664092 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 19290955 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 404895 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 826576 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 5505240 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.387478 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.387478 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 429940005 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 423678 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 176362 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 23001843 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 17812469 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 423678 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 800835 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 5352685 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.411562 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.411562 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 423654359 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 33581 0.01% # Type of FU issued - IntAlu 166734854 38.78% # Type of FU issued - IntMult 2150402 0.50% # Type of FU issued + IntAlu 164699955 38.88% # Type of FU issued + IntMult 2150553 0.51% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 35165170 8.18% # Type of FU issued - FloatCmp 7853884 1.83% # Type of FU issued - FloatCvt 2943482 0.68% # Type of FU issued - FloatMult 16785484 3.90% # Type of FU issued - FloatDiv 1589029 0.37% # Type of FU issued + FloatAdd 34423933 8.13% # Type of FU issued + FloatCmp 7590989 1.79% # Type of FU issued + FloatCvt 2918170 0.69% # Type of FU issued + FloatMult 16813198 3.97% # Type of FU issued + FloatDiv 1589024 0.38% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 114042343 26.53% # Type of FU issued - MemWrite 82641776 19.22% # Type of FU issued + MemRead 112375969 26.53% # Type of FU issued + MemWrite 81058987 19.13% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 9809447 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.022816 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 9621593 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.022711 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 43912 0.45% # attempts to use FU when none available + IntAlu 40277 0.42% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 84838 0.86% # attempts to use FU when none available - FloatCmp 1645 0.02% # attempts to use FU when none available - FloatCvt 15421 0.16% # attempts to use FU when none available - FloatMult 1864355 19.01% # attempts to use FU when none available - FloatDiv 751232 7.66% # attempts to use FU when none available + FloatAdd 97634 1.01% # attempts to use FU when none available + FloatCmp 3955 0.04% # attempts to use FU when none available + FloatCvt 14420 0.15% # attempts to use FU when none available + FloatMult 1625332 16.89% # attempts to use FU when none available + FloatDiv 750896 7.80% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 5780067 58.92% # attempts to use FU when none available - MemWrite 1267977 12.93% # attempts to use FU when none available + MemRead 5547187 57.65% # attempts to use FU when none available + MemWrite 1541892 16.03% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 270687656 +system.cpu.iq.ISSUE:issued_per_cycle.samples 266069288 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 99778614 3686.12% - 1 58432972 2158.69% - 2 39984102 1477.13% - 3 28980071 1070.61% - 4 24076713 889.46% - 5 11776300 435.05% - 6 4840111 178.81% - 7 2180586 80.56% - 8 638187 23.58% + 0 96503300 3627.00% + 1 57159929 2148.31% + 2 40537288 1523.56% + 3 30901170 1161.40% + 4 22699747 853.15% + 5 10809299 406.26% + 6 4873798 183.18% + 7 2049983 77.05% + 8 534774 20.10% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.588319 # Inst issue rate -system.cpu.iq.iqInstsAdded 468450414 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 429940005 # Number of instructions issued +system.cpu.iq.ISSUE:rate 1.592264 # Inst issue rate +system.cpu.iq.iqInstsAdded 461951468 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 423654359 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 91656765 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1252688 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 85357325 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 903613 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 70486985 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 63961435 # ITB accesses -system.cpu.itb.acv 1 # ITB acv -system.cpu.itb.hits 63961136 # ITB hits -system.cpu.itb.misses 299 # ITB misses +system.cpu.iq.iqSquashedOperandsExamined 69252259 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 63321261 # ITB accesses +system.cpu.itb.acv 2 # ITB acv +system.cpu.itb.hits 63320961 # ITB hits +system.cpu.itb.misses 300 # ITB misses system.cpu.l2cache.ReadExReq_accesses 3195 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 4663.223787 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2663.223787 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 14899000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 4638.497653 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2638.497653 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 14820000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 3195 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 8509000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 8430000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 3195 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 4883 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4347.238406 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2347.238406 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 592 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 18654000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.878763 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4291 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10072000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.878763 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4291 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_avg_miss_latency 4341.521020 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2341.521020 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 649 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 18382000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.867090 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4234 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 9914000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.867090 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 4234 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 121 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 4500 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2500 # average UpgradeReq mshr miss latency @@ -372,44 +372,41 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency 302500 system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 121 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 636 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 636 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 636 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_hits 636 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.137170 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.128626 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 8078 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4482.099920 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2482.099920 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 592 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 33553000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.926715 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7486 # number of demand (read+write) misses +system.cpu.l2cache.demand_avg_miss_latency 4469.242159 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2469.242159 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 649 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 33202000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.919658 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7429 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 18581000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.926715 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7486 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 18344000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.919658 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7429 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 8078 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4482.099920 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2482.099920 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 4469.242159 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2469.242159 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 592 # number of overall hits -system.cpu.l2cache.overall_miss_latency 33553000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.926715 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7486 # number of overall misses +system.cpu.l2cache.overall_hits 649 # number of overall hits +system.cpu.l2cache.overall_miss_latency 33202000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.919658 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7429 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 18581000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.926715 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7486 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 18344000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.919658 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7429 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -421,31 +418,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 6 # number of replacements -system.cpu.l2cache.sampled_refs 4170 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 15 # number of replacements +system.cpu.l2cache.sampled_refs 4688 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3521.000776 # Cycle average of tags in use -system.cpu.l2cache.total_refs 572 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3886.512098 # Cycle average of tags in use +system.cpu.l2cache.total_refs 603 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 270688778 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 9099322 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1995191 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 138097938 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 7233951 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 686963869 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 520820269 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 337090567 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 97114306 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 15528683 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 10493249 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 77558226 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 354158 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 37906 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 22964339 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 253 # count of temporary serializing insts renamed -system.cpu.timesIdled 418 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.numCycles 266070412 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 9037497 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 259532351 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1658142 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 136681474 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 7036650 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 676869332 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 514036809 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 332594976 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 95406326 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 14771982 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 9818184 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 73062625 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 353825 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 37914 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 21299684 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 252 # count of temporary serializing insts renamed +system.cpu.timesIdled 417 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout index 50ed34325..f2cd9657b 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout @@ -1,2 +1,2 @@ Eon, Version 1.1 -OO-style eon Time= 0.133333 +OO-style eon Time= 0.116667 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini index f30cc2238..e96d29170 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -169,6 +169,7 @@ euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt index ebb18ce61..6d3f9def2 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,21 +1,21 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1238026 # Simulator instruction rate (inst/s) -host_mem_usage 207368 # Number of bytes of host memory used -host_seconds 322.02 # Real time elapsed on the host -host_tick_rate 1761163764 # Simulator tick rate (ticks/s) +host_inst_rate 850841 # Simulator instruction rate (inst/s) +host_mem_usage 157124 # Number of bytes of host memory used +host_seconds 468.55 # Real time elapsed on the host +host_tick_rate 1210368735 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664609 # Number of instructions simulated -sim_seconds 0.567124 # Number of seconds simulated -sim_ticks 567124013000 # Number of ticks simulated +sim_seconds 0.567123 # Number of seconds simulated +sim_ticks 567123353000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 24216.842105 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22216.842105 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 23522.105263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21522.105263 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 23006000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 22346000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 21106000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 20446000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses) @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 24825.515947 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22825.515947 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 24670.731707 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 22670.731707 # average overall mshr miss latency system.cpu.dcache.demand_hits 168270956 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 105856000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 105196000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses system.cpu.dcache.demand_misses 4264 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 97328000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 96668000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 4264 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 24825.515947 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22825.515947 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 24670.731707 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 22670.731707 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 168270956 # number of overall hits -system.cpu.dcache.overall_miss_latency 105856000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 105196000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_misses 4264 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 97328000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 96668000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 4264 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3289.453852 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3289.454246 # Cycle average of tags in use system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 625 # number of writebacks @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1769 # number of replacements system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1795.369803 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1795.369921 # Cycle average of tags in use system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -171,13 +171,13 @@ system.cpu.l2cache.ReadExReq_mshr_misses 3202 # nu system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 530 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 90046000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.885356 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4093 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 45023000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.885356 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4093 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_hits 585 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 88836000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.873459 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4038 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 44418000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 112 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency @@ -188,13 +188,10 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1232000 system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 112 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 625 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 625 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.128109 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.120240 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -203,14 +200,14 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 530 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 160490000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.932268 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7295 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 585 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 159280000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.925240 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7240 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 80245000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.932268 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7295 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 79640000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.925240 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7240 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate @@ -218,14 +215,14 @@ system.cpu.l2cache.overall_accesses 7825 # nu system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 530 # number of overall hits -system.cpu.l2cache.overall_miss_latency 160490000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.932268 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7295 # number of overall misses +system.cpu.l2cache.overall_hits 585 # number of overall hits +system.cpu.l2cache.overall_miss_latency 159280000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.925240 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7240 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 80245000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.932268 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7295 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 79640000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.925240 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7240 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -237,15 +234,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 6 # number of replacements -system.cpu.l2cache.sampled_refs 3981 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 15 # number of replacements +system.cpu.l2cache.sampled_refs 4491 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3355.056761 # Cycle average of tags in use -system.cpu.l2cache.total_refs 510 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3714.863490 # Cycle average of tags in use +system.cpu.l2cache.total_refs 540 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1134248026 # number of cpu cycles simulated +system.cpu.numCycles 1134246706 # number of cpu cycles simulated system.cpu.num_insts 398664609 # Number of instructions executed system.cpu.num_refs 174183455 # Number of memory references system.cpu.workload.PROG:num_syscalls 215 # Number of system calls diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr index 4bb0d9bbe..982c0e2fd 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr @@ -1,3 +1,4 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. getting pixel output filename pixels_out.cook diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index 7ccc4388b..155b89d4e 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -169,6 +169,7 @@ euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt index 0c4f37988..b73b39051 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,21 +1,21 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1159414 # Simulator instruction rate (inst/s) -host_mem_usage 206548 # Number of bytes of host memory used -host_seconds 1732.76 # Real time elapsed on the host -host_tick_rate 1597499589 # Simulator tick rate (ticks/s) +host_inst_rate 883544 # Simulator instruction rate (inst/s) +host_mem_usage 162840 # Number of bytes of host memory used +host_seconds 2273.78 # Real time elapsed on the host +host_tick_rate 1217345227 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated -sim_seconds 2.768086 # Number of seconds simulated -sim_ticks 2768085828000 # Number of ticks simulated +sim_seconds 2.767980 # Number of seconds simulated +sim_ticks 2767979952000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 24898.959808 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22898.959808 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 24826.352085 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22826.352085 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 36307464000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 36201588000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 33391080000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 33285204000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 24903.889094 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22903.889094 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 24834.823569 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 22834.823569 # average overall mshr miss latency system.cpu.dcache.demand_hits 720331943 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 38177139000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 38071263000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002124 # miss rate for demand accesses system.cpu.dcache.demand_misses 1532979 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 35111181000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 35005305000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002124 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 1532979 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 24903.889094 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22903.889094 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 24834.823569 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 22834.823569 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 720331943 # number of overall hits -system.cpu.dcache.overall_miss_latency 38177139000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 38071263000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002124 # miss rate for overall accesses system.cpu.dcache.overall_misses 1532979 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 35111181000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 35005305000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002124 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 1532979 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 1526048 # number of replacements system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.361643 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.361619 # Cycle average of tags in use system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 795905000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 74589 # number of writebacks @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 9046 # number of replacements system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1478.559335 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1478.559454 # Cycle average of tags in use system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -171,13 +171,13 @@ system.cpu.l2cache.ReadExReq_mshr_misses 71952 # nu system.cpu.l2cache.ReadReq_accesses 1468788 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 20497 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 31862402000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.986045 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1448291 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15931201000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.986045 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1448291 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_hits 29320 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 31668296000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.980038 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1439468 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 15834148000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980038 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1439468 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 2835 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 21821.516755 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency @@ -188,13 +188,10 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31185000 system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 2835 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 74589 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 74589 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_hits 74589 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.015643 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.023744 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -203,14 +200,14 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 20497 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 33445346000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.986697 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 1520243 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 29320 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 33251240000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.980970 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1511420 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 16722673000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.986697 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 1520243 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 16625620000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.980970 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1511420 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate @@ -218,14 +215,14 @@ system.cpu.l2cache.overall_accesses 1540740 # nu system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 20497 # number of overall hits -system.cpu.l2cache.overall_miss_latency 33445346000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.986697 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 1520243 # number of overall misses +system.cpu.l2cache.overall_hits 29320 # number of overall hits +system.cpu.l2cache.overall_miss_latency 33251240000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.980970 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1511420 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 16722673000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.986697 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 1520243 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 16625620000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.980970 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1511420 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -237,15 +234,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 1412930 # number of replacements -system.cpu.l2cache.sampled_refs 1445479 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 1473608 # number of replacements +system.cpu.l2cache.sampled_refs 1506166 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31165.186472 # Cycle average of tags in use -system.cpu.l2cache.total_refs 22612 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 31924.676313 # Cycle average of tags in use +system.cpu.l2cache.total_refs 35763 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.writebacks 66899 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5536171656 # number of cpu cycles simulated +system.cpu.numCycles 5535959904 # number of cpu cycles simulated system.cpu.num_insts 2008987605 # Number of instructions executed system.cpu.num_refs 722823898 # Number of memory references system.cpu.workload.PROG:num_syscalls 39 # Number of system calls diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr index a6133a5ee..aa60d7c13 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr @@ -1,3 +1,4 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 0, ...) diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt index 74d2aee08..8d53ad02b 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 8036279 # Number of BTB hits -global.BPredUnit.BTBLookups 14260181 # Number of BTB lookups -global.BPredUnit.RASInCorrect 35537 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 456495 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 10555311 # Number of conditional branches predicted -global.BPredUnit.lookups 16250871 # Number of BP lookups -global.BPredUnit.usedRAS 1941181 # Number of times the RAS was used to get a target. -host_inst_rate 115474 # Simulator instruction rate (inst/s) -host_mem_usage 160356 # Number of bytes of host memory used -host_seconds 689.26 # Real time elapsed on the host -host_tick_rate 36122153 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12102830 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 10931763 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 22978723 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 16295551 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 8038204 # Number of BTB hits +global.BPredUnit.BTBLookups 14256935 # Number of BTB lookups +global.BPredUnit.RASInCorrect 35926 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 456185 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 10553314 # Number of conditional branches predicted +global.BPredUnit.lookups 16248074 # Number of BP lookups +global.BPredUnit.usedRAS 1941559 # Number of times the RAS was used to get a target. +host_inst_rate 107979 # Simulator instruction rate (inst/s) +host_mem_usage 171824 # Number of bytes of host memory used +host_seconds 737.10 # Real time elapsed on the host +host_tick_rate 33795098 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12328057 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 11324911 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 22967030 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 16293172 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated -sim_seconds 0.024898 # Number of seconds simulated -sim_ticks 24897604000 # Number of ticks simulated +sim_seconds 0.024910 # Number of seconds simulated +sim_ticks 24910446000 # Number of ticks simulated system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3356243 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 3431451 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 48528188 +system.cpu.commit.COM:committed_per_cycle.samples 48556236 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 19702397 4059.99% - 1 10946158 2255.63% - 2 5036045 1037.76% - 3 3466785 714.39% - 4 2664416 549.05% - 5 1534889 316.29% - 6 1008769 207.87% - 7 812486 167.43% - 8 3356243 691.61% + 0 19632028 4043.15% + 1 11130407 2292.27% + 2 5090838 1048.44% + 3 3451952 710.92% + 4 2493473 513.52% + 5 1522245 313.50% + 6 990886 204.07% + 7 812956 167.43% + 8 3431451 706.70% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 20379399 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 35224018 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 360762 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 360457 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8068812 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8047613 # The number of squashed insts skipped by commit system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.625633 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.625633 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 20378393 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 15241.304772 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4212.764920 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20316865 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 937767000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.003019 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 61528 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 82787 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 259203000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003019 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61528 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 13782122 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 32047.161184 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5374.422625 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 13632306 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4801177500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.010870 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 149816 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 831255 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 805174500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010870 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 149816 # number of WriteReq MSHR misses +system.cpu.cpi 0.625955 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.625955 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 44 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 44 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 20358815 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 14848.430668 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3932.171708 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 20297292 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 913520000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.003022 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 61523 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 82415 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 241919000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 61523 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 13806620 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 30619.646254 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5319.309194 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 13656795 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4587588500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.010852 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 149825 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 806757 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 796965500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.010852 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 149825 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 165.626302 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 165.649492 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 34160515 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27154.518226 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5036.232398 # average overall mshr miss latency -system.cpu.dcache.demand_hits 33949171 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 5738944500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.006187 # miss rate for demand accesses -system.cpu.dcache.demand_misses 211344 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 914042 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1064377500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.006187 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 211344 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 34165435 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 26028.675455 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4915.516116 # average overall mshr miss latency +system.cpu.dcache.demand_hits 33954087 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 5501108500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.006186 # miss rate for demand accesses +system.cpu.dcache.demand_misses 211348 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 889172 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 1038884500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.006186 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 211348 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 34160515 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27154.518226 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5036.232398 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 34165435 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 26028.675455 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4915.516116 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 33949171 # number of overall hits -system.cpu.dcache.overall_miss_latency 5738944500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.006187 # miss rate for overall accesses -system.cpu.dcache.overall_misses 211344 # number of overall misses -system.cpu.dcache.overall_mshr_hits 914042 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1064377500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.006187 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 211344 # number of overall MSHR misses +system.cpu.dcache.overall_hits 33954087 # number of overall hits +system.cpu.dcache.overall_miss_latency 5501108500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.006186 # miss rate for overall accesses +system.cpu.dcache.overall_misses 211348 # number of overall misses +system.cpu.dcache.overall_mshr_hits 889172 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 1038884500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.006186 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 211348 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -120,104 +120,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 200917 # number of replacements -system.cpu.dcache.sampled_refs 205013 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 200918 # number of replacements +system.cpu.dcache.sampled_refs 205014 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4080.927145 # Cycle average of tags in use -system.cpu.dcache.total_refs 33955545 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 120649000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 147757 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 943541 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 96612 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3650840 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 101683737 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 27936407 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 19620838 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1265214 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 284149 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 27403 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 36632249 # DTB accesses -system.cpu.dtb.acv 36 # DTB access violations -system.cpu.dtb.hits 36460811 # DTB hits -system.cpu.dtb.misses 171438 # DTB misses -system.cpu.dtb.read_accesses 21568197 # DTB read accesses -system.cpu.dtb.read_acv 34 # DTB read access violations -system.cpu.dtb.read_hits 21411149 # DTB read hits -system.cpu.dtb.read_misses 157048 # DTB read misses -system.cpu.dtb.write_accesses 15064052 # DTB write accesses +system.cpu.dcache.tagsinuse 4080.935098 # Cycle average of tags in use +system.cpu.dcache.total_refs 33960465 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 120644000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147759 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 965138 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 96643 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3649464 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 101643368 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 27939518 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 19626008 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1262570 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 284543 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 25573 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 36605590 # DTB accesses +system.cpu.dtb.acv 38 # DTB access violations +system.cpu.dtb.hits 36432080 # DTB hits +system.cpu.dtb.misses 173510 # DTB misses +system.cpu.dtb.read_accesses 21546917 # DTB read accesses +system.cpu.dtb.read_acv 36 # DTB read access violations +system.cpu.dtb.read_hits 21390081 # DTB read hits +system.cpu.dtb.read_misses 156836 # DTB read misses +system.cpu.dtb.write_accesses 15058673 # DTB write accesses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_hits 15049662 # DTB write hits -system.cpu.dtb.write_misses 14390 # DTB write misses -system.cpu.fetch.Branches 16250871 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 13378376 # Number of cache lines fetched -system.cpu.fetch.Cycles 33230958 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 152674 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 103283004 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 574326 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.326354 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 13378376 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 9977460 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.074155 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 15041999 # DTB write hits +system.cpu.dtb.write_misses 16674 # DTB write misses +system.cpu.fetch.Branches 16248074 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 13374991 # Number of cache lines fetched +system.cpu.fetch.Cycles 33229665 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 154532 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 103238390 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 573003 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.326130 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 13374991 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 9979763 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.072191 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 49793403 +system.cpu.fetch.rateDist.samples 49818807 system.cpu.fetch.rateDist.min_value 0 - 0 29966239 6018.11% - 1 1875035 376.56% - 2 1535605 308.40% - 3 1804270 362.35% - 4 3961078 795.50% - 5 1877676 377.09% - 6 698372 140.25% - 7 1099999 220.91% - 8 6975129 1400.81% + 0 29989736 6019.76% + 1 1895135 380.41% + 2 1526458 306.40% + 3 1823774 366.08% + 4 3936760 790.22% + 5 1866062 374.57% + 6 698148 140.14% + 7 1109093 222.63% + 8 6973641 1399.80% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 13377544 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4583.036351 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2544.804459 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 13291961 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 392230000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.006398 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 85583 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 832 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 217792000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006398 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 85583 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 13374115 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 4650.026870 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2608.921937 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 13288517 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 398033000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.006400 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 85598 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 876 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 223318500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.006400 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 85598 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 155.310763 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 155.243312 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 13377544 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4583.036351 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2544.804459 # average overall mshr miss latency -system.cpu.icache.demand_hits 13291961 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 392230000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.006398 # miss rate for demand accesses -system.cpu.icache.demand_misses 85583 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 832 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 217792000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.006398 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 85583 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 13374115 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 4650.026870 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2608.921937 # average overall mshr miss latency +system.cpu.icache.demand_hits 13288517 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 398033000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.006400 # miss rate for demand accesses +system.cpu.icache.demand_misses 85598 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 876 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 223318500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.006400 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 85598 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 13377544 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4583.036351 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2544.804459 # average overall mshr miss latency +system.cpu.icache.overall_accesses 13374115 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 4650.026870 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2608.921937 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 13291961 # number of overall hits -system.cpu.icache.overall_miss_latency 392230000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.006398 # miss rate for overall accesses -system.cpu.icache.overall_misses 85583 # number of overall misses -system.cpu.icache.overall_mshr_hits 832 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 217792000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.006398 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 85583 # number of overall MSHR misses +system.cpu.icache.overall_hits 13288517 # number of overall hits +system.cpu.icache.overall_miss_latency 398033000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.006400 # miss rate for overall accesses +system.cpu.icache.overall_misses 85598 # number of overall misses +system.cpu.icache.overall_mshr_hits 876 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 223318500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.006400 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 85598 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -229,80 +229,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 83535 # number of replacements -system.cpu.icache.sampled_refs 85583 # Sample count of references to valid blocks. +system.cpu.icache.replacements 83550 # number of replacements +system.cpu.icache.sampled_refs 85598 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1922.482733 # Cycle average of tags in use -system.cpu.icache.total_refs 13291961 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 21658930000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 1922.621732 # Cycle average of tags in use +system.cpu.icache.total_refs 13288517 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 21667252000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1806 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14744087 # Number of branches executed -system.cpu.iew.EXEC:nop 9381144 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.703621 # Inst execution rate -system.cpu.iew.EXEC:refs 36974156 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15296705 # Number of stores executed +system.cpu.idleCycles 2086 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14743916 # Number of branches executed +system.cpu.iew.EXEC:nop 9378551 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.702006 # Inst execution rate +system.cpu.iew.EXEC:refs 36947583 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15291466 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 42381395 # num instructions consuming a value -system.cpu.iew.WB:count 84348023 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.765304 # average fanout of values written-back +system.cpu.iew.WB:consumers 42399540 # num instructions consuming a value +system.cpu.iew.WB:count 84317145 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.765160 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 32434648 # num instructions producing a value -system.cpu.iew.WB:rate 1.693898 # insts written-back per cycle -system.cpu.iew.WB:sent 84580813 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 401245 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 18721 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 22978723 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 4986 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 359067 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 16295551 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 98839523 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 21677451 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 547314 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 84832143 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 2010 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 32442413 # num instructions producing a value +system.cpu.iew.WB:rate 1.692405 # insts written-back per cycle +system.cpu.iew.WB:sent 84551587 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 401023 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 18086 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 22967030 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 4976 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 358113 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 16293172 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 98809667 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 21656117 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 536500 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 84795443 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 1943 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 182 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1265214 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 2634 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 166 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1262570 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 2513 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 948620 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 989 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 947497 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 960 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 20664 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1306 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2599324 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1450932 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 20664 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 108416 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 292829 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.598382 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.598382 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 85379457 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 18554 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1310 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 2587631 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1448553 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 18554 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 108095 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 292928 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.597558 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.597558 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 85331943 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 47888413 56.09% # Type of FU issued - IntMult 42937 0.05% # Type of FU issued + IntAlu 47873863 56.10% # Type of FU issued + IntMult 42967 0.05% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 121447 0.14% # Type of FU issued + FloatAdd 121266 0.14% # Type of FU issued FloatCmp 86 0.00% # Type of FU issued - FloatCvt 122009 0.14% # Type of FU issued + FloatCvt 121911 0.14% # Type of FU issued FloatMult 50 0.00% # Type of FU issued - FloatDiv 38531 0.05% # Type of FU issued + FloatDiv 38525 0.05% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 21786877 25.52% # Type of FU issued - MemWrite 15379107 18.01% # Type of FU issued + MemRead 21762707 25.50% # Type of FU issued + MemWrite 15370568 18.01% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 969118 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011351 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 973739 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011411 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 94143 9.71% # attempts to use FU when none available + IntAlu 95466 9.80% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -311,105 +311,102 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 449697 46.40% # attempts to use FU when none available - MemWrite 425278 43.88% # attempts to use FU when none available + MemRead 447999 46.01% # attempts to use FU when none available + MemWrite 430274 44.19% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 49793403 +system.cpu.iq.ISSUE:issued_per_cycle.samples 49818807 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 14936070 2999.61% - 1 13322790 2675.61% - 2 8095375 1625.79% - 3 4742465 952.43% - 4 4697667 943.43% - 5 2107602 423.27% - 6 1178715 236.72% - 7 464198 93.22% - 8 248521 49.91% + 0 14814928 2973.76% + 1 13524369 2714.71% + 2 8025078 1610.85% + 3 4803693 964.23% + 4 4680291 939.46% + 5 2123644 426.27% + 6 1156346 232.11% + 7 454785 91.29% + 8 235673 47.31% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.714612 # Inst issue rate -system.cpu.iq.iqInstsAdded 89453393 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 85379457 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 4986 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 9664351 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 49402 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 403 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 6605234 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 13403794 # ITB accesses +system.cpu.iq.ISSUE:rate 1.712774 # Inst issue rate +system.cpu.iq.iqInstsAdded 89426140 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 85331943 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 4976 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 9626821 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 45871 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 393 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 6618385 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 13400594 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 13378376 # ITB hits -system.cpu.itb.misses 25418 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 143485 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 4092.825034 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2092.825034 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 587259000 # number of ReadExReq miss cycles +system.cpu.itb.hits 13374991 # ITB hits +system.cpu.itb.misses 25603 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 143491 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 4105.274895 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2105.274895 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 589070000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 143485 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 300289000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 143491 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 302088000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 143485 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 147111 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4141.158104 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2141.158104 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 98428 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 201604000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.330927 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 48683 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 104238000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.330927 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 48683 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 6350 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 4242.677165 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2244.724409 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 26941000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 143491 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 147121 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4130.611741 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2130.611741 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 102527 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 184200500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.303111 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 44594 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 95012500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.303111 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 44594 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 6346 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 4217.538607 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2242.593760 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 26764500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 6350 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14254000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 6346 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14231500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 6350 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 147757 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 147757 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 147757 # number of Writeback MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 6346 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 147759 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 147759 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.449601 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.676534 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 290596 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4105.069523 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2105.069523 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 98428 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 788863000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.661289 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 192168 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 290612 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4111.282133 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2111.282133 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 102527 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 773270500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.647203 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 188085 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 404527000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.661289 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 192168 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 397100500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.647203 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 188085 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 290596 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4105.069523 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2105.069523 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 290612 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4111.282133 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2111.282133 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 98428 # number of overall hits -system.cpu.l2cache.overall_miss_latency 788863000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.661289 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 192168 # number of overall misses +system.cpu.l2cache.overall_hits 102527 # number of overall hits +system.cpu.l2cache.overall_miss_latency 773270500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.647203 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 188085 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 404527000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.661289 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 192168 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 397100500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.647203 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 188085 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -421,31 +418,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 25961 # number of replacements -system.cpu.l2cache.sampled_refs 41866 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 148798 # number of replacements +system.cpu.l2cache.sampled_refs 174015 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 4585.787881 # Cycle average of tags in use -system.cpu.l2cache.total_refs 102555 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18438.001925 # Cycle average of tags in use +system.cpu.l2cache.total_refs 117727 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 49795209 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 258129 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 120645 # number of writebacks +system.cpu.numCycles 49820893 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 263970 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 32247 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 28248638 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 541903 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 121528434 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 100873332 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 60701342 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 19331218 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1265214 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 614234 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 8154461 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 75970 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 5252 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 1383660 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 5250 # count of temporary serializing insts renamed -system.cpu.timesIdled 679 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 36282 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 28255906 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 551452 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 121470810 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 100830627 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 60670426 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 19329077 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1262570 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 631100 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 8123545 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 76184 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 5248 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 1415098 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 5246 # count of temporary serializing insts renamed +system.cpu.timesIdled 786 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 99534f902..0e853bbc7 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -169,6 +169,7 @@ euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt index c05407db8..5c61eb239 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,21 +1,21 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1210019 # Simulator instruction rate (inst/s) -host_mem_usage 209960 # Number of bytes of host memory used -host_seconds 73.01 # Real time elapsed on the host -host_tick_rate 1768843958 # Simulator tick rate (ticks/s) +host_inst_rate 826490 # Simulator instruction rate (inst/s) +host_mem_usage 170652 # Number of bytes of host memory used +host_seconds 106.89 # Real time elapsed on the host +host_tick_rate 1207717238 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated -sim_seconds 0.129140 # Number of seconds simulated -sim_ticks 129139604000 # Number of ticks simulated +sim_seconds 0.129089 # Number of seconds simulated +sim_ticks 129089084000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 20958.331276 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18958.331276 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 19821.229326 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17821.229326 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1273533000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 1204437000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1152003000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1082907000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 23833.613541 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 21833.613541 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 23505.456929 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 21505.456929 # average overall mshr miss latency system.cpu.dcache.demand_hits 34679457 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 5018358000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 4949262000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses system.cpu.dcache.demand_misses 210558 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4597242000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4528146000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 210558 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 23833.613541 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 21833.613541 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 23505.456929 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 21505.456929 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 34679457 # number of overall hits -system.cpu.dcache.overall_miss_latency 5018358000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 4949262000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses system.cpu.dcache.overall_misses 210558 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4597242000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4528146000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 210558 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,9 +76,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 200247 # number of replacements system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4080.930479 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4080.925680 # Cycle average of tags in use system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 737173000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 736945000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147714 # number of writebacks system.cpu.dtb.accesses 34987415 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations @@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 14613377 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 14131.456382 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12131.456382 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 14374.483228 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12374.483228 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1080152000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 1098728000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 927280000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 945856000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 14131.456382 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12131.456382 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 14374.483228 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12374.483228 # average overall mshr miss latency system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1080152000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 1098728000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 927280000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 945856000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 14131.456382 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12131.456382 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 14374.483228 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12374.483228 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 88361638 # number of overall hits -system.cpu.icache.overall_miss_latency 1080152000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 1098728000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses system.cpu.icache.overall_misses 76436 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 927280000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 945856000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 74391 # number of replacements system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1876.941758 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1876.966161 # Cycle average of tags in use system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -171,30 +171,27 @@ system.cpu.l2cache.ReadExReq_mshr_misses 143578 # nu system.cpu.l2cache.ReadReq_accesses 137201 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 89695 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1045132000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.346251 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 47506 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 522566000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.346251 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 47506 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_hits 93905 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 952512000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.315566 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 43296 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 476256000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315566 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 43296 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 21989.380531 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 21869.026549 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 136664000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 135916000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 68365000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 147714 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 147714 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.294067 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.630834 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -203,14 +200,14 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 89695 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 4203848000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.680549 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 191084 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 93905 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 4111228000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.665555 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 186874 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2101924000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.680549 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 191084 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 2055614000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.665555 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 186874 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate @@ -218,14 +215,14 @@ system.cpu.l2cache.overall_accesses 280779 # nu system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 89695 # number of overall hits -system.cpu.l2cache.overall_miss_latency 4203848000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.680549 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 191084 # number of overall misses +system.cpu.l2cache.overall_hits 93905 # number of overall hits +system.cpu.l2cache.overall_miss_latency 4111228000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.665555 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 186874 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2101924000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.680549 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 191084 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 2055614000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.665555 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 186874 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -237,15 +234,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 24953 # number of replacements -system.cpu.l2cache.sampled_refs 40841 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 147560 # number of replacements +system.cpu.l2cache.sampled_refs 172765 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 4393.054480 # Cycle average of tags in use -system.cpu.l2cache.total_refs 93692 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18266.602159 # Cycle average of tags in use +system.cpu.l2cache.total_refs 108986 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.writebacks 120634 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 258279208 # number of cpu cycles simulated +system.cpu.numCycles 258178168 # number of cpu cycles simulated system.cpu.num_insts 88340673 # Number of instructions executed system.cpu.num_refs 35321418 # Number of memory references system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr index f33d007a7..5992f7131 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr @@ -1,2 +1,3 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt index a58ca9014..667657de7 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,21 +1,21 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1907380 # Simulator instruction rate (inst/s) -host_mem_usage 192852 # Number of bytes of host memory used -host_seconds 71.38 # Real time elapsed on the host -host_tick_rate 2806502009 # Simulator tick rate (ticks/s) +host_inst_rate 595046 # Simulator instruction rate (inst/s) +host_mem_usage 168184 # Number of bytes of host memory used +host_seconds 228.79 # Real time elapsed on the host +host_tick_rate 875480121 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated -sim_seconds 0.200315 # Number of seconds simulated -sim_ticks 200314732000 # Number of ticks simulated +sim_seconds 0.200299 # Number of seconds simulated +sim_ticks 200299240000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21198.421943 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19198.421943 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 20034.528231 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18034.528231 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 37185802 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 964507000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 911551000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 45499 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 873509000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 820553000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 45499 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses) @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 23883.385839 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 21883.385839 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 23541.522491 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 21541.522491 # average overall mshr miss latency system.cpu.dcache.demand_hits 57940701 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 3699632000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 3646676000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002666 # miss rate for demand accesses system.cpu.dcache.demand_misses 154904 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3389824000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3336868000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002666 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 154904 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 23883.385839 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 21883.385839 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 23541.522491 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 21541.522491 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 57940701 # number of overall hits -system.cpu.dcache.overall_miss_latency 3699632000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 3646676000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002666 # miss rate for overall accesses system.cpu.dcache.overall_misses 154904 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3389824000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3336868000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002666 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 154904 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 146582 # number of replacements system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4089.107586 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4089.107061 # Cycle average of tags in use system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 584704000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 584692000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 107271 # number of writebacks system.cpu.icache.ReadReq_accesses 136293812 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 13638.549063 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.549063 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13838.865600 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11838.865600 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 136106788 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 2550736000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 2588200000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.001372 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2176688000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 2214152000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.001372 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 136293812 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 13638.549063 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11638.549063 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13838.865600 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11838.865600 # average overall mshr miss latency system.cpu.icache.demand_hits 136106788 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 2550736000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 2588200000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.001372 # miss rate for demand accesses system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2176688000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 2214152000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.001372 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 136293812 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 13638.549063 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11638.549063 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13838.865600 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11838.865600 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 136106788 # number of overall hits -system.cpu.icache.overall_miss_latency 2550736000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 2588200000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.001372 # miss rate for overall accesses system.cpu.icache.overall_misses 187024 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2176688000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 2214152000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.001372 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,9 +148,9 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 184976 # number of replacements system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 2006.863735 # Cycle average of tags in use +system.cpu.icache.tagsinuse 2006.879224 # Cycle average of tags in use system.cpu.icache.total_refs 136106788 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 142653354000 # Cycle when the warmup percentage was hit. +system.cpu.icache.warmup_cycle 142655430000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses) @@ -165,30 +165,27 @@ system.cpu.l2cache.ReadExReq_mshr_misses 105179 # nu system.cpu.l2cache.ReadReq_accesses 232523 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 191486 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 902814000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.176486 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 41037 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 451407000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.176486 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 41037 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_hits 192777 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 874412000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.170934 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 39746 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 437206000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170934 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 39746 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 4266 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 21963.900609 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 21907.172996 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 93698000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 93456000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 4266 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 46926000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 4266 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 107271 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 107271 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 107271 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_hits 107271 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 5.316385 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.433849 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -197,14 +194,14 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 191486 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3216752000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.432973 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 146216 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 192777 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 3188350000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.429151 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 144925 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1608376000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.432973 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 146216 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 1594175000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.429151 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 144925 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate @@ -212,14 +209,14 @@ system.cpu.l2cache.overall_accesses 337702 # nu system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 191486 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3216752000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.432973 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 146216 # number of overall misses +system.cpu.l2cache.overall_hits 192777 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3188350000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.429151 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 144925 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1608376000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.432973 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 146216 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 1594175000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.429151 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 144925 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -231,15 +228,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 22008 # number of replacements -system.cpu.l2cache.sampled_refs 36484 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 120486 # number of replacements +system.cpu.l2cache.sampled_refs 139196 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 6146.828377 # Cycle average of tags in use -system.cpu.l2cache.total_refs 193963 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 19343.330573 # Cycle average of tags in use +system.cpu.l2cache.total_refs 199586 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.writebacks 87413 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 400629464 # number of cpu cycles simulated +system.cpu.numCycles 400598480 # number of cpu cycles simulated system.cpu.num_insts 136139203 # Number of instructions executed system.cpu.num_refs 58160249 # Number of memory references system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr index b1416b6ce..059f14554 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr @@ -1,4 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7003 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: ignoring syscall time(4026527848, 4026528248, ...) warn: ignoring syscall time(4026527400, 1375098, ...) diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout index b4ac9419f..c5f2dbeb0 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 28 2007 18:29:37 -M5 started Wed Nov 28 18:29:38 2007 -M5 executing on nacho +M5 compiled Feb 13 2008 00:33:29 +M5 started Wed Feb 13 18:35:08 2008 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 200314732000 because target called exit() +Exiting @ tick 200299240000 because target called exit() diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt index bace5dece..cfecc80fb 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 295839323 # Number of BTB hits -global.BPredUnit.BTBLookups 304173612 # Number of BTB lookups -global.BPredUnit.RASInCorrect 120 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 19407214 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 254124042 # Number of conditional branches predicted -global.BPredUnit.lookups 329654643 # Number of BP lookups -global.BPredUnit.usedRAS 23321143 # Number of times the RAS was used to get a target. -host_inst_rate 104317 # Simulator instruction rate (inst/s) -host_mem_usage 152912 # Number of bytes of host memory used -host_seconds 16642.00 # Real time elapsed on the host -host_tick_rate 39307247 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 71970990 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 36581415 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 594992698 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 221743701 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 295818465 # Number of BTB hits +global.BPredUnit.BTBLookups 304122978 # Number of BTB lookups +global.BPredUnit.RASInCorrect 117 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 19402485 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 254075805 # Number of conditional branches predicted +global.BPredUnit.lookups 329612468 # Number of BP lookups +global.BPredUnit.usedRAS 23323532 # Number of times the RAS was used to get a target. +host_inst_rate 97496 # Simulator instruction rate (inst/s) +host_mem_usage 329184 # Number of bytes of host memory used +host_seconds 17806.38 # Real time elapsed on the host +host_tick_rate 36626304 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 70242096 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 35756687 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 594298118 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 221596838 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated -sim_seconds 0.654151 # Number of seconds simulated -sim_ticks 654151114500 # Number of ticks simulated +sim_seconds 0.652182 # Number of seconds simulated +sim_ticks 652181935500 # Number of ticks simulated system.cpu.commit.COM:branches 214632552 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 63247563 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 63182611 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 1235798413 +system.cpu.commit.COM:committed_per_cycle.samples 1232005757 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 591538550 4786.69% - 1 262725182 2125.96% - 2 125553761 1015.97% - 3 79229965 641.12% - 4 49991517 404.53% - 5 29482875 238.57% - 6 23306420 188.59% - 7 10722580 86.77% - 8 63247563 511.80% + 0 589160016 4782.12% + 1 261470532 2122.32% + 2 125479748 1018.50% + 3 79571868 645.87% + 4 48773289 395.89% + 5 29278259 237.65% + 6 23936883 194.29% + 7 11152551 90.52% + 8 63182611 512.84% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,14 +43,14 @@ system.cpu.commit.COM:loads 445666361 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 606571343 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 19406708 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 19401982 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 476380348 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 475043649 # The number of squashed insts skipped by commit system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.753611 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.753611 # CPI: Total CPI of All Threads +system.cpu.cpi 0.751343 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.751343 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_avg_miss_latency 7500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 5500 # average LoadLockedReq mshr miss latency @@ -61,62 +61,62 @@ system.cpu.dcache.LoadLockedReq_misses 1 # nu system.cpu.dcache.LoadLockedReq_mshr_miss_latency 5500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 511433519 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 6211.244353 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3240.935477 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 504159005 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 45183784000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.014224 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 7274514 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 1442447 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 23576230500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.014224 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7274514 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 158840548 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 13691.826036 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7367.776387 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 156591933 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 30787645402 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_accesses 511397910 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5961.540286 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3155.891925 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 504123428 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 43367117500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.014225 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 7274482 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 1270693 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 22957479000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.014225 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7274482 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 158841743 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 13698.127588 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7375.596927 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 156593123 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 30801883656 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.014156 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2248615 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1887954 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 16567292501 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 2248620 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1886759 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 16584914763 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.014156 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 2248615 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 1521.257137 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 2248620 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 1503.843690 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 1667.900476 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 72.179769 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 34783 # number of cycles access was blocked +system.cpu.dcache.avg_refs 72.176220 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 32186 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 65110 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 52913887 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 48402713 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 108597000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 670274067 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 7977.570124 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 4215.371124 # average overall mshr miss latency -system.cpu.dcache.demand_hits 660750938 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 75971429402 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.014208 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9523129 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 3330401 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 40143523001 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.014208 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9523129 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 670239653 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 7788.323716 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4152.259816 # average overall mshr miss latency +system.cpu.dcache.demand_hits 660716551 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 74169001156 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.014209 # miss rate for demand accesses +system.cpu.dcache.demand_misses 9523102 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 3157452 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 39542393763 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.014209 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9523102 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 670274067 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 7977.570124 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 4215.371124 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 670239653 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 7788.323716 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4152.259816 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 660750938 # number of overall hits -system.cpu.dcache.overall_miss_latency 75971429402 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.014208 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9523129 # number of overall misses -system.cpu.dcache.overall_mshr_hits 3330401 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 40143523001 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.014208 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9523129 # number of overall MSHR misses +system.cpu.dcache.overall_hits 660716551 # number of overall hits +system.cpu.dcache.overall_miss_latency 74169001156 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.014209 # miss rate for overall accesses +system.cpu.dcache.overall_misses 9523102 # number of overall misses +system.cpu.dcache.overall_mshr_hits 3157452 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 39542393763 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.014209 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9523102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -128,104 +128,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 9155185 # number of replacements -system.cpu.dcache.sampled_refs 9159281 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 9155159 # number of replacements +system.cpu.dcache.sampled_refs 9159255 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4084.725934 # Cycle average of tags in use -system.cpu.dcache.total_refs 661114789 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 6949556000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2245528 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 23691676 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 575 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 51434078 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2685033131 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 684622012 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 525045997 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 72503618 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 1687 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 2438729 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 758263324 # DTB accesses +system.cpu.dcache.tagsinuse 4084.262567 # Cycle average of tags in use +system.cpu.dcache.total_refs 661080401 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 6949510000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2245532 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 20296019 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 568 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 51416617 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 2683518542 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 684337640 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 525337430 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 72357917 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 1672 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 2034669 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 758199856 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 743549416 # DTB hits -system.cpu.dtb.misses 14713908 # DTB misses -system.cpu.dtb.read_accesses 558500328 # DTB read accesses +system.cpu.dtb.hits 743488243 # DTB hits +system.cpu.dtb.misses 14711613 # DTB misses +system.cpu.dtb.read_accesses 558546548 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 549711484 # DTB read hits -system.cpu.dtb.read_misses 8788844 # DTB read misses -system.cpu.dtb.write_accesses 199762996 # DTB write accesses +system.cpu.dtb.read_hits 549772416 # DTB read hits +system.cpu.dtb.read_misses 8774132 # DTB read misses +system.cpu.dtb.write_accesses 199653308 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 193837932 # DTB write hits -system.cpu.dtb.write_misses 5925064 # DTB write misses -system.cpu.fetch.Branches 329654643 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 338459959 # Number of cache lines fetched -system.cpu.fetch.Cycles 875922747 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 8905673 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 2732615563 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 26330323 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.251971 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 338459959 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 319160466 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.088673 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 193715827 # DTB write hits +system.cpu.dtb.write_misses 5937481 # DTB write misses +system.cpu.fetch.Branches 329612468 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 338613941 # Number of cache lines fetched +system.cpu.fetch.Cycles 876004177 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 8904316 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 2731617625 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 26354316 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.252700 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 338613941 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 319141997 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.094214 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 1308302032 +system.cpu.fetch.rateDist.samples 1304363675 system.cpu.fetch.rateDist.min_value 0 - 0 770839280 5891.91% - 1 46037016 351.88% - 2 31884250 243.71% - 3 48862901 373.48% - 4 119031591 909.82% - 5 67260944 514.11% - 6 45605032 348.58% - 7 40088076 306.41% - 8 138692942 1060.10% + 0 766973475 5880.06% + 1 46084102 353.31% + 2 31888422 244.47% + 3 48880451 374.75% + 4 119066916 912.84% + 5 67245019 515.54% + 6 45549495 349.21% + 7 40080763 307.28% + 8 138595032 1062.55% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 338459878 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 7805.862832 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5445.796460 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 338458974 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 7056500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 338613861 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 7795.580110 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 5439.226519 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 338612956 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 7055000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 904 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 81 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 4923000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 905 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 80 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 4922500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 904 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 905 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 374401.519912 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 374157.962431 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 338459878 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 7805.862832 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5445.796460 # average overall mshr miss latency -system.cpu.icache.demand_hits 338458974 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 7056500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 338613861 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 7795.580110 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 5439.226519 # average overall mshr miss latency +system.cpu.icache.demand_hits 338612956 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 7055000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses -system.cpu.icache.demand_misses 904 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 81 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 4923000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 905 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 80 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 4922500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 904 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 905 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 338459878 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 7805.862832 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5445.796460 # average overall mshr miss latency +system.cpu.icache.overall_accesses 338613861 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 7795.580110 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 5439.226519 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 338458974 # number of overall hits -system.cpu.icache.overall_miss_latency 7056500 # number of overall miss cycles +system.cpu.icache.overall_hits 338612956 # number of overall hits +system.cpu.icache.overall_miss_latency 7055000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses -system.cpu.icache.overall_misses 904 # number of overall misses -system.cpu.icache.overall_mshr_hits 81 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 4923000 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 905 # number of overall misses +system.cpu.icache.overall_mshr_hits 80 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 4922500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 904 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 905 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -238,79 +238,79 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 904 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 905 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 710.981866 # Cycle average of tags in use -system.cpu.icache.total_refs 338458974 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 710.790129 # Cycle average of tags in use +system.cpu.icache.total_refs 338612956 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 198 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 270496625 # Number of branches executed -system.cpu.iew.EXEC:nop 123104848 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.690526 # Inst execution rate -system.cpu.iew.EXEC:refs 759555953 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 199980179 # Number of stores executed +system.cpu.idleCycles 197 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 270601627 # Number of branches executed +system.cpu.iew.EXEC:nop 122950690 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.695694 # Inst execution rate +system.cpu.iew.EXEC:refs 759488153 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 199866169 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1477074261 # num instructions consuming a value -system.cpu.iew.WB:count 2172910244 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.814315 # average fanout of values written-back +system.cpu.iew.WB:consumers 1476471660 # num instructions consuming a value +system.cpu.iew.WB:count 2173120671 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.814447 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1202804007 # num instructions producing a value -system.cpu.iew.WB:rate 1.660863 # insts written-back per cycle -system.cpu.iew.WB:sent 2193655810 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 21011435 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 889547 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 594992698 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 23236538 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 221743701 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2499789841 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 559575774 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 40783144 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2211719271 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 12131 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1202508134 # num instructions producing a value +system.cpu.iew.WB:rate 1.666039 # insts written-back per cycle +system.cpu.iew.WB:sent 2193819887 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 21036346 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 890955 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 594298118 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 23367194 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 221596838 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2498495898 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 559621984 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 40950985 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2211801428 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 13541 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 5627 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 72503618 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 62383 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 2831 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 72357917 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 97673 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 123419 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 36795200 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 338163 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 127122 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 37060344 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 338095 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 340968 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 149326337 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 60838719 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 340968 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 705255 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 20306180 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.326944 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.326944 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 2252502415 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 366768 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 9 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 148631757 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 60691856 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 366768 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 707965 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 20328381 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.330951 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.330951 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 2252752413 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 1478322731 65.63% # Type of FU issued - IntMult 86 0.00% # Type of FU issued + IntAlu 1478789273 65.64% # Type of FU issued + IntMult 88 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 218 0.00% # Type of FU issued + FloatAdd 219 0.00% # Type of FU issued FloatCmp 15 0.00% # Type of FU issued - FloatCvt 143 0.00% # Type of FU issued + FloatCvt 142 0.00% # Type of FU issued FloatMult 14 0.00% # Type of FU issued FloatDiv 24 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 570745775 25.34% # Type of FU issued - MemWrite 203433409 9.03% # Type of FU issued + MemRead 570630847 25.33% # Type of FU issued + MemWrite 203331791 9.03% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 16701899 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007415 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 16520505 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.007333 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 2428134 14.54% # attempts to use FU when none available + IntAlu 2435019 14.74% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -319,105 +319,102 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 10594349 63.43% # attempts to use FU when none available - MemWrite 3679416 22.03% # attempts to use FU when none available + MemRead 10615930 64.26% # attempts to use FU when none available + MemWrite 3469556 21.00% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 1308302032 +system.cpu.iq.ISSUE:issued_per_cycle.samples 1304363675 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 464994043 3554.18% - 1 246274613 1882.40% - 2 221057057 1689.65% - 3 136661391 1044.57% - 4 111222575 850.13% - 5 73372635 560.82% - 6 42938142 328.20% - 7 9505420 72.65% - 8 2276156 17.40% + 0 462770877 3547.87% + 1 244714532 1876.12% + 2 220402920 1689.74% + 3 136161657 1043.89% + 4 111417032 854.19% + 5 74141239 568.41% + 6 43153628 330.84% + 7 9363341 71.78% + 8 2238449 17.16% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.721699 # Inst issue rate -system.cpu.iq.iqInstsAdded 2376684951 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2252502415 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 628382811 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 968171 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 253289947 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 338459995 # ITB accesses +system.cpu.iq.ISSUE:rate 1.727089 # Inst issue rate +system.cpu.iq.iqInstsAdded 2375545164 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2252752413 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 626246255 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 560449 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 250981207 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 338613977 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 338459959 # ITB hits +system.cpu.itb.hits 338613941 # ITB hits system.cpu.itb.misses 36 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 1884767 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 5021.674297 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 3021.674297 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 9464686000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 1884773 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 4937.593280 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2937.593280 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 9306242500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1884767 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 5695152000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 1884773 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 5536696500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1884767 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 7275418 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4312.531905 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2312.531905 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5169529 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 9081713500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.289453 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 2105889 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4869935500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.289453 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 2105889 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 363855 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 4840.345742 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2840.551868 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1761184000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 1884773 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 7275387 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4268.742599 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2268.742599 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5387095 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 8060632500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.259545 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1888292 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 4284048500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259545 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1888292 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 363852 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 4821.983939 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2827.799490 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 1754488500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 363855 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1033549000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 363852 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1028900500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 363855 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2245528 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 2245528 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 2245528 # number of Writeback MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 363852 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2245532 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2245532 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.195593 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.418007 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9160185 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4647.456333 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2647.456333 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5169529 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 18546399500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.435652 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 3990656 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 9160160 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4602.856033 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2602.856033 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 5387095 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 17366875000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.411899 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3773065 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 10565087500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.435652 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 3990656 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 9820745000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.411899 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3773065 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 9160185 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4647.456333 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2647.456333 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 9160160 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4602.856033 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2602.856033 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5169529 # number of overall hits -system.cpu.l2cache.overall_miss_latency 18546399500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.435652 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 3990656 # number of overall misses +system.cpu.l2cache.overall_hits 5387095 # number of overall hits +system.cpu.l2cache.overall_miss_latency 17366875000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.411899 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3773065 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 10565087500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.435652 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 3990656 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 9820745000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.411899 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3773065 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -429,32 +426,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 1375756 # number of replacements -system.cpu.l2cache.sampled_refs 1398753 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 2759208 # number of replacements +system.cpu.l2cache.sampled_refs 2783807 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18802.772512 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5868598 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 505903236000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 1308302230 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 9337863 # Number of cycles rename is blocking +system.cpu.l2cache.tagsinuse 25807.653410 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6731265 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 138143419000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1195675 # number of writebacks +system.cpu.numCycles 1304363872 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 7040310 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 3445344 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 700444791 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 8719600 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 7541 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 3393542111 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2622643654 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1968531217 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 511623129 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 72503618 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 14392122 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 592328254 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 509 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 47 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 29038166 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 45 # count of temporary serializing insts renamed -system.cpu.timesIdled 380 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 2463939 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 700105266 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 8691200 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 11040 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 3391931401 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2621456398 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 1967699206 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 511613721 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 72357917 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 13245923 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 591496243 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 538 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 27887649 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 47 # count of temporary serializing insts renamed +system.cpu.timesIdled 1183 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 9095d9dfe..8ed394bb6 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -169,6 +169,7 @@ euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt index afbd9c385..c79bac28f 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,21 +1,21 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1279505 # Simulator instruction rate (inst/s) -host_mem_usage 199716 # Number of bytes of host memory used -host_seconds 1422.25 # Real time elapsed on the host -host_tick_rate 1826162604 # Simulator tick rate (ticks/s) +host_inst_rate 890836 # Simulator instruction rate (inst/s) +host_mem_usage 328448 # Number of bytes of host memory used +host_seconds 2042.78 # Real time elapsed on the host +host_tick_rate 1270245606 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated -sim_seconds 2.597265 # Number of seconds simulated -sim_ticks 2597265186000 # Number of ticks simulated +sim_seconds 2.594831 # Number of seconds simulated +sim_ticks 2594830590000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 16451.345769 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 14451.345769 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 16114.256812 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 14114.256812 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 118818430000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 116383834000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 104373602000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 101939006000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 18480.410584 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 16480.410584 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 18223.331337 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 16223.331337 # average overall mshr miss latency system.cpu.dcache.demand_hits 595853949 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 175013480000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 172578884000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.015645 # miss rate for demand accesses system.cpu.dcache.demand_misses 9470216 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 156073048000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 153638452000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.015645 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 9470216 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 18480.410584 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 16480.410584 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 18223.331337 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 16223.331337 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 595853949 # number of overall hits -system.cpu.dcache.overall_miss_latency 175013480000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 172578884000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.015645 # miss rate for overall accesses system.cpu.dcache.overall_misses 9470216 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 156073048000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 153638452000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.015645 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 9470216 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,9 +76,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 9107638 # number of replacements system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4079.325443 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4079.310460 # Cycle average of tags in use system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 40727877000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 40726989000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2244708 # number of writebacks system.cpu.dtb.accesses 611922547 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 611.506832 # Cycle average of tags in use +system.cpu.icache.tagsinuse 611.506560 # Cycle average of tags in use system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -171,30 +171,27 @@ system.cpu.l2cache.ReadExReq_mshr_misses 1889320 # nu system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5145160 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 45717232000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.287691 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 2078056 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 22858616000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.287691 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 2078056 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_hits 5348043 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 41253806000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.259604 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1875173 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 20626903000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259604 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1875173 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 358482 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 21999.018082 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 21978.336430 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 7886252000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 7878838000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 358482 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3943302000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 358482 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 2244708 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 2244708 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_hits 2244708 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.187898 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.407812 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -203,14 +200,14 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5145160 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 87282272000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.435376 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 3967376 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 5348043 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 82818846000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.413111 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 3764493 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 43641136000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.435376 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 3967376 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 41409423000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.413111 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 3764493 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate @@ -218,14 +215,14 @@ system.cpu.l2cache.overall_accesses 9112536 # nu system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5145160 # number of overall hits -system.cpu.l2cache.overall_miss_latency 87282272000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.435376 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 3967376 # number of overall misses +system.cpu.l2cache.overall_hits 5348043 # number of overall hits +system.cpu.l2cache.overall_miss_latency 82818846000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.413111 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 3764493 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 43641136000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.435376 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 3967376 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 41409423000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.413111 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 3764493 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -237,15 +234,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 1367767 # number of replacements -system.cpu.l2cache.sampled_refs 1390767 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 2751986 # number of replacements +system.cpu.l2cache.sampled_refs 2776586 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18552.565433 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5824390 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2034930554000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.tagsinuse 25384.669947 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6685498 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 571912424000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1194738 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5194530372 # number of cpu cycles simulated +system.cpu.numCycles 5189661180 # number of cpu cycles simulated system.cpu.num_insts 1819780127 # Number of instructions executed system.cpu.num_refs 613169725 # Number of memory references system.cpu.workload.PROG:num_syscalls 29 # Number of system calls diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr index d0a887867..256a7f3be 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr @@ -1,3 +1,4 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt index 29f0901b4..442001435 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 12981460 # Number of BTB hits -global.BPredUnit.BTBLookups 16925064 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1200 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1943725 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 14569092 # Number of conditional branches predicted -global.BPredUnit.lookups 19413931 # Number of BP lookups -global.BPredUnit.usedRAS 1712105 # Number of times the RAS was used to get a target. -host_inst_rate 84618 # Simulator instruction rate (inst/s) -host_mem_usage 156264 # Number of bytes of host memory used -host_seconds 994.82 # Real time elapsed on the host -host_tick_rate 40727067 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 17086953 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 4901863 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 33850154 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 10567224 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 12982100 # Number of BTB hits +global.BPredUnit.BTBLookups 16925674 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1193 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1943811 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 14569446 # Number of conditional branches predicted +global.BPredUnit.lookups 19414460 # Number of BP lookups +global.BPredUnit.usedRAS 1712096 # Number of times the RAS was used to get a target. +host_inst_rate 78473 # Simulator instruction rate (inst/s) +host_mem_usage 156252 # Number of bytes of host memory used +host_seconds 1072.72 # Real time elapsed on the host +host_tick_rate 37770547 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 17082206 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 4901517 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 33850526 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 10567472 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated -sim_seconds 0.040516 # Number of seconds simulated -sim_ticks 40516250000 # Number of ticks simulated +sim_seconds 0.040517 # Number of seconds simulated +sim_ticks 40517060000 # Number of ticks simulated system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2905596 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 2905382 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 73004137 +system.cpu.commit.COM:committed_per_cycle.samples 73005548 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 35920134 4920.29% - 1 18137405 2484.44% - 2 7363835 1008.69% - 3 3887057 532.44% - 4 2043329 279.89% - 5 1276462 174.85% - 6 715818 98.05% - 7 754501 103.35% - 8 2905596 398.00% + 0 35921098 4920.32% + 1 18137551 2484.41% + 2 7364010 1008.69% + 3 3887256 532.46% + 4 2043377 279.89% + 5 1276568 174.86% + 6 715830 98.05% + 7 754476 103.35% + 8 2905382 397.97% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 20034413 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 26537108 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1931243 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1931330 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 55734183 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 55735776 # The number of squashed insts skipped by commit system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.962613 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.962613 # CPI: Total CPI of All Threads +system.cpu.cpi 0.962632 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.962632 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 23342617 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 8955.533597 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5521.739130 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 23342111 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4531500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses 23342837 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 8742.094862 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5367.588933 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23342331 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4423500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 506 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 125 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2794000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_hits 121 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2716000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6494986 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 24898.921833 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5797.574124 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6493131 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 46187500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses 6494987 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 24890.835580 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5791.644205 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6493132 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 46172500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1855 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 6117 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 10754500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_hits 6116 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 10743500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1855 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13319.361607 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13319.460268 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 29837603 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 21481.999153 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5738.458280 # average overall mshr miss latency -system.cpu.dcache.demand_hits 29835242 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 50719000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 29837824 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 21429.902584 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 5700.762389 # average overall mshr miss latency +system.cpu.dcache.demand_hits 29835463 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 50596000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses system.cpu.dcache.demand_misses 2361 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6242 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 13548500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_hits 6237 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 13459500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 2361 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 29837603 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 21481.999153 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5738.458280 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 29837824 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 21429.902584 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 5700.762389 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 29835242 # number of overall hits -system.cpu.dcache.overall_miss_latency 50719000 # number of overall miss cycles +system.cpu.dcache.overall_hits 29835463 # number of overall hits +system.cpu.dcache.overall_miss_latency 50596000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses system.cpu.dcache.overall_misses 2361 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6242 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 13548500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_hits 6237 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 13459500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 2361 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -123,101 +123,101 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 159 # number of replacements system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1459.079813 # Cycle average of tags in use -system.cpu.dcache.total_refs 29835370 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1459.087304 # Cycle average of tags in use +system.cpu.dcache.total_refs 29835591 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 105 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 3482319 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 3482162 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 12650 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3029666 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 162321559 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 39484158 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 29812969 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 8027574 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 45360 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 224692 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 31857877 # DTB accesses +system.cpu.decode.DECODE:BranchResolved 3029893 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 162323026 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 39485043 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 29813671 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 8027779 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 45343 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 224673 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 31858285 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 31398595 # DTB hits -system.cpu.dtb.misses 459282 # DTB misses -system.cpu.dtb.read_accesses 24667330 # DTB read accesses +system.cpu.dtb.hits 31399009 # DTB hits +system.cpu.dtb.misses 459276 # DTB misses +system.cpu.dtb.read_accesses 24667541 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 24209046 # DTB read hits -system.cpu.dtb.read_misses 458284 # DTB read misses -system.cpu.dtb.write_accesses 7190547 # DTB write accesses +system.cpu.dtb.read_hits 24209262 # DTB read hits +system.cpu.dtb.read_misses 458279 # DTB read misses +system.cpu.dtb.write_accesses 7190744 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 7189549 # DTB write hits -system.cpu.dtb.write_misses 998 # DTB write misses -system.cpu.fetch.Branches 19413931 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 19196468 # Number of cache lines fetched -system.cpu.fetch.Cycles 50093769 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 510771 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 167169540 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2080057 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.239582 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 19196468 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 14693565 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.062994 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 7189747 # DTB write hits +system.cpu.dtb.write_misses 997 # DTB write misses +system.cpu.fetch.Branches 19414460 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 19196880 # Number of cache lines fetched +system.cpu.fetch.Cycles 50094936 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 510856 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 167171428 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2080137 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.239584 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 19196880 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 14694196 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.062976 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 81031712 +system.cpu.fetch.rateDist.samples 81033328 system.cpu.fetch.rateDist.min_value 0 - 0 50134485 6187.02% - 1 3110350 383.84% - 2 2001832 247.04% - 3 3498087 431.69% - 4 4581661 565.42% - 5 1504587 185.68% - 6 2029421 250.45% - 7 1835152 226.47% - 8 12336137 1522.38% + 0 50135346 6187.00% + 1 3110572 383.86% + 2 2001906 247.05% + 3 3498240 431.70% + 4 4581898 565.43% + 5 1504688 185.69% + 6 2029552 250.46% + 7 1835028 226.45% + 8 12336098 1522.35% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 19196110 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5282.113499 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3147.221947 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 19186013 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 53333500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 19196523 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5281.475978 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3147.102526 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 19186428 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 53316500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000526 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 10097 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 358 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 31777500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 10095 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 357 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 31770000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000526 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10097 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 10095 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1900.169654 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1900.587221 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 19196110 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5282.113499 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3147.221947 # average overall mshr miss latency -system.cpu.icache.demand_hits 19186013 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 53333500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 19196523 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5281.475978 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3147.102526 # average overall mshr miss latency +system.cpu.icache.demand_hits 19186428 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 53316500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000526 # miss rate for demand accesses -system.cpu.icache.demand_misses 10097 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 358 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 31777500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 10095 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 357 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 31770000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000526 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10097 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 10095 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 19196110 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5282.113499 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3147.221947 # average overall mshr miss latency +system.cpu.icache.overall_accesses 19196523 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5281.475978 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3147.102526 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 19186013 # number of overall hits -system.cpu.icache.overall_miss_latency 53333500 # number of overall miss cycles +system.cpu.icache.overall_hits 19186428 # number of overall hits +system.cpu.icache.overall_miss_latency 53316500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000526 # miss rate for overall accesses -system.cpu.icache.overall_misses 10097 # number of overall misses -system.cpu.icache.overall_mshr_hits 358 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 31777500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 10095 # number of overall misses +system.cpu.icache.overall_mshr_hits 357 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 31770000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000526 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10097 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 10095 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -229,80 +229,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 8184 # number of replacements -system.cpu.icache.sampled_refs 10097 # Sample count of references to valid blocks. +system.cpu.icache.replacements 8181 # number of replacements +system.cpu.icache.sampled_refs 10095 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1548.546110 # Cycle average of tags in use -system.cpu.icache.total_refs 19186013 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1548.554006 # Cycle average of tags in use +system.cpu.icache.total_refs 19186428 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 789 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 12780650 # Number of branches executed -system.cpu.iew.EXEC:nop 12539176 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.254784 # Inst execution rate -system.cpu.iew.EXEC:refs 31909001 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7192174 # Number of stores executed +system.cpu.idleCycles 793 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 12780668 # Number of branches executed +system.cpu.iew.EXEC:nop 12539131 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.254771 # Inst execution rate +system.cpu.iew.EXEC:refs 31909412 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7192377 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 90874521 # num instructions consuming a value -system.cpu.iew.WB:count 99789775 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.723650 # average fanout of values written-back +system.cpu.iew.WB:consumers 90873941 # num instructions consuming a value +system.cpu.iew.WB:count 99790534 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.723651 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 65761308 # num instructions producing a value -system.cpu.iew.WB:rate 1.231478 # insts written-back per cycle -system.cpu.iew.WB:sent 100700291 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2107867 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 246686 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 33850154 # Number of dispatched load instructions +system.cpu.iew.WB:producers 65761001 # num instructions producing a value +system.cpu.iew.WB:rate 1.231463 # insts written-back per cycle +system.cpu.iew.WB:sent 100701135 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2107897 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 246665 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 33850526 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 429 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1732826 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 10567224 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 147636366 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 24716827 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2166736 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 101678323 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 118341 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 1732647 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 10567472 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 147637958 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 24717035 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2166845 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 101679237 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 118331 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 5 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 8027574 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 156748 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 8027779 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 156734 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 856559 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2771 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.ignoredResponses 2781 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 251773 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 251777 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 9738 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 13815741 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 4064529 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 251773 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 201329 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1906538 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.038839 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.038839 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 103845059 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 13816113 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 4064777 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 251777 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 201293 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1906604 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.038818 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.038818 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 103846082 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 7 0.00% # Type of FU issued - IntAlu 64291165 61.91% # Type of FU issued - IntMult 474912 0.46% # Type of FU issued + IntAlu 64291846 61.91% # Type of FU issued + IntMult 474892 0.46% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2784322 2.68% # Type of FU issued + FloatAdd 2784334 2.68% # Type of FU issued FloatCmp 115616 0.11% # Type of FU issued - FloatCvt 2378756 2.29% # Type of FU issued + FloatCvt 2378731 2.29% # Type of FU issued FloatMult 305685 0.29% # Type of FU issued FloatDiv 755261 0.73% # Type of FU issued FloatSqrt 321 0.00% # Type of FU issued - MemRead 25423503 24.48% # Type of FU issued - MemWrite 7315511 7.04% # Type of FU issued + MemRead 25423709 24.48% # Type of FU issued + MemWrite 7315680 7.04% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 1872956 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt 1872954 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.018036 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 224474 11.99% # attempts to use FU when none available + IntAlu 224469 11.98% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 178 0.01% # attempts to use FU when none available @@ -311,105 +311,102 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 2233 0.12% # attempts to use FU when none available FloatDiv 827912 44.20% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 741386 39.58% # attempts to use FU when none available - MemWrite 73219 3.91% # attempts to use FU when none available + MemRead 741361 39.58% # attempts to use FU when none available + MemWrite 73247 3.91% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 81031712 +system.cpu.iq.ISSUE:issued_per_cycle.samples 81033328 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 34941008 4312.02% - 1 18670913 2304.15% - 2 11746620 1449.63% - 3 6722224 829.58% - 4 5133188 633.48% - 5 2276216 280.90% - 6 1240275 153.06% - 7 251392 31.02% - 8 49876 6.16% + 0 34942372 4312.10% + 1 18670897 2304.10% + 2 11746700 1449.61% + 3 6722042 829.54% + 4 5133527 633.51% + 5 2276322 280.91% + 6 1240213 153.05% + 7 251377 31.02% + 8 49878 6.16% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.281524 # Inst issue rate -system.cpu.iq.iqInstsAdded 135096761 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 103845059 # Number of instructions issued +system.cpu.iq.ISSUE:rate 1.281511 # Inst issue rate +system.cpu.iq.iqInstsAdded 135098398 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 103846082 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 429 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 50310453 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 231145 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 50311951 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 231214 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 47100281 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 19196542 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 47101038 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 19196954 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 19196468 # ITB hits +system.cpu.itb.hits 19196880 # ITB hits system.cpu.itb.misses 74 # ITB misses system.cpu.l2cache.ReadExReq_accesses 1735 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 4502.305476 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2502.305476 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 7811500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 4494.812680 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2494.812680 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 7798500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 1735 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4341500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4328500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1735 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 10602 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4264.852210 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2264.852210 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7185 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14573000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.322298 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3417 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 7739000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.322298 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3417 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 10600 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4263.499557 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2263.499557 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7211 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 14449000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.319717 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3389 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 7671000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319717 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3389 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 4439.024390 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2439.024390 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 546000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 4426.829268 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2426.829268 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 544500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 123 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 300000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 298500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 123 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 105 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 105 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.182564 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.151271 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 12337 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4344.817547 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2344.817547 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7185 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 22384500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.417606 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5152 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 12335 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4341.822795 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2341.822795 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7211 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 22247500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.415403 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5124 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 12080500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.417606 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5152 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 11999500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.415403 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5124 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 12337 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4344.817547 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2344.817547 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 12335 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4341.822795 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2341.822795 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 7185 # number of overall hits -system.cpu.l2cache.overall_miss_latency 22384500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.417606 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5152 # number of overall misses +system.cpu.l2cache.overall_hits 7211 # number of overall hits +system.cpu.l2cache.overall_miss_latency 22247500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.415403 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5124 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 12080500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.417606 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5152 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 11999500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.415403 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5124 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -422,30 +419,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3292 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3345 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2249.807027 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7185 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2256.522025 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7196 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 81032501 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 1616562 # Number of cycles rename is blocking +system.cpu.numCycles 81034121 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 1616502 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 794040 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 40700023 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 985256 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 202768082 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 157137531 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 115831457 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 28813428 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 8027574 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1869404 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 47404096 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 4721 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IQFullEvents 794130 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 40700940 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 985111 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 202769823 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 157139154 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 115832522 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 28814075 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 8027779 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1869307 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 47405161 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 4725 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 464 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4330553 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 4330333 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 453 # count of temporary serializing insts renamed -system.cpu.timesIdled 325 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index da35f8268..11131e743 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -169,6 +169,7 @@ euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt index d2756f127..2349a6461 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,21 +1,21 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1354641 # Simulator instruction rate (inst/s) -host_mem_usage 204632 # Number of bytes of host memory used -host_seconds 67.84 # Real time elapsed on the host -host_tick_rate 1747991543 # Simulator tick rate (ticks/s) +host_inst_rate 877549 # Simulator instruction rate (inst/s) +host_mem_usage 155412 # Number of bytes of host memory used +host_seconds 104.73 # Real time elapsed on the host +host_tick_rate 1132363341 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated -sim_seconds 0.118590 # Number of seconds simulated -sim_ticks 118589630000 # Number of ticks simulated +sim_seconds 0.118589 # Number of seconds simulated +sim_ticks 118589318000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 24316.455696 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22316.455696 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 23658.227848 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21658.227848 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 11526000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 11214000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 10578000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 10266000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 24861.123018 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22861.123018 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 24727.389627 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 22727.389627 # average overall mshr miss latency system.cpu.dcache.demand_hits 26494968 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 58001000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 57689000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses system.cpu.dcache.demand_misses 2333 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 53335000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 53023000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 2333 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 24861.123018 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22861.123018 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 24727.389627 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 22727.389627 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 26494968 # number of overall hits -system.cpu.dcache.overall_miss_latency 58001000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 57689000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses system.cpu.dcache.overall_misses 2333 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 53335000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 53023000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 2333 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1441.457531 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1441.456926 # Cycle average of tags in use system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 104 # number of writebacks @@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 6681 # number of replacements system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1418.474247 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1418.474191 # Cycle average of tags in use system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -171,13 +171,13 @@ system.cpu.l2cache.ReadExReq_mshr_misses 1748 # nu system.cpu.l2cache.ReadReq_accesses 8984 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5916 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 67496000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.341496 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3068 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 33748000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.341496 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3068 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 66924000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.338602 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3042 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 33462000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338602 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3042 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency @@ -188,13 +188,10 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1221000 system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 111 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 104 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 104 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.002030 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.970090 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -203,14 +200,14 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5916 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 105952000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.448751 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4816 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 5942 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 105380000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.446329 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 4790 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 52976000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.448751 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4816 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 52690000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.446329 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 4790 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate @@ -218,14 +215,14 @@ system.cpu.l2cache.overall_accesses 10732 # nu system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5916 # number of overall hits -system.cpu.l2cache.overall_miss_latency 105952000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.448751 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4816 # number of overall misses +system.cpu.l2cache.overall_hits 5942 # number of overall hits +system.cpu.l2cache.overall_miss_latency 105380000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.446329 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 4790 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 52976000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.448751 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4816 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 52690000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.446329 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 4790 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -238,14 +235,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 2955 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3009 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2014.751911 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5916 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2021.711944 # Cycle average of tags in use +system.cpu.l2cache.total_refs 5928 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 237179260 # number of cpu cycles simulated +system.cpu.numCycles 237178636 # number of cpu cycles simulated system.cpu.num_insts 91903056 # Number of instructions executed system.cpu.num_refs 26537141 # Number of memory references system.cpu.workload.PROG:num_syscalls 389 # Number of system calls diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr index f33d007a7..5992f7131 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr @@ -1,2 +1,3 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt index 11499dff9..1a1f8243f 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1710803 # Simulator instruction rate (inst/s) -host_mem_usage 188480 # Number of bytes of host memory used -host_seconds 113.07 # Real time elapsed on the host -host_tick_rate 2391482744 # Simulator tick rate (ticks/s) +host_inst_rate 615476 # Simulator instruction rate (inst/s) +host_mem_usage 157048 # Number of bytes of host memory used +host_seconds 314.29 # Real time elapsed on the host +host_tick_rate 860356799 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193435005 # Number of instructions simulated sim_seconds 0.270398 # Number of seconds simulated @@ -182,13 +182,10 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency 275000 system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 25 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 23 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 23 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 23 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_hits 23 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.136632 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.128249 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -232,9 +229,9 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 4062 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 4078 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2649.703495 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2649.709095 # Cycle average of tags in use system.cpu.l2cache.total_refs 8679 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr index 2fe6268cd..5992f7131 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr @@ -1,3 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7010 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout index 45fe06809..bc5990f1f 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout @@ -18,9 +18,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 28 2007 18:29:37 -M5 started Wed Nov 28 18:29:38 2007 -M5 executing on nacho +M5 compiled Feb 13 2008 00:33:29 +M5 started Wed Feb 13 18:42:03 2008 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second Exiting @ tick 270397899000 because target called exit() |