diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-04-19 09:04:42 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-04-19 09:04:42 -0400 |
| commit | 5dd23833fdeb0f7b152c972f47ff81d5595c6fea (patch) | |
| tree | 70eb9519c91bba922d22723e7e3ba85b65dd7c81 /tests/long | |
| parent | 3d858e5627b539713abb59c14363fb6af180e026 (diff) | |
| download | gem5-5dd23833fdeb0f7b152c972f47ff81d5595c6fea.tar.xz | |
stats: Update stats for ldr_ret_uop (changeset 35198406dd72)
This patch merely bumps the stats to match the changes introduced in
changeset 35198406dd72.
Diffstat (limited to 'tests/long')
5 files changed, 5733 insertions, 5767 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index d2ffa946d..8654e0694 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,143 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.533115 # Number of seconds simulated -sim_ticks 2533114761500 # Number of ticks simulated -final_tick 2533114761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.533112 # Number of seconds simulated +sim_ticks 2533112171000 # Number of ticks simulated +final_tick 2533112171000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 40037 # Simulator instruction rate (inst/s) -host_op_rate 51517 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1681683677 # Simulator tick rate (ticks/s) -host_mem_usage 439348 # Number of bytes of host memory used -host_seconds 1506.30 # Real time elapsed on the host -sim_insts 60307912 # Number of instructions simulated -sim_ops 77599507 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 67901 # Simulator instruction rate (inst/s) +host_op_rate 87370 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2852051940 # Simulator tick rate (ticks/s) +host_mem_usage 401172 # Number of bytes of host memory used +host_seconds 888.17 # Real time elapsed on the host +sim_insts 60307726 # Number of instructions simulated +sim_ops 77599286 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093776 # Number of bytes read from this memory -system.physmem.bytes_read::total 129431504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797568 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783296 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 795840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093456 # Number of bytes read from this memory +system.physmem.bytes_read::total 129429648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 795840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 795840 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3782016 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799368 # Number of bytes written to this memory +system.physmem.bytes_written::total 6798088 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 36 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12462 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142124 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096833 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59114 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 40 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12435 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142119 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096804 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59094 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813132 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47189991 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 910 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314857 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51095792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314857 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314857 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493535 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2684193 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493535 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47189991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 910 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314857 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780616 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53779984 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096833 # Total number of read requests seen -system.physmem.writeReqs 813132 # Total number of write requests seen -system.physmem.cpureqs 218384 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966197312 # Total number of bytes read from memory -system.physmem.bytesWritten 52040448 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129431504 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799368 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 362 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4681 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943940 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943443 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943393 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943981 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943147 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943874 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943783 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943286 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943218 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943604 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943073 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 942962 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943604 # Track reads on a per bank basis +system.physmem.num_writes::total 813112 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47190040 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314175 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51095111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314175 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314175 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493031 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190659 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683690 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47190040 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314175 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53778801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096804 # Total number of read requests seen +system.physmem.writeReqs 813112 # Total number of write requests seen +system.physmem.cpureqs 218338 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966195456 # Total number of bytes read from memory +system.physmem.bytesWritten 52039168 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129429648 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6798088 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 312 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943939 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943442 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943392 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944196 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943979 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943150 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943272 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943868 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943799 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943285 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943215 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943605 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943692 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943079 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 942978 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943601 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 50831 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50410 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50407 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50182 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50278 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50867 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51364 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50898 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51185 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51240 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50713 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50631 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51151 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50915 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50185 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50277 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51366 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50795 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51181 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51246 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50711 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50625 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51223 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32499 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533113625500 # Total gap between requests +system.physmem.numWrRetry 32505 # Number of times wr buffer was full causing retry +system.physmem.totGap 2533111047500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154589 # Categorize read packet sizes +system.physmem.readPktSize::6 154560 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59114 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1039924 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981034 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950254 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2676520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2688059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60688 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59177 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108732 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16575 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20010 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 12714 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59094 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1040132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981079 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2676469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2688032 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649605 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60687 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108699 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157561 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16731 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20063 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 12693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see @@ -151,46 +139,46 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32695 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 32647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32522 # What write queue length does an incoming req see -system.physmem.totQLat 393203348000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485594944250 # Sum of mem lat for all requests -system.physmem.totBusLat 75482355000 # Total cycles spent in databus access -system.physmem.totBankLat 16909241250 # Total cycles spent in bank access -system.physmem.avgQLat 26046.04 # Average queueing delay per request -system.physmem.avgBankLat 1120.08 # Average bank access latency per request +system.physmem.wrQLenPdf::27 32623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32524 # What write queue length does an incoming req see +system.physmem.totQLat 393223335500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485617965500 # Sum of mem lat for all requests +system.physmem.totBusLat 75482460000 # Total cycles spent in databus access +system.physmem.totBankLat 16912170000 # Total cycles spent in bank access +system.physmem.avgQLat 26047.33 # Average queueing delay per request +system.physmem.avgBankLat 1120.27 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32166.12 # Average memory access latency +system.physmem.avgMemAccLat 32167.60 # Average memory access latency system.physmem.avgRdBW 381.43 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.10 # Average consumed read bandwidth in MB/s @@ -198,32 +186,44 @@ system.physmem.avgConsumedWrBW 2.68 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.19 # Average read queue length over time -system.physmem.avgWrQLen 12.50 # Average write queue length over time -system.physmem.readRowHits 15020252 # Number of row buffer hits during reads -system.physmem.writeRowHits 793086 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.50 # Row buffer hit rate for reads +system.physmem.avgWrQLen 11.09 # Average write queue length over time +system.physmem.readRowHits 15020204 # Number of row buffer hits during reads +system.physmem.writeRowHits 793057 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes -system.physmem.avgGap 159215.54 # Average gap between requests +system.physmem.avgGap 159215.87 # Average gap between requests +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14667150 # Number of BP lookups -system.cpu.branchPred.condPredicted 11753528 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704564 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9796618 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7939850 # Number of BTB hits +system.cpu.branchPred.lookups 14674954 # Number of BP lookups +system.cpu.branchPred.condPredicted 11760315 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 703452 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9798337 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7946170 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.046847 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1399135 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72592 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.097129 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1399969 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72392 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14987498 # DTB read hits +system.cpu.checker.dtb.read_hits 14987449 # DTB read hits system.cpu.checker.dtb.read_misses 7302 # DTB read misses -system.cpu.checker.dtb.write_hits 11227787 # DTB write hits +system.cpu.checker.dtb.write_hits 11227758 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -234,13 +234,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994800 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229976 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994751 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229947 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26215285 # DTB hits +system.cpu.checker.dtb.hits 26215207 # DTB hits system.cpu.checker.dtb.misses 9491 # DTB misses -system.cpu.checker.dtb.accesses 26224776 # DTB accesses -system.cpu.checker.itb.inst_hits 61481914 # ITB inst hits +system.cpu.checker.dtb.accesses 26224698 # DTB accesses +system.cpu.checker.itb.inst_hits 61481725 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -257,36 +257,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61486385 # ITB inst accesses -system.cpu.checker.itb.hits 61481914 # DTB hits +system.cpu.checker.itb.inst_accesses 61486196 # ITB inst accesses +system.cpu.checker.itb.hits 61481725 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61486385 # DTB accesses -system.cpu.checker.numCycles 77885316 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61486196 # DTB accesses +system.cpu.checker.numCycles 77885092 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51396830 # DTB read hits -system.cpu.dtb.read_misses 64077 # DTB read misses -system.cpu.dtb.write_hits 11700143 # DTB write hits -system.cpu.dtb.write_misses 15896 # DTB write misses +system.cpu.dtb.read_hits 51400725 # DTB read hits +system.cpu.dtb.read_misses 64230 # DTB read misses +system.cpu.dtb.write_hits 11699827 # DTB write hits +system.cpu.dtb.write_misses 15817 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 6547 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2438 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 402 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 6546 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2361 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 419 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1367 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51460907 # DTB read accesses -system.cpu.dtb.write_accesses 11716039 # DTB write accesses +system.cpu.dtb.perms_faults 1347 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51464955 # DTB read accesses +system.cpu.dtb.write_accesses 11715644 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63096973 # DTB hits -system.cpu.dtb.misses 79973 # DTB misses -system.cpu.dtb.accesses 63176946 # DTB accesses -system.cpu.itb.inst_hits 12326910 # ITB inst hits -system.cpu.itb.inst_misses 11389 # ITB inst misses +system.cpu.dtb.hits 63100552 # DTB hits +system.cpu.dtb.misses 80047 # DTB misses +system.cpu.dtb.accesses 63180599 # DTB accesses +system.cpu.itb.inst_hits 12329192 # ITB inst hits +system.cpu.itb.inst_misses 11376 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -295,148 +295,148 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 4946 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 4940 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2902 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2865 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12338299 # ITB inst accesses -system.cpu.itb.hits 12326910 # DTB hits -system.cpu.itb.misses 11389 # DTB misses -system.cpu.itb.accesses 12338299 # DTB accesses -system.cpu.numCycles 471812928 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12340568 # ITB inst accesses +system.cpu.itb.hits 12329192 # DTB hits +system.cpu.itb.misses 11376 # DTB misses +system.cpu.itb.accesses 12340568 # DTB accesses +system.cpu.numCycles 471811908 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30572325 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 95988347 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14667150 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9338985 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21158726 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5294508 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 123624 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95546847 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2524 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 86189 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195223 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 338 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12323529 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 899693 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5440 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151321070 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.784862 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.149553 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30566850 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 96025902 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14674954 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9346139 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21161280 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5294268 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122956 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95541161 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2622 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 86967 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195337 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 356 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12325832 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 900070 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5461 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151313220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.785216 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.150211 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130177628 86.03% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1303626 0.86% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1711813 1.13% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2496487 1.65% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2227867 1.47% 91.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1109718 0.73% 91.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2758277 1.82% 93.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745468 0.49% 94.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8790186 5.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130167339 86.03% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1302330 0.86% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1712200 1.13% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2496857 1.65% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2222542 1.47% 91.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1109034 0.73% 91.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2758411 1.82% 93.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745566 0.49% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8798941 5.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151321070 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031087 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.203446 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32524080 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95179608 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19189171 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962117 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3466094 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1956870 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171719 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112629435 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 567829 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3466094 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34464944 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36679462 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52534223 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18153241 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6023106 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106095889 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20512 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 985946 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4064605 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 763 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110475366 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485429679 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485339109 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90570 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78390245 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32085120 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830681 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 737048 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12150768 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20327707 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13516010 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1973803 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2472084 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97885695 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983581 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124302750 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167746 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21700961 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 56920385 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501172 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151321070 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.821450 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.535276 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151313220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031103 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.203526 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32523025 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95170118 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19191132 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 962347 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3466598 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1956722 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171732 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112651707 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 566963 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3466598 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34464368 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36692438 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52511672 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18154881 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6023263 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106120156 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20539 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 985607 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4064974 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 783 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110525870 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485527409 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485436293 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91116 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78390038 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32135831 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830318 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736784 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12149928 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20332565 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13516637 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1977838 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2480356 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97929601 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983934 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124328965 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167666 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21748794 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 57017345 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501539 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151313220 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.821666 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.535351 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107116828 70.79% 70.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13508917 8.93% 79.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7078442 4.68% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5929928 3.92% 88.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12595030 8.32% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2803233 1.85% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1696659 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 465338 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 126695 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107094975 70.78% 70.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13518793 8.93% 79.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7075318 4.68% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5935233 3.92% 88.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12598116 8.33% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2801723 1.85% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1697051 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 465636 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 126375 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151321070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151313220 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61883 0.70% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8366537 94.63% 95.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413041 4.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62335 0.71% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8363613 94.62% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413579 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58607180 47.15% 47.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93099 0.07% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58629316 47.16% 47.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93112 0.07% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued @@ -449,10 +449,10 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 18 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 17 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 4 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued @@ -460,353 +460,353 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52915799 42.57% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12320844 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52921084 42.57% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12319626 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124302750 # Type of FU issued -system.cpu.iq.rate 0.263458 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8841465 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071128 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 408992248 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121586509 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85934655 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23175 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12492 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10289 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132768239 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12310 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623420 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124328965 # Type of FU issued +system.cpu.iq.rate 0.263514 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8839530 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071098 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409034606 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121678500 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85964427 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23410 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12602 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10310 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132792371 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12458 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623186 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4673095 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6218 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29888 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1783885 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4678002 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6260 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29908 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1784543 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107776 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 892693 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107773 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 892534 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3466094 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27949012 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 433143 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100090532 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 202747 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20327707 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13516010 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410284 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 112802 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3586 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29888 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350750 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269018 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619768 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121511519 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52083610 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2791231 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3466598 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27942266 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 433430 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100134856 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 201220 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20332565 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13516637 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410804 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113293 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3501 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29908 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350102 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268608 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 618710 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121542985 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52087637 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2785980 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221256 # number of nop insts executed -system.cpu.iew.exec_refs 64295473 # number of memory reference insts executed -system.cpu.iew.exec_branches 11548935 # Number of branches executed -system.cpu.iew.exec_stores 12211863 # Number of stores executed -system.cpu.iew.exec_rate 0.257542 # Inst execution rate -system.cpu.iew.wb_sent 120354811 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85944944 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47248906 # num instructions producing a value -system.cpu.iew.wb_consumers 88214174 # num instructions consuming a value +system.cpu.iew.exec_nop 221321 # number of nop insts executed +system.cpu.iew.exec_refs 64299335 # number of memory reference insts executed +system.cpu.iew.exec_branches 11558025 # Number of branches executed +system.cpu.iew.exec_stores 12211698 # Number of stores executed +system.cpu.iew.exec_rate 0.257609 # Inst execution rate +system.cpu.iew.wb_sent 120384508 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85974737 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47254500 # num instructions producing a value +system.cpu.iew.wb_consumers 88210457 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182159 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535616 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182222 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535702 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21435223 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482409 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535384 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147854976 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.525852 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.516269 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21478461 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482395 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 534359 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147846622 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.525881 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.516310 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120428562 81.45% 81.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13320107 9.01% 90.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3879152 2.62% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2123376 1.44% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1928119 1.30% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 968604 0.66% 96.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1604726 1.09% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 701143 0.47% 98.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2901187 1.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120416670 81.45% 81.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13325889 9.01% 90.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3878179 2.62% 93.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2122601 1.44% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1929203 1.30% 95.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 968068 0.65% 96.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1602055 1.08% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 701521 0.47% 98.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2902436 1.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147854976 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60458293 # Number of instructions committed -system.cpu.commit.committedOps 77749888 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147846622 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60458107 # Number of instructions committed +system.cpu.commit.committedOps 77749667 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386737 # Number of memory references committed -system.cpu.commit.loads 15654612 # Number of loads committed -system.cpu.commit.membars 403603 # Number of memory barriers committed -system.cpu.commit.branches 9961369 # Number of branches committed +system.cpu.commit.refs 27386657 # Number of memory references committed +system.cpu.commit.loads 15654563 # Number of loads committed +system.cpu.commit.membars 403601 # Number of memory barriers committed +system.cpu.commit.branches 9961339 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68855092 # Number of committed integer instructions. -system.cpu.commit.function_calls 991267 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2901187 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68854898 # Number of committed integer instructions. +system.cpu.commit.function_calls 991261 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2902436 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242290263 # The number of ROB reads -system.cpu.rob.rob_writes 201932483 # The number of ROB writes -system.cpu.timesIdled 1770811 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320491858 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4594333550 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307912 # Number of Instructions Simulated -system.cpu.committedOps 77599507 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307912 # Number of Instructions Simulated -system.cpu.cpi 7.823400 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.823400 # CPI: Total CPI of All Threads +system.cpu.rob.rob_reads 242323721 # The number of ROB reads +system.cpu.rob.rob_writes 202019018 # The number of ROB writes +system.cpu.timesIdled 1771597 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320498688 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4594329392 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60307726 # Number of Instructions Simulated +system.cpu.committedOps 77599286 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60307726 # Number of Instructions Simulated +system.cpu.cpi 7.823407 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.823407 # CPI: Total CPI of All Threads system.cpu.ipc 0.127822 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.127822 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550176561 # number of integer regfile reads -system.cpu.int_regfile_writes 88426578 # number of integer regfile writes -system.cpu.fp_regfile_reads 8298 # number of floating regfile reads -system.cpu.fp_regfile_writes 2914 # number of floating regfile writes -system.cpu.misc_regfile_reads 30119271 # number of misc regfile reads -system.cpu.misc_regfile_writes 831902 # number of misc regfile writes -system.cpu.icache.replacements 980182 # number of replacements -system.cpu.icache.tagsinuse 511.616610 # Cycle average of tags in use -system.cpu.icache.total_refs 11263184 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980694 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.484912 # Average number of references to valid blocks. +system.cpu.int_regfile_reads 550308718 # number of integer regfile reads +system.cpu.int_regfile_writes 88462541 # number of integer regfile writes +system.cpu.fp_regfile_reads 8334 # number of floating regfile reads +system.cpu.fp_regfile_writes 2902 # number of floating regfile writes +system.cpu.misc_regfile_reads 30122249 # number of misc regfile reads +system.cpu.misc_regfile_writes 831893 # number of misc regfile writes +system.cpu.icache.replacements 979554 # number of replacements +system.cpu.icache.tagsinuse 511.616693 # Cycle average of tags in use +system.cpu.icache.total_refs 11266265 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980066 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.495415 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6410377000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.616610 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 511.616693 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999251 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999251 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11263184 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11263184 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11263184 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11263184 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11263184 # number of overall hits -system.cpu.icache.overall_hits::total 11263184 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060219 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060219 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060219 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060219 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060219 # number of overall misses -system.cpu.icache.overall_misses::total 1060219 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14018220995 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14018220995 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14018220995 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14018220995 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14018220995 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14018220995 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12323403 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12323403 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12323403 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12323403 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12323403 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12323403 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086033 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.086033 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.086033 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.086033 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.086033 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.086033 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13222.005072 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13222.005072 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13222.005072 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13222.005072 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13222.005072 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13222.005072 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4586 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 11266265 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11266265 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11266265 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11266265 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11266265 # number of overall hits +system.cpu.icache.overall_hits::total 11266265 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1059442 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1059442 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1059442 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1059442 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1059442 # number of overall misses +system.cpu.icache.overall_misses::total 1059442 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13996692496 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13996692496 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13996692496 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13996692496 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13996692496 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13996692496 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12325707 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12325707 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12325707 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12325707 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12325707 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12325707 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085954 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.085954 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.085954 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.085954 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.085954 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.085954 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13211.381554 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13211.381554 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13211.381554 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13211.381554 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13211.381554 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13211.381554 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5064 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 802 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 300 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 15.286667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 17.050505 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 802 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79489 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79489 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79489 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79489 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79489 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79489 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980730 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980730 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980730 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980730 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980730 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980730 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11392389495 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11392389495 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11392389495 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11392389495 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11392389495 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11392389495 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79338 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79338 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79338 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79338 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79338 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79338 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980104 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 980104 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 980104 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 980104 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 980104 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 980104 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11377433497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11377433497 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11377433497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11377433497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11377433497 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11377433497 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7555000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7555000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7555000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7555000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079583 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079583 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079583 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.079583 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079583 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.079583 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11616.234331 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11616.234331 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11616.234331 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11616.234331 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11616.234331 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11616.234331 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079517 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079517 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079517 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.079517 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079517 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.079517 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11608.394106 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11608.394106 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11608.394106 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11608.394106 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11608.394106 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11608.394106 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64360 # number of replacements -system.cpu.l2cache.tagsinuse 51336.859008 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1885213 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129758 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.528684 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2523139048000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36935.695243 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 23.234452 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.003892 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8162.031134 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6215.894286 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563594 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000355 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 64331 # number of replacements +system.cpu.l2cache.tagsinuse 51338.673427 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1885045 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129724 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.531197 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2498168723000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36938.437105 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.056413 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 8154.476716 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6219.702844 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.563636 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000398 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.124543 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.094847 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.783338 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52172 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10475 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 967239 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 386976 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1416862 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607588 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607588 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 42 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112931 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112931 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 52172 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10475 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 967239 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 499907 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1529793 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 52172 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10475 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 967239 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 499907 # number of overall hits -system.cpu.l2cache.overall_hits::total 1529793 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 36 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12355 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10700 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23094 # number of ReadReq misses +system.cpu.l2cache.occ_percent::cpu.inst 0.124427 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.094905 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.783366 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52232 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10453 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 966649 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 387163 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1416497 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607765 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607765 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 40 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 40 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 14 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 14 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 112922 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112922 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 52232 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10453 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 966649 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 500085 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1529419 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 52232 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10453 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 966649 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 500085 # number of overall hits +system.cpu.l2cache.overall_hits::total 1529419 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 40 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12328 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10698 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23068 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2920 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133206 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133206 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 36 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12355 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143906 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156300 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 36 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12355 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143906 # number of overall misses -system.cpu.l2cache.overall_misses::total 156300 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2484000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 186500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 703826000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 629251500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1335748000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 410500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 410500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6753390000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6753390000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2484000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 186500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 703826000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7382641500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8089138000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2484000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 186500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 703826000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7382641500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8089138000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52208 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10478 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 979594 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 397676 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1439956 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607588 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607588 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2962 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2962 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246137 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246137 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52208 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10478 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 979594 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 643813 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1686093 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52208 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10478 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 979594 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 643813 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1686093 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000690 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000286 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012612 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026906 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016038 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985820 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985820 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541186 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541186 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000690 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000286 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012612 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223521 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.092700 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000690 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000286 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012612 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223521 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.092700 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 69000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 62166.666667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56966.895994 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58808.551402 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 57839.612020 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 140.582192 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 140.582192 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50698.842394 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50698.842394 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 69000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 62166.666667 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56966.895994 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51301.832446 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51753.921945 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 69000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 62166.666667 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56966.895994 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51301.832446 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51753.921945 # average overall miss latency +system.cpu.l2cache.ReadExReq_misses::cpu.data 133207 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133207 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 40 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 12328 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143905 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156275 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 40 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 12328 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143905 # number of overall misses +system.cpu.l2cache.overall_misses::total 156275 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2857500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 695307000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 633744500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1332027000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 479000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 479000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6744999000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6744999000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2857500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 695307000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7378743500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8077026000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2857500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 695307000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7378743500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8077026000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52272 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10455 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 978977 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 397861 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1439565 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 607765 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 607765 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2960 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2960 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 17 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 17 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246129 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246129 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52272 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10455 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 978977 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 643990 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1685694 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52272 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10455 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 978977 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 643990 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1685694 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000765 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000191 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012593 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026889 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016024 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986486 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986486 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.176471 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.176471 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541208 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541208 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000765 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000191 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012593 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223458 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.092707 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000765 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000191 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012593 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223458 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.092707 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 71437.500000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56400.632706 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59239.530753 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 57743.497486 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 164.041096 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 164.041096 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50635.469607 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50635.469607 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 71437.500000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56400.632706 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51275.101630 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51684.696849 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 71437.500000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56400.632706 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51275.101630 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51684.696849 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -815,109 +815,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59114 # number of writebacks -system.cpu.l2cache.writebacks::total 59114 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 59094 # number of writebacks +system.cpu.l2cache.writebacks::total 59094 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 36 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12343 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10640 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23022 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 40 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12316 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10637 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 22995 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2920 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133206 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133206 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 36 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12343 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143846 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156228 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 36 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12343 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143846 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156228 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2033785 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 149502 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 549600048 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 494356239 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1046139574 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133207 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133207 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 40 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12316 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143844 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156202 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 40 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12316 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143844 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156202 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2357290 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93251 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 541399772 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 498823739 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1042674052 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29202920 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29202920 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5093264625 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5093264625 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2033785 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 149502 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 549600048 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5587620864 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6139404199 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2033785 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 149502 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 549600048 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5587620864 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6139404199 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5084805426 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5084805426 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2357290 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93251 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 541399772 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5583629165 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6127479478 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2357290 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93251 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 541399772 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5583629165 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6127479478 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5080830 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002364267 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007445097 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26884342911 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26884342911 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002473267 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007554097 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26911803456 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26911803456 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5080830 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193886707178 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193891788008 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000690 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000286 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026755 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015988 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985820 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985820 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541186 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541186 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000690 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000286 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223428 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092657 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000690 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000286 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223428 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092657 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56494.027778 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 49834 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44527.266305 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.052538 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45440.864130 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193914276723 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193919357553 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000765 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026735 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015974 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986486 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986486 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.176471 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.176471 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541208 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541208 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000765 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223364 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092663 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000765 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223364 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092663 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 58932.250000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43959.059110 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46895.152675 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45343.511720 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38236.000068 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38236.000068 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56494.027778 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 49834 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44527.266305 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38844.464664 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39297.719993 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56494.027778 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 49834 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44527.266305 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38844.464664 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39297.719993 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38172.208863 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38172.208863 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 58932.250000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43959.059110 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38817.254560 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39227.919476 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 58932.250000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43959.059110 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38817.254560 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39227.919476 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -927,161 +927,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643301 # number of replacements +system.cpu.dcache.replacements 643478 # number of replacements system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use -system.cpu.dcache.total_refs 21506564 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 643813 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.404986 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 21510687 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643990 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.402207 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 42245000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13753913 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13753913 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259030 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259030 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242896 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242896 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247606 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247606 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21012943 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21012943 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21012943 # number of overall hits -system.cpu.dcache.overall_hits::total 21012943 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737130 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737130 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2963360 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2963360 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13521 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13521 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3700490 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3700490 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3700490 # number of overall misses -system.cpu.dcache.overall_misses::total 3700490 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9747104000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9747104000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104655662232 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104655662232 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180718000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 180718000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 192000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 114402766232 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 114402766232 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 114402766232 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 114402766232 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14491043 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14491043 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222390 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222390 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256417 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256417 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247618 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247618 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24713433 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24713433 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24713433 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24713433 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050868 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050868 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289889 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289889 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052731 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052731 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149736 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149736 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149736 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149736 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13223.046138 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13223.046138 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35316.553585 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35316.553585 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13365.727387 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13365.727387 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30915.572325 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30915.572325 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30915.572325 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30915.572325 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 30983 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 18747 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2620 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 251 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.825573 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 74.689243 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13758124 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13758124 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7259035 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7259035 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242788 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242788 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247600 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247600 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21017159 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21017159 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21017159 # number of overall hits +system.cpu.dcache.overall_hits::total 21017159 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737277 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737277 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963328 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2963328 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13553 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13553 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 17 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 17 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3700605 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3700605 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3700605 # number of overall misses +system.cpu.dcache.overall_misses::total 3700605 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9762499000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9762499000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104581700226 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104581700226 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181087500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 181087500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 257000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 257000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 114344199226 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 114344199226 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 114344199226 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 114344199226 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14495401 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14495401 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222363 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222363 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256341 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256341 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247617 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247617 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24717764 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24717764 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24717764 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24717764 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050863 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050863 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289887 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289887 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052871 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052871 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000069 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000069 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149714 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149714 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149714 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149714 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13241.290587 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13241.290587 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35291.975855 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35291.975855 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13361.432893 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13361.432893 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15117.647059 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15117.647059 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30898.785260 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30898.785260 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30898.785260 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30898.785260 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 30275 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 18688 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2630 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 248 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.511407 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 75.354839 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607588 # number of writebacks -system.cpu.dcache.writebacks::total 607588 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351544 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351544 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714338 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714338 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1354 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1354 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3065882 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3065882 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3065882 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3065882 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385586 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385586 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249022 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249022 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12167 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12167 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634608 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634608 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634608 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634608 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4803296500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4803296500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8203666916 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8203666916 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141299500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141299500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13006963416 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13006963416 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13006963416 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13006963416 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395564500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395564500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36699724336 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36699724336 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219095288836 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 219095288836 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026609 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026609 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024360 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024360 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047450 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047450 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.writebacks::writebacks 607765 # number of writebacks +system.cpu.dcache.writebacks::total 607765 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351549 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351549 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714318 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714318 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1341 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1341 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065867 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065867 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065867 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065867 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385728 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385728 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249010 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249010 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12212 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12212 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634738 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634738 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634738 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634738 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4809640000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4809640000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8195040415 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8195040415 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141777000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141777000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 223000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 223000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13004680415 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13004680415 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13004680415 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13004680415 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395703000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395703000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36727476899 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36727476899 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219123179899 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 219123179899 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026610 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026610 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024359 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024359 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047640 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047640 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000069 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000069 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.025679 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025679 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12457.134076 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12457.134076 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32943.542803 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32943.542803 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11613.339361 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11613.339361 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20496.059640 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20496.059640 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20496.059640 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20496.059640 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12468.993695 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12468.993695 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32910.487189 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32910.487189 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11609.646250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11609.646250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13117.647059 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13117.647059 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20488.265103 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20488.265103 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20488.265103 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20488.265103 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1103,16 +1103,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229535673761 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229535673761 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229535673761 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229535673761 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229570022553 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229570022553 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229570022553 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229570022553 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83046 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83043 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 85477463e..e24b483f1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,173 +1,151 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.602779 # Number of seconds simulated -sim_ticks 2602778916500 # Number of ticks simulated -final_tick 2602778916500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.102958 # Number of seconds simulated +sim_ticks 1102958416500 # Number of ticks simulated +final_tick 1102958416500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48820 # Simulator instruction rate (inst/s) -host_op_rate 62855 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2024215186 # Simulator tick rate (ticks/s) -host_mem_usage 443440 # Number of bytes of host memory used -host_seconds 1285.82 # Real time elapsed on the host -sim_insts 62774383 # Number of instructions simulated -sim_ops 80820330 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 148 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 148 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 148 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 395584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4382196 # Number of bytes read from this memory +host_inst_rate 66795 # Simulator instruction rate (inst/s) +host_op_rate 85978 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1196309321 # Simulator tick rate (ticks/s) +host_mem_usage 404244 # Number of bytes of host memory used +host_seconds 921.97 # Real time elapsed on the host +sim_insts 61582525 # Number of instructions simulated +sim_ops 79269125 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 410752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4380596 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 426624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5245232 # Number of bytes read from this memory -system.physmem.bytes_read::total 131562340 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 395584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 426624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 822208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4273600 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 405056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5224880 # Number of bytes read from this memory +system.physmem.bytes_read::total 59182180 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 410752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 405056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 815808 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4259968 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7302736 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6181 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68544 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory +system.physmem.bytes_written::total 7287312 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6418 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68519 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6666 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81983 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15302224 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66775 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6329 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81665 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257812 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66562 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 824059 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46531239 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 151985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1683660 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 163911 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2015243 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50546875 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 151985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 163911 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315896 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1641937 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6531 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1157277 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2805746 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1641937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46531239 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 151985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1690192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 163911 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3172520 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53352621 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15302224 # Total number of read requests seen -system.physmem.writeReqs 824059 # Total number of write requests seen -system.physmem.cpureqs 244149 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 979342336 # Total number of bytes read from memory -system.physmem.bytesWritten 52739776 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131562340 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7302736 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 337 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 14071 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956809 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 956626 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 956229 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956838 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956744 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 956129 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 956236 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956861 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955985 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 956063 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 956435 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956372 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955730 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 955657 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 956452 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51554 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51377 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51697 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51535 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50985 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51049 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51663 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 52119 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51405 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51482 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51861 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51782 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51276 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51190 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51930 # Track writes on a per bank basis +system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory +system.physmem.num_writes::total 823398 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44207273 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 754 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 372409 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3971678 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 367245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4737150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53657671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 372409 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 367245 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 739654 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3862311 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2729336 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6607060 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3862311 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44207273 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 754 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 372409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3987091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 367245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7466486 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60264731 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257812 # Total number of read requests seen +system.physmem.writeReqs 823398 # Total number of write requests seen +system.physmem.cpureqs 242000 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 400499968 # Total number of bytes read from memory +system.physmem.bytesWritten 52697472 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 59182180 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7287312 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 78 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 12579 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 391407 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 391213 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 390854 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 391610 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 391518 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 390872 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 390926 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 391637 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 391404 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 390705 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 390857 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 391237 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 391233 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 390526 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 390472 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 391263 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51413 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51231 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 51006 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51680 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51540 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50963 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50973 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51665 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 52039 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51352 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51495 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51885 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51842 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51248 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51173 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51893 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32645 # Number of times wr buffer was full causing retry -system.physmem.totGap 2602777722500 # Total gap between requests +system.physmem.numWrRetry 32627 # Number of times wr buffer was full causing retry +system.physmem.totGap 1102957282500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes -system.physmem.readPktSize::3 15138816 # Categorize read packet sizes +system.physmem.readPktSize::3 6094848 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 163303 # Categorize read packet sizes +system.physmem.readPktSize::6 162859 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 757284 # Categorize write packet sizes +system.physmem.writePktSize::2 756836 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66775 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1059619 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 995756 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 964447 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3596573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2710922 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2723432 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2682017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 62131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 60256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 110205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 159682 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 109728 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 17046 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16811 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 12933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66562 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 493912 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 430569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 391898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1441588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1085856 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1098172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1064332 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 26910 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24845 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 44429 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 63782 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 44273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12054 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 11817 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 15280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 7853 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -178,304 +156,308 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32658 # What write queue length does an incoming req see -system.physmem.totQLat 398163291750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 491955679250 # Sum of mem lat for all requests -system.physmem.totBusLat 76509435000 # Total cycles spent in databus access -system.physmem.totBankLat 17282952500 # Total cycles spent in bank access -system.physmem.avgQLat 26020.54 # Average queueing delay per request -system.physmem.avgBankLat 1129.47 # Average bank access latency per request +system.physmem.wrQLenPdf::0 2898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32643 # What write queue length does an incoming req see +system.physmem.totQLat 199244474250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 239068869250 # Sum of mem lat for all requests +system.physmem.totBusLat 31288670000 # Total cycles spent in databus access +system.physmem.totBankLat 8535725000 # Total cycles spent in bank access +system.physmem.avgQLat 31839.72 # Average queueing delay per request +system.physmem.avgBankLat 1364.03 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32150.00 # Average memory access latency -system.physmem.avgRdBW 376.27 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.26 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.55 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.81 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 38203.74 # Average memory access latency +system.physmem.avgRdBW 363.11 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 47.78 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 53.66 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.10 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.19 # Average read queue length over time -system.physmem.avgWrQLen 12.56 # Average write queue length over time -system.physmem.readRowHits 15222567 # Number of row buffer hits during reads -system.physmem.writeRowHits 800487 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.48 # Row buffer hit rate for reads +system.physmem.busUtil 3.21 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.22 # Average read queue length over time +system.physmem.avgWrQLen 10.41 # Average write queue length over time +system.physmem.readRowHits 6213843 # Number of row buffer hits during reads +system.physmem.writeRowHits 799878 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.14 # Row buffer hit rate for writes -system.physmem.avgGap 161399.73 # Average gap between requests -system.l2c.replacements 73011 # number of replacements -system.l2c.tagsinuse 53067.424425 # Cycle average of tags in use -system.l2c.total_refs 1872250 # Total number of references to valid blocks. -system.l2c.sampled_refs 138181 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.549258 # Average number of references to valid blocks. +system.physmem.avgGap 155758.31 # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 72564 # number of replacements +system.l2c.tagsinuse 53751.759262 # Cycle average of tags in use +system.l2c.total_refs 1839556 # Total number of references to valid blocks. +system.l2c.sampled_refs 137761 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.353242 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37745.757624 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 5.485079 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000341 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4193.697813 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2948.995369 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 14.004673 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.955179 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4039.578813 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4118.949534 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.575955 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000084 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 39378.859227 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 4.194190 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.010198 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4015.520084 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2826.859367 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 10.896267 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3720.882915 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3794.537014 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.600874 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000064 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.063991 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.044998 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000214 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.061639 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.062850 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.809745 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 23032 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4492 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 392957 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 165711 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 32830 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5777 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 607042 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 201661 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1433502 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 582954 # number of Writeback hits -system.l2c.Writeback_hits::total 582954 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1024 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 725 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1749 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 207 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 160 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 367 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 47437 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 59291 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106728 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 23032 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4492 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 392957 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 213148 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 32830 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5777 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 607042 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 260952 # number of demand (read+write) hits -system.l2c.demand_hits::total 1540230 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 23032 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4492 # number of overall hits -system.l2c.overall_hits::cpu0.inst 392957 # number of overall hits -system.l2c.overall_hits::cpu0.data 213148 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 32830 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5777 # number of overall hits -system.l2c.overall_hits::cpu1.inst 607042 # number of overall hits -system.l2c.overall_hits::cpu1.data 260952 # number of overall hits -system.l2c.overall_hits::total 1540230 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 14 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6061 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6334 # number of ReadReq misses +system.l2c.occ_percent::cpu0.inst 0.061272 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.043134 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000166 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.056776 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.057900 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.820187 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 21638 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4069 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 385706 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 166655 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30870 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5056 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 589485 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 198042 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1401521 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 580941 # number of Writeback hits +system.l2c.Writeback_hits::total 580941 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1130 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 742 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1872 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 193 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 147 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 340 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 48042 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 58929 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 106971 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 21638 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4069 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 385706 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 214697 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 30870 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5056 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 589485 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 256971 # number of demand (read+write) hits +system.l2c.demand_hits::total 1508492 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 21638 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4069 # number of overall hits +system.l2c.overall_hits::cpu0.inst 385706 # number of overall hits +system.l2c.overall_hits::cpu0.data 214697 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30870 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5056 # number of overall hits +system.l2c.overall_hits::cpu1.inst 589485 # number of overall hits +system.l2c.overall_hits::cpu1.data 256971 # number of overall hits +system.l2c.overall_hits::total 1508492 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 13 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6298 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6402 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 17 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6630 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6368 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25427 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5641 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4355 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 9996 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 765 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 590 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1355 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63626 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 76877 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140503 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 14 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6061 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 69960 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu1.inst 6294 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 6282 # number of ReadReq misses +system.l2c.ReadReq_misses::total 25309 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5141 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3789 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8930 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 641 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 416 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1057 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63471 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 76579 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140050 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6298 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 69873 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 17 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6630 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 83245 # number of demand (read+write) misses -system.l2c.demand_misses::total 165930 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 14 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6061 # number of overall misses -system.l2c.overall_misses::cpu0.data 69960 # number of overall misses +system.l2c.demand_misses::cpu1.inst 6294 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 82861 # number of demand (read+write) misses +system.l2c.demand_misses::total 165359 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 13 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu0.inst 6298 # number of overall misses +system.l2c.overall_misses::cpu0.data 69873 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 17 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6630 # number of overall misses -system.l2c.overall_misses::cpu1.data 83245 # number of overall misses -system.l2c.overall_misses::total 165930 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 934000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 118000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 341015500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 362076499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1414500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 68500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 395474000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 399545499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1500646498 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 8933491 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 12111000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 21044491 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 544500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3029499 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3573999 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3156158498 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4120290994 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7276449492 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 934000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 118000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 341015500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3518234997 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1414500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 68500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 395474000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4519836493 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8777095990 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 934000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 118000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 341015500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3518234997 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1414500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 68500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 395474000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4519836493 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8777095990 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 23046 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 4494 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 399018 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 172045 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 32847 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 5778 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 613672 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 208029 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1458929 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 582954 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 582954 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 6665 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5080 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 11745 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 972 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 750 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1722 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111063 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 136168 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247231 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 23046 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 4494 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 399018 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 283108 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 32847 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 5778 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 613672 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 344197 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1706160 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 23046 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 4494 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 399018 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 283108 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 32847 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 5778 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 613672 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 344197 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1706160 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000607 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000445 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015190 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036816 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000518 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000173 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010804 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.030611 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.017429 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.846362 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.857283 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.851086 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.787037 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.786667 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.786876 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.572882 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.564575 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.568307 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000607 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000445 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015190 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.247114 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000518 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000173 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010804 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.241853 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.097253 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000607 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000445 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015190 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.247114 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000518 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000173 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010804 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.241853 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.097253 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66714.285714 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 59000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 56263.900346 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 57163.956268 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83205.882353 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 68500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 59649.170437 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 62742.697707 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 59017.835293 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1583.671512 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2780.941447 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2105.291216 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 711.764706 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5134.744068 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 2637.637638 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49604.854902 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53595.886858 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 51788.570294 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66714.285714 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 56263.900346 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 50289.236664 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83205.882353 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 68500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 59649.170437 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 54295.591243 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52896.377930 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66714.285714 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 56263.900346 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 50289.236664 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83205.882353 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 68500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 59649.170437 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 54295.591243 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52896.377930 # average overall miss latency +system.l2c.overall_misses::cpu1.inst 6294 # number of overall misses +system.l2c.overall_misses::cpu1.data 82861 # number of overall misses +system.l2c.overall_misses::total 165359 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 867000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 187000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 349540500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 369073494 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1249500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 380545500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 397720997 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1499183991 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 8713990 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 11767499 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 20481489 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 612500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2911000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 3523500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3164041493 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4107833997 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7271875490 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 867000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 187000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 349540500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3533114987 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1249500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 380545500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4505554994 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8771059481 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 867000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 187000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 349540500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3533114987 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1249500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 380545500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4505554994 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8771059481 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 21651 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 4072 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 392004 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 173057 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 30887 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 5056 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 595779 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 204324 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1426830 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 580941 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 580941 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6271 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4531 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10802 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 834 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 563 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1397 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111513 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 135508 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247021 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 21651 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 4072 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 392004 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 284570 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 30887 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5056 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 595779 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 339832 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1673851 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 21651 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 4072 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 392004 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 284570 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 30887 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5056 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 595779 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 339832 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1673851 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000600 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000737 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.016066 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036994 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000550 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010564 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.030745 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.017738 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.819805 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836239 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.826699 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.768585 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.738899 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.756621 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.569180 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.565125 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.566956 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000600 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000737 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.016066 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.245539 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000550 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010564 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.243829 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.098790 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000600 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000737 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.016066 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.245539 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000550 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010564 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.243829 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.098790 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66692.307692 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 62333.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55500.238171 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 57649.717901 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 73500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 60461.630124 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 63311.206145 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 59235.212415 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1694.999027 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3105.700449 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2293.559798 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 955.538222 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6997.596154 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3333.491012 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49850.191316 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53641.781650 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 51923.423706 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66692.307692 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 62333.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 55500.238171 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 50564.810256 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 73500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 60461.630124 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 54374.856615 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 53042.528565 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66692.307692 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 62333.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 55500.238171 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 50564.810256 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 73500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 60461.630124 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 54374.856615 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 53042.528565 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -484,180 +466,168 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 66775 # number of writebacks -system.l2c.writebacks::total 66775 # number of writebacks +system.l2c.writebacks::writebacks 66562 # number of writebacks +system.l2c.writebacks::total 66562 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 37 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 26 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 25 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 37 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 26 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 25 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 37 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 26 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 14 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 6056 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6297 # number of ReadReq MSHR misses +system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 25 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 76 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 13 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6293 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6364 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 17 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6623 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 6342 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 25352 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 5641 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 4355 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 9996 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 765 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 590 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1355 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 63626 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 76877 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140503 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 14 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 6056 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 69923 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6286 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 6257 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 25233 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 5141 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3789 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8930 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 641 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 416 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1057 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 63471 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 76579 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140050 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 13 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6293 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 69835 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 17 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6623 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 83219 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 165855 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 14 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 6056 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 69923 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6286 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 82836 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 165283 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 13 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 6293 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 69835 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 17 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6623 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 83219 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 165855 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 760014 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 93251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 265447152 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 281377954 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1202016 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 56251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 312696352 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 319251979 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1180884969 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 56679510 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 44248783 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 100928293 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7679249 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 5912584 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 13591833 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2367645075 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3158595985 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5526241060 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 760014 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93251 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 265447152 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2649023029 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1202016 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 56251 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 312696352 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3477847964 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6707126029 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 760014 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93251 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 265447152 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2649023029 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1202016 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 56251 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 312696352 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3477847964 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6707126029 # number of overall MSHR miss cycles +system.l2c.overall_mshr_misses::cpu1.inst 6286 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 82836 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 165283 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 703763 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 149502 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 271011114 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 287092769 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1035767 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 301672543 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 317723170 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1179388628 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51700505 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38483216 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 90183721 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6462619 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4189409 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 10652028 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2377449956 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3149883999 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5527333955 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 703763 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 149502 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 271011114 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2664542725 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1035767 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 301672543 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3467607169 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6706722583 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 703763 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 149502 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 271011114 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2664542725 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1035767 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 301672543 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3467607169 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6706722583 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5286835 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12335434047 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12406848538 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1838032 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154945975242 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167288534156 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1114449737 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25984901303 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 27099351040 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154667566747 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167081540152 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050379735 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25959313642 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 27009693377 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5286835 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13449883784 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13457228273 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1838032 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180930876545 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 194387885196 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000607 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000445 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015177 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036601 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000518 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000173 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010792 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030486 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.017377 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.846362 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.857283 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.851086 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.787037 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.786667 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.786876 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.572882 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564575 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.568307 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000607 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000445 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015177 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.246983 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000518 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000173 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010792 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.241777 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.097210 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000607 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000445 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015177 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.246983 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000518 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000173 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010792 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.241777 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.097210 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54286.714286 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 43832.092470 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44684.445609 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70706.823529 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47213.702552 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 50339.321823 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 46579.558575 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10047.776990 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10160.455339 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10096.868047 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10038.233987 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10021.328814 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10030.873063 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37211.911404 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41086.358534 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 39331.836758 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54286.714286 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 43832.092470 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37884.859474 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70706.823529 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47213.702552 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41791.513525 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40439.697501 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54286.714286 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 43832.092470 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37884.859474 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70706.823529 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47213.702552 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41791.513525 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40439.697501 # average overall mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180626880389 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 194091233529 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000600 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000737 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016053 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036774 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000550 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010551 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030623 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017685 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.819805 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836239 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.826699 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.768585 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.738899 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.756621 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569180 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.565125 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.566956 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000600 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000737 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016053 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.245405 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000550 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010551 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.243756 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098744 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000600 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000737 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016053 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.245405 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000550 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010551 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.243756 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.098744 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54135.615385 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 43065.487685 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45112.000157 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 60927.470588 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47991.177696 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 50778.834905 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 46739.928982 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10056.507489 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10156.562681 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10098.960918 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10082.088924 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10070.694712 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10077.604541 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37457.263254 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41132.477559 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 39466.861514 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54135.615385 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 43065.487685 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38154.832462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 60927.470588 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47991.177696 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41861.113151 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40577.207474 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54135.615385 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 43065.487685 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38154.832462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 60927.470588 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47991.177696 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41861.113151 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40577.207474 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -678,38 +648,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 6065134 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4623218 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 295247 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3783915 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2943990 # Number of BTB hits +system.cpu0.branchPred.lookups 5991996 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4570590 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 295222 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3736406 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2908427 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.802752 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 682666 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28697 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.840229 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 670993 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28752 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8964880 # DTB read hits -system.cpu0.dtb.read_misses 29505 # DTB read misses -system.cpu0.dtb.write_hits 5211507 # DTB write hits -system.cpu0.dtb.write_misses 5768 # DTB write misses +system.cpu0.dtb.read_hits 8901229 # DTB read hits +system.cpu0.dtb.read_misses 28750 # DTB read misses +system.cpu0.dtb.write_hits 5135502 # DTB write hits +system.cpu0.dtb.write_misses 5613 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1820 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1111 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 256 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1817 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 968 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 288 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 587 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8994385 # DTB read accesses -system.cpu0.dtb.write_accesses 5217275 # DTB write accesses +system.cpu0.dtb.perms_faults 548 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8929979 # DTB read accesses +system.cpu0.dtb.write_accesses 5141115 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14176387 # DTB hits -system.cpu0.dtb.misses 35273 # DTB misses -system.cpu0.dtb.accesses 14211660 # DTB accesses -system.cpu0.itb.inst_hits 4271941 # ITB inst hits -system.cpu0.itb.inst_misses 5082 # ITB inst misses +system.cpu0.dtb.hits 14036731 # DTB hits +system.cpu0.dtb.misses 34363 # DTB misses +system.cpu0.dtb.accesses 14071094 # DTB accesses +system.cpu0.itb.inst_hits 4213364 # ITB inst hits +system.cpu0.itb.inst_misses 5048 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -718,534 +688,530 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1340 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1344 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1395 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1487 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4277023 # ITB inst accesses -system.cpu0.itb.hits 4271941 # DTB hits -system.cpu0.itb.misses 5082 # DTB misses -system.cpu0.itb.accesses 4277023 # DTB accesses -system.cpu0.numCycles 68310391 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4218412 # ITB inst accesses +system.cpu0.itb.hits 4213364 # DTB hits +system.cpu0.itb.misses 5048 # DTB misses +system.cpu0.itb.accesses 4218412 # DTB accesses +system.cpu0.numCycles 67828518 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11985780 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32442629 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6065134 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3626656 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7605462 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1460769 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 62659 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 21080761 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5794 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 46842 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 87230 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 220 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4270468 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157226 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2109 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41924364 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.999512 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.380874 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11769514 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 31989018 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 5991996 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3579420 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7508503 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1450801 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 60684 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20631180 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4911 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 48154 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 85409 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4211784 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 156653 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2012 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41149957 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.004329 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.384713 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34326103 81.88% 81.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 570380 1.36% 83.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 823787 1.96% 85.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 686899 1.64% 86.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 778226 1.86% 88.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 563231 1.34% 90.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 676382 1.61% 91.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 356953 0.85% 92.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3142403 7.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33648798 81.77% 81.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 562155 1.37% 83.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 818096 1.99% 85.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 677471 1.65% 86.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 773499 1.88% 88.65% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 558438 1.36% 90.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 664363 1.61% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 352105 0.86% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3095032 7.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41924364 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088788 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.474930 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12503811 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 21012915 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6898585 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 522974 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 986079 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 948336 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64663 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40543036 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 211520 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 986079 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 13078116 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5721380 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13152385 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6797650 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2188754 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 39433741 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1845 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 443177 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1244404 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 41 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39808870 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 178177695 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 178143549 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34146 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31430562 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8378307 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 419823 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 376669 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5441918 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7757618 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5774212 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1139116 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1209168 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 37348543 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 904610 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37701629 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 81879 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6330369 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13296779 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 257143 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41924364 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.899277 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.510411 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41149957 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088340 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.471616 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12268271 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20578267 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6812810 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 512754 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 977855 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 934513 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64660 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 39970940 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 212731 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 977855 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12837244 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5740254 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12723807 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6707246 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2163551 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38872652 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1850 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 437651 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1233683 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 23 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39221318 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175562913 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175528548 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34365 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30916412 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8304905 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 410995 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 369967 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5350401 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7642102 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5682819 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1122438 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1201311 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36799804 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 894837 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37219527 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 80251 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6274775 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13129416 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256270 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41149957 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.904485 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.513383 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26590532 63.43% 63.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5818938 13.88% 77.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3210799 7.66% 84.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2498063 5.96% 90.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2114705 5.04% 95.97% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 942628 2.25% 98.21% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 502674 1.20% 99.41% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 189300 0.45% 99.86% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 56725 0.14% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26028016 63.25% 63.25% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5729313 13.92% 77.17% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3155280 7.67% 84.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2465546 5.99% 90.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2105206 5.12% 95.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 932712 2.27% 98.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 494007 1.20% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 184426 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 55451 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41924364 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41149957 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 26752 2.49% 2.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 460 0.04% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 840001 78.12% 80.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 208012 19.35% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 26761 2.50% 2.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 453 0.04% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 841654 78.63% 81.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 201534 18.83% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22644819 60.06% 60.20% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 48004 0.13% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9425277 25.00% 85.33% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5530613 14.67% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22319985 59.97% 60.11% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46930 0.13% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9357970 25.14% 85.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5441771 14.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37701629 # Type of FU issued -system.cpu0.iq.rate 0.551916 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1075225 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028519 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 118511451 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44591434 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34839098 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8242 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4622 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3868 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38720352 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4288 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 316630 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37219527 # Type of FU issued +system.cpu0.iq.rate 0.548730 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1070402 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028759 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 116765436 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 43977253 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34319519 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8378 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4660 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3869 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38233387 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4393 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 306639 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1380313 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2666 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13062 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 544614 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1370211 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2367 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13030 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 536244 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149563 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5584 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192745 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5335 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 986079 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4106132 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 100687 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 38371433 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 85430 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7757618 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5774212 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 577195 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40897 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3001 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13062 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 150158 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117749 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 267907 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37323557 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9281925 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 378072 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 977855 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4123044 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 98683 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37812695 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 84467 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7642102 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5682819 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571073 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39963 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2983 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13030 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 149756 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117796 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 267552 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36844879 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9216416 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 374648 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118280 # number of nop insts executed -system.cpu0.iew.exec_refs 14765828 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4915455 # Number of branches executed -system.cpu0.iew.exec_stores 5483903 # Number of stores executed -system.cpu0.iew.exec_rate 0.546382 # Inst execution rate -system.cpu0.iew.wb_sent 37128467 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34842966 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18565053 # num instructions producing a value -system.cpu0.iew.wb_consumers 35706535 # num instructions consuming a value +system.cpu0.iew.exec_nop 118054 # number of nop insts executed +system.cpu0.iew.exec_refs 14611375 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4852197 # Number of branches executed +system.cpu0.iew.exec_stores 5394959 # Number of stores executed +system.cpu0.iew.exec_rate 0.543206 # Inst execution rate +system.cpu0.iew.wb_sent 36651456 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34323388 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18278983 # num instructions producing a value +system.cpu0.iew.wb_consumers 35164474 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.510068 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.519934 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.506032 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.519814 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6140110 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 647467 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 231710 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40938285 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.775989 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.737548 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6082175 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638567 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 231668 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40172102 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.778393 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.739779 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 29080513 71.04% 71.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5796475 14.16% 85.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1964427 4.80% 89.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 998229 2.44% 92.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 793584 1.94% 94.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 517255 1.26% 95.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 395614 0.97% 96.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 224138 0.55% 97.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1168050 2.85% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28502177 70.95% 70.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5716215 14.23% 85.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1915316 4.77% 89.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 977454 2.43% 92.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 784200 1.95% 94.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 521856 1.30% 95.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 386686 0.96% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 221286 0.55% 97.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1146912 2.85% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40938285 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24057849 # Number of instructions committed -system.cpu0.commit.committedOps 31767677 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40172102 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23670658 # Number of instructions committed +system.cpu0.commit.committedOps 31269703 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11606903 # Number of memory references committed -system.cpu0.commit.loads 6377305 # Number of loads committed -system.cpu0.commit.membars 231785 # Number of memory barriers committed -system.cpu0.commit.branches 4305044 # Number of branches committed +system.cpu0.commit.refs 11418466 # Number of memory references committed +system.cpu0.commit.loads 6271891 # Number of loads committed +system.cpu0.commit.membars 229601 # Number of memory barriers committed +system.cpu0.commit.branches 4243665 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28078801 # Number of committed integer instructions. -system.cpu0.commit.function_calls 498475 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1168050 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27627466 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489162 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1146912 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 76811981 # The number of ROB reads -system.cpu0.rob.rob_writes 76803371 # The number of ROB writes -system.cpu0.timesIdled 362519 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26386027 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5137205074 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23977107 # Number of Instructions Simulated -system.cpu0.committedOps 31686935 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23977107 # Number of Instructions Simulated -system.cpu0.cpi 2.848984 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.848984 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.351002 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.351002 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 174070948 # number of integer regfile reads -system.cpu0.int_regfile_writes 34592870 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3226 # number of floating regfile reads +system.cpu0.rob.rob_reads 75526096 # The number of ROB reads +system.cpu0.rob.rob_writes 75683450 # The number of ROB writes +system.cpu0.timesIdled 360623 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26678561 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2138046604 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23589916 # Number of Instructions Simulated +system.cpu0.committedOps 31188961 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23589916 # Number of Instructions Simulated +system.cpu0.cpi 2.875318 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.875318 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.347788 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.347788 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171729807 # number of integer regfile reads +system.cpu0.int_regfile_writes 34069963 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3242 # number of floating regfile reads system.cpu0.fp_regfile_writes 898 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13196303 # number of misc regfile reads -system.cpu0.misc_regfile_writes 457522 # number of misc regfile writes -system.cpu0.icache.replacements 399011 # number of replacements -system.cpu0.icache.tagsinuse 511.581015 # Cycle average of tags in use -system.cpu0.icache.total_refs 3839482 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 399523 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.610165 # Average number of references to valid blocks. +system.cpu0.misc_regfile_reads 13000351 # number of misc regfile reads +system.cpu0.misc_regfile_writes 450996 # number of misc regfile writes +system.cpu0.icache.replacements 392023 # number of replacements +system.cpu0.icache.tagsinuse 511.011023 # Cycle average of tags in use +system.cpu0.icache.total_refs 3788789 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 392535 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.652105 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6567370000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.581015 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999182 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999182 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3839482 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3839482 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3839482 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3839482 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3839482 # number of overall hits -system.cpu0.icache.overall_hits::total 3839482 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 430854 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 430854 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 430854 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 430854 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 430854 # number of overall misses -system.cpu0.icache.overall_misses::total 430854 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5887932497 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5887932497 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5887932497 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5887932497 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5887932497 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5887932497 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4270336 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4270336 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4270336 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4270336 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4270336 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4270336 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100895 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100895 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100895 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100895 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100895 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100895 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13665.725506 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13665.725506 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13665.725506 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13665.725506 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13665.725506 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13665.725506 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2816 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::cpu0.inst 511.011023 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.998068 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998068 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3788789 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3788789 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3788789 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3788789 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3788789 # number of overall hits +system.cpu0.icache.overall_hits::total 3788789 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 422860 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 422860 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 422860 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 422860 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 422860 # number of overall misses +system.cpu0.icache.overall_misses::total 422860 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5794359497 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5794359497 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5794359497 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5794359497 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5794359497 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5794359497 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4211649 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4211649 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4211649 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4211649 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4211649 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4211649 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100402 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100402 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100402 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100402 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100402 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100402 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13702.784602 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13702.784602 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13702.784602 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13702.784602 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13702.784602 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13702.784602 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2670 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 151 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 161 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.649007 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.583851 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31313 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 31313 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 31313 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 31313 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 31313 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 31313 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 399541 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 399541 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 399541 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 399541 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 399541 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 399541 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4811758497 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4811758497 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4811758497 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4811758497 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4811758497 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4811758497 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30304 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30304 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30304 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30304 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30304 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30304 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 392556 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 392556 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 392556 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 392556 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 392556 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 392556 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4741290497 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4741290497 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4741290497 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4741290497 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4741290497 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4741290497 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7889500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7889500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7889500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7889500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093562 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093562 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093562 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093562 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093562 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093562 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12043.215833 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12043.215833 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12043.215833 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12043.215833 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12043.215833 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12043.215833 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093207 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093207 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093207 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093207 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093207 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093207 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12077.997781 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12077.997781 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12077.997781 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12077.997781 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12077.997781 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12077.997781 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 274797 # number of replacements -system.cpu0.dcache.tagsinuse 481.556098 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9422136 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 275309 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.223858 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 275942 # number of replacements +system.cpu0.dcache.tagsinuse 461.279186 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9251897 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276454 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.466316 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 43505000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 481.556098 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.940539 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.940539 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5871189 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5871189 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3228929 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3228929 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139484 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139484 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137178 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137178 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9100118 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9100118 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9100118 # number of overall hits -system.cpu0.dcache.overall_hits::total 9100118 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 393197 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 393197 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1579789 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1579789 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8860 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8860 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7754 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7754 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1972986 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1972986 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1972986 # number of overall misses -system.cpu0.dcache.overall_misses::total 1972986 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5458812500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5458812500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60787010865 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 60787010865 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88634000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 88634000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50172500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 50172500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 66245823365 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 66245823365 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 66245823365 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 66245823365 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6264386 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6264386 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4808718 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4808718 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148344 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 148344 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144932 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144932 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11073104 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11073104 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11073104 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11073104 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062767 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.062767 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.328526 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.328526 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059726 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059726 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053501 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053501 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178178 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.178178 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178178 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.178178 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13883.148905 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13883.148905 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38477.930195 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38477.930195 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10003.837472 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10003.837472 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6470.531339 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6470.531339 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33576.428502 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33576.428502 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33576.428502 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33576.428502 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8479 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 4081 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 642 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 79 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.207165 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 51.658228 # average number of cycles each access was blocked +system.cpu0.dcache.occ_blocks::cpu0.data 461.279186 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.900936 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.900936 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5774894 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5774894 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3157331 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3157331 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139041 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139041 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137030 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137030 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8932225 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8932225 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8932225 # number of overall hits +system.cpu0.dcache.overall_hits::total 8932225 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 392966 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 392966 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1582314 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1582314 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8784 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8784 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7484 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7484 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1975280 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1975280 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1975280 # number of overall misses +system.cpu0.dcache.overall_misses::total 1975280 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5474748500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5474748500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60929978373 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 60929978373 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88607500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88607500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46564000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 46564000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 66404726873 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 66404726873 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 66404726873 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 66404726873 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6167860 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6167860 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4739645 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4739645 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147825 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 147825 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144514 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144514 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10907505 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10907505 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10907505 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10907505 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063712 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063712 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333847 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.333847 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059422 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059422 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051787 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051787 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181094 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.181094 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181094 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.181094 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13931.863062 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13931.863062 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38506.881929 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38506.881929 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10087.374772 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10087.374772 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6221.806521 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6221.806521 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33617.880439 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33617.880439 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33617.880439 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33617.880439 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8609 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2195 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 639 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 78 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.472613 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 28.141026 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 255199 # number of writebacks -system.cpu0.dcache.writebacks::total 255199 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204311 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 204311 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1449026 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1449026 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 480 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 480 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1653337 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1653337 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1653337 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1653337 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188886 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188886 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130763 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130763 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8380 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8380 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7752 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7752 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319649 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319649 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319649 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319649 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2359118000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2359118000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4052722492 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4052722492 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66818500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66818500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34670500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34670500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6411840492 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6411840492 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6411840492 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6411840492 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13437088000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13437088000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1251489878 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1251489878 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14688577878 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14688577878 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030152 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030152 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027193 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027193 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056490 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056490 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053487 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053487 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028867 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028867 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028867 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028867 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12489.639253 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12489.639253 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30992.884012 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30992.884012 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7973.568019 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7973.568019 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4472.458720 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4472.458720 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20059.003757 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20059.003757 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20059.003757 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20059.003757 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256402 # number of writebacks +system.cpu0.dcache.writebacks::total 256402 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204348 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 204348 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1452057 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1452057 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 461 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 461 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1656405 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1656405 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1656405 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1656405 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188618 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188618 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130257 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130257 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8323 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8323 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7482 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7482 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 318875 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 318875 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 318875 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 318875 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2375120000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2375120000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4054292491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4054292491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66886000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66886000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31600000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31600000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6429412491 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6429412491 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6429412491 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6429412491 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13513828500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13513828500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180296878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180296878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14694125378 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14694125378 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030581 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030581 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027482 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027482 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056303 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056303 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051774 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051774 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029234 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029234 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029234 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029234 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12592.223436 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12592.223436 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31125.332926 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31125.332926 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8036.284993 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8036.284993 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4223.469661 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4223.469661 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20162.798874 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20162.798874 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20162.798874 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20162.798874 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1253,38 +1219,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9260108 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7598823 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 418413 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6211409 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5330705 # Number of BTB hits +system.cpu1.branchPred.lookups 9066051 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7453207 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 407044 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6058627 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5236584 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 85.821188 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 799378 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 44339 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 86.431860 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 771955 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42437 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43181625 # DTB read hits -system.cpu1.dtb.read_misses 38342 # DTB read misses -system.cpu1.dtb.write_hits 6975478 # DTB write hits -system.cpu1.dtb.write_misses 10879 # DTB write misses +system.cpu1.dtb.read_hits 42902362 # DTB read hits +system.cpu1.dtb.read_misses 36935 # DTB read misses +system.cpu1.dtb.write_hits 6824519 # DTB write hits +system.cpu1.dtb.write_misses 10718 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3080 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 279 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2005 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2714 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 302 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 684 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43219967 # DTB read accesses -system.cpu1.dtb.write_accesses 6986357 # DTB write accesses +system.cpu1.dtb.perms_faults 645 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42939297 # DTB read accesses +system.cpu1.dtb.write_accesses 6835237 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 50157103 # DTB hits -system.cpu1.dtb.misses 49221 # DTB misses -system.cpu1.dtb.accesses 50206324 # DTB accesses -system.cpu1.itb.inst_hits 8542294 # ITB inst hits -system.cpu1.itb.inst_misses 5605 # ITB inst misses +system.cpu1.dtb.hits 49726881 # DTB hits +system.cpu1.dtb.misses 47653 # DTB misses +system.cpu1.dtb.accesses 49774534 # DTB accesses +system.cpu1.itb.inst_hits 8392998 # ITB inst hits +system.cpu1.itb.inst_misses 5431 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1293,114 +1259,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1533 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1531 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1566 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1493 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8547899 # ITB inst accesses -system.cpu1.itb.hits 8542294 # DTB hits -system.cpu1.itb.misses 5605 # DTB misses -system.cpu1.itb.accesses 8547899 # DTB accesses -system.cpu1.numCycles 410577330 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8398429 # ITB inst accesses +system.cpu1.itb.hits 8392998 # DTB hits +system.cpu1.itb.misses 5431 # DTB misses +system.cpu1.itb.accesses 8398429 # DTB accesses +system.cpu1.numCycles 408779942 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 20304470 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 67058817 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9260108 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6130083 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14383842 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4002399 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 71431 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77735291 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5936 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42666 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 133916 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 201 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8540383 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 747213 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2975 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 115405308 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.704397 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.049572 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 19814855 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 66055643 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9066051 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6008539 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14146730 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3957386 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 64683 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77267641 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 42583 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 129813 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 133 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8391200 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 740435 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2770 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114169430 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.700459 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.044215 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 101028811 87.54% 87.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 815655 0.71% 88.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 964627 0.84% 89.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1914792 1.66% 90.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1533608 1.33% 92.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 591916 0.51% 92.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2159319 1.87% 94.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 420670 0.36% 94.82% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5975910 5.18% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 100030180 87.62% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 795116 0.70% 88.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 937715 0.82% 89.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1888304 1.65% 90.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1526967 1.34% 92.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 578073 0.51% 92.63% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2128721 1.86% 94.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 409818 0.36% 94.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5874536 5.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 115405308 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022554 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.163328 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21846277 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 77383941 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 13006148 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 540398 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2628544 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1139252 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 100555 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 76481536 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 334945 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2628544 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 23246660 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 32001614 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 41094778 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 12051133 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4382579 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 70980554 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18812 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 684543 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3106754 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 398 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 74967908 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 326797465 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 326738119 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59346 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50107015 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 24860893 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 461639 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 401710 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8025653 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13466262 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8327830 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1061558 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1475331 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 64680036 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1175419 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 90315471 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 95817 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 16379719 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 46059622 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 276388 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 115405308 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.782594 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.520017 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114169430 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022178 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.161592 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21335636 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 76916914 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12791603 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 523584 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2601693 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1104215 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 98013 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 75225150 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 326089 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2601693 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22720139 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 31942959 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40740266 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11835652 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4328721 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 69758398 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18799 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 669077 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3086745 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 378 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 73725482 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 321189458 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 321130296 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59162 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49052273 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 24673209 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 444958 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 387932 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7868643 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13207791 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8146456 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1036357 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1539549 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 63487430 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1157915 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89117422 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94398 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 16230957 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 45692140 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 277223 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114169430 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.780572 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.518996 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 84537407 73.25% 73.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8582035 7.44% 80.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4411988 3.82% 84.51% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3834760 3.32% 87.83% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10634435 9.21% 97.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1994605 1.73% 98.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1053936 0.91% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 278337 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 77805 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83779617 73.38% 73.38% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8401659 7.36% 80.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4300327 3.77% 84.51% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3769049 3.30% 87.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10578609 9.27% 97.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1966316 1.72% 98.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1028949 0.90% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 270980 0.24% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 73924 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 115405308 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114169430 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32501 0.41% 0.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 990 0.01% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 31906 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 996 0.01% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available @@ -1428,395 +1394,395 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7572486 95.74% 96.16% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 303829 3.84% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7548325 95.86% 96.28% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 292902 3.72% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 38327866 42.44% 42.79% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61115 0.07% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1704 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 44265466 49.01% 91.87% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7345367 8.13% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37601994 42.19% 42.55% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59184 0.07% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43968762 49.34% 91.95% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7172015 8.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 90315471 # Type of FU issued -system.cpu1.iq.rate 0.219972 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7909806 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.087580 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 304076071 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 82244261 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 54749584 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14863 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8084 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6852 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 97903555 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7790 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 356637 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89117422 # Type of FU issued +system.cpu1.iq.rate 0.218008 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7874129 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088357 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 300405264 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 80884614 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53615647 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15005 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8070 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6847 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96669700 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7919 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 342898 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3487877 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 4207 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17725 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1325961 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3454228 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3835 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 16932 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1307521 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31951985 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 889967 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31906117 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 888056 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2628544 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24227901 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 361425 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 65958607 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 113659 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13466262 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8327830 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 878933 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 66066 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3533 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17725 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 207255 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 158224 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 365479 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 87865625 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43564360 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2449846 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2601693 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24180087 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 359608 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 64749015 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 111417 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13207791 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8146456 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 869148 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 64619 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3744 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 16932 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 200731 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 155107 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 355838 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 86675355 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43272699 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2442067 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 103152 # number of nop insts executed -system.cpu1.iew.exec_refs 50845626 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7156733 # Number of branches executed -system.cpu1.iew.exec_stores 7281266 # Number of stores executed -system.cpu1.iew.exec_rate 0.214005 # Inst execution rate -system.cpu1.iew.wb_sent 86881552 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 54756436 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30516075 # num instructions producing a value -system.cpu1.iew.wb_consumers 54547350 # num instructions consuming a value +system.cpu1.iew.exec_nop 103670 # number of nop insts executed +system.cpu1.iew.exec_refs 50383092 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6989591 # Number of branches executed +system.cpu1.iew.exec_stores 7110393 # Number of stores executed +system.cpu1.iew.exec_rate 0.212034 # Inst execution rate +system.cpu1.iew.wb_sent 85698110 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53622494 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29929482 # num instructions producing a value +system.cpu1.iew.wb_consumers 53410166 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.133364 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.559442 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131177 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560371 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 16276380 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 899031 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 319402 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 112776764 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.436287 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.405749 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 16109317 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880692 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 310619 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111567737 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.431575 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.399552 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 95648521 84.81% 84.81% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8417489 7.46% 92.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2180084 1.93% 94.21% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1287029 1.14% 95.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1270394 1.13% 96.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 584036 0.52% 96.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1018862 0.90% 97.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 513430 0.46% 98.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1856919 1.65% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94819418 84.99% 84.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8239382 7.39% 92.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2114964 1.90% 94.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1255344 1.13% 95.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1246323 1.12% 96.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 567268 0.51% 97.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1001355 0.90% 97.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 504765 0.45% 98.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1818918 1.63% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 112776764 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38866915 # Number of instructions committed -system.cpu1.commit.committedOps 49203034 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111567737 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38062248 # Number of instructions committed +system.cpu1.commit.committedOps 48149803 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16980254 # Number of memory references committed -system.cpu1.commit.loads 9978385 # Number of loads committed -system.cpu1.commit.membars 195514 # Number of memory barriers committed -system.cpu1.commit.branches 6118836 # Number of branches committed +system.cpu1.commit.refs 16592498 # Number of memory references committed +system.cpu1.commit.loads 9753563 # Number of loads committed +system.cpu1.commit.membars 190132 # Number of memory barriers committed +system.cpu1.commit.branches 5967184 # Number of branches committed system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43616937 # Number of committed integer instructions. -system.cpu1.commit.function_calls 553185 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1856919 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 42685255 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534609 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1818918 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 175333256 # The number of ROB reads -system.cpu1.rob.rob_writes 133679925 # The number of ROB writes -system.cpu1.timesIdled 1420320 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 295172022 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4794342654 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38797276 # Number of Instructions Simulated -system.cpu1.committedOps 49133395 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38797276 # Number of Instructions Simulated -system.cpu1.cpi 10.582633 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.582633 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.094494 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.094494 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 393458890 # number of integer regfile reads -system.cpu1.int_regfile_writes 57301820 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4905 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2316 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18909839 # number of misc regfile reads -system.cpu1.misc_regfile_writes 419175 # number of misc regfile writes -system.cpu1.icache.replacements 613709 # number of replacements -system.cpu1.icache.tagsinuse 498.827741 # Cycle average of tags in use -system.cpu1.icache.total_refs 7879826 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 614221 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 12.828975 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74226336500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.827741 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974273 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974273 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7879826 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7879826 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7879826 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7879826 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7879826 # number of overall hits -system.cpu1.icache.overall_hits::total 7879826 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 660506 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 660506 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 660506 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 660506 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 660506 # number of overall misses -system.cpu1.icache.overall_misses::total 660506 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8908973494 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8908973494 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8908973494 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8908973494 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8908973494 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8908973494 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8540332 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8540332 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8540332 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8540332 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8540332 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8540332 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.077340 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.077340 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.077340 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.077340 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.077340 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.077340 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13488.103808 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13488.103808 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13488.103808 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13488.103808 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13488.103808 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13488.103808 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2847 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 1026 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 181 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.729282 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 1026 # average number of cycles each access was blocked +system.cpu1.rob.rob_reads 172963873 # The number of ROB reads +system.cpu1.rob.rob_writes 131212452 # The number of ROB writes +system.cpu1.timesIdled 1408163 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 294610512 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1796500385 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37992609 # Number of Instructions Simulated +system.cpu1.committedOps 48080164 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37992609 # Number of Instructions Simulated +system.cpu1.cpi 10.759460 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.759460 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092941 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092941 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 387855246 # number of integer regfile reads +system.cpu1.int_regfile_writes 56190036 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4937 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2324 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18474333 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405457 # number of misc regfile writes +system.cpu1.icache.replacements 595836 # number of replacements +system.cpu1.icache.tagsinuse 480.940966 # Cycle average of tags in use +system.cpu1.icache.total_refs 7749865 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 596348 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 12.995541 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74230255500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 480.940966 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.939338 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.939338 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7749865 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7749865 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7749865 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7749865 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7749865 # number of overall hits +system.cpu1.icache.overall_hits::total 7749865 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 641285 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 641285 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 641285 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 641285 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 641285 # number of overall misses +system.cpu1.icache.overall_misses::total 641285 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8628357996 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8628357996 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8628357996 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8628357996 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8628357996 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8628357996 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8391150 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8391150 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8391150 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8391150 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8391150 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8391150 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076424 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.076424 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076424 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.076424 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076424 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.076424 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13454.794664 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13454.794664 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13454.794664 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13454.794664 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13454.794664 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13454.794664 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 3208 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 172 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.651163 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46258 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 46258 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 46258 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 46258 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 46258 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 46258 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 614248 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 614248 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 614248 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 614248 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 614248 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 614248 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7279881995 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7279881995 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7279881995 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7279881995 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7279881995 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7279881995 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44912 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44912 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44912 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44912 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44912 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44912 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 596373 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 596373 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 596373 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 596373 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 596373 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 596373 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7067932496 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7067932496 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7067932496 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7067932496 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7067932496 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7067932496 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2836500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2836500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2836500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 2836500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071923 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071923 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071923 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.071923 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071923 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.071923 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11851.698329 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11851.698329 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11851.698329 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11851.698329 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11851.698329 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11851.698329 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071072 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071072 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071072 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.071072 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071072 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.071072 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11851.529992 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11851.529992 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11851.529992 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11851.529992 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11851.529992 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11851.529992 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 363224 # number of replacements -system.cpu1.dcache.tagsinuse 486.354105 # Cycle average of tags in use -system.cpu1.dcache.total_refs 13022243 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 363588 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 35.815932 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 70357393000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 486.354105 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.949910 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.949910 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8515751 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8515751 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4271525 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4271525 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 100014 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 100014 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 97065 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 97065 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12787276 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12787276 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12787276 # number of overall hits -system.cpu1.dcache.overall_hits::total 12787276 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 404538 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 404538 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1563969 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1563969 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14182 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14182 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10922 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10922 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1968507 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1968507 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1968507 # number of overall misses -system.cpu1.dcache.overall_misses::total 1968507 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6180682000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6180682000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61609358019 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 61609358019 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131994000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 131994000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58853500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 58853500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 67790040019 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 67790040019 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 67790040019 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 67790040019 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8920289 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8920289 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5835494 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5835494 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 114196 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 114196 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107987 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 107987 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14755783 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14755783 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14755783 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14755783 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045350 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045350 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.268010 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.268010 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124190 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124190 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101142 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101142 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.133406 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.133406 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.133406 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.133406 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15278.371871 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15278.371871 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39392.953453 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 39392.953453 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9307.149908 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9307.149908 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5388.527742 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5388.527742 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34437.286745 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 34437.286745 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34437.286745 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 34437.286745 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 29332 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 12945 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3336 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 164 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.792566 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 78.932927 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 360523 # number of replacements +system.cpu1.dcache.tagsinuse 474.680181 # Cycle average of tags in use +system.cpu1.dcache.total_refs 12675453 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 360873 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 35.124415 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 70362031000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 474.680181 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.927110 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.927110 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8307994 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8307994 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4138933 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4138933 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97647 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 97647 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94867 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 94867 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12446927 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12446927 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12446927 # number of overall hits +system.cpu1.dcache.overall_hits::total 12446927 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 399316 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 399316 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1556536 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1556536 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13951 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13951 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10617 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10617 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1955852 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1955852 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1955852 # number of overall misses +system.cpu1.dcache.overall_misses::total 1955852 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6096380000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6096380000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61399313493 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 61399313493 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129350500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 129350500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53940000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 53940000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 67495693493 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 67495693493 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 67495693493 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 67495693493 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8707310 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8707310 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5695469 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5695469 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111598 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 111598 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105484 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105484 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14402779 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14402779 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14402779 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14402779 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045860 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045860 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273294 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273294 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125011 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125011 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100650 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100650 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135797 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135797 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135797 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135797 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15267.056667 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15267.056667 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39446.124916 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39446.124916 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9271.772633 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9271.772633 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5080.531224 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5080.531224 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34509.611920 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 34509.611920 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34509.611920 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 34509.611920 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 27560 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 11546 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3309 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 159 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.328800 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 72.616352 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 327755 # number of writebacks -system.cpu1.dcache.writebacks::total 327755 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 173193 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 173193 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1400907 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1400907 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1451 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1451 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1574100 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1574100 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1574100 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1574100 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231345 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 231345 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163062 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 163062 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12731 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12731 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10917 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10917 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 394407 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 394407 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 394407 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 394407 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2902469000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2902469000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5146576709 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5146576709 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90486500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90486500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 37019500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 37019500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8049045709 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8049045709 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8049045709 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8049045709 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169298073000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169298073000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35738645182 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35738645182 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 205036718182 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 205036718182 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025935 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025935 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027943 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027943 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111484 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111484 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101096 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101096 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026729 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026729 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026729 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026729 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12546.063239 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12546.063239 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31562.085029 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31562.085029 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7107.572068 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7107.572068 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3390.995695 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3390.995695 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20407.968695 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20407.968695 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20407.968695 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20407.968695 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 324541 # number of writebacks +system.cpu1.dcache.writebacks::total 324541 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171136 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 171136 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1394941 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1394941 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1433 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1433 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566077 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1566077 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566077 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1566077 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228180 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228180 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161595 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161595 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12518 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12518 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10611 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10611 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389775 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389775 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389775 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389775 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2858069500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2858069500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5115737712 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5115737712 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88636500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88636500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32718000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32718000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7973807212 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7973807212 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7973807212 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7973807212 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168990097000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168990097000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35704290190 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35704290190 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204694387190 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204694387190 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026206 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026206 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028373 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028373 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112170 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112170 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100593 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100593 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027062 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027062 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027062 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027062 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12525.503988 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12525.503988 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31657.772283 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31657.772283 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7080.723758 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7080.723758 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3083.404015 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3083.404015 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20457.461900 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20457.461900 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20457.461900 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20457.461900 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1838,18 +1804,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1245278858614 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1245278858614 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1245278858614 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1245278858614 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540179772418 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 540179772418 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540179772418 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 540179772418 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 42369 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41712 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 50346 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48858 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 7716042a9..97fb1321d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,143 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.533115 # Number of seconds simulated -sim_ticks 2533114761500 # Number of ticks simulated -final_tick 2533114761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.533112 # Number of seconds simulated +sim_ticks 2533112171000 # Number of ticks simulated +final_tick 2533112171000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48903 # Simulator instruction rate (inst/s) -host_op_rate 62925 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2054075271 # Simulator tick rate (ticks/s) -host_mem_usage 439344 # Number of bytes of host memory used -host_seconds 1233.21 # Real time elapsed on the host -sim_insts 60307912 # Number of instructions simulated -sim_ops 77599507 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 62365 # Simulator instruction rate (inst/s) +host_op_rate 80247 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2619544402 # Simulator tick rate (ticks/s) +host_mem_usage 400132 # Number of bytes of host memory used +host_seconds 967.00 # Real time elapsed on the host +sim_insts 60307726 # Number of instructions simulated +sim_ops 77599286 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093776 # Number of bytes read from this memory -system.physmem.bytes_read::total 129431504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797568 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783296 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 795840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093456 # Number of bytes read from this memory +system.physmem.bytes_read::total 129429648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 795840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 795840 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3782016 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799368 # Number of bytes written to this memory +system.physmem.bytes_written::total 6798088 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 36 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12462 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142124 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096833 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59114 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 40 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12435 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142119 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096804 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59094 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813132 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47189991 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 910 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314857 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51095792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314857 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314857 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493535 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2684193 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493535 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47189991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 910 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314857 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780616 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53779984 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096833 # Total number of read requests seen -system.physmem.writeReqs 813132 # Total number of write requests seen -system.physmem.cpureqs 218384 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966197312 # Total number of bytes read from memory -system.physmem.bytesWritten 52040448 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129431504 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799368 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 362 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4681 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943940 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943443 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943393 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943981 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943147 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943874 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943783 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943286 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943218 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943604 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943073 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 942962 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943604 # Track reads on a per bank basis +system.physmem.num_writes::total 813112 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47190040 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314175 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51095111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314175 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314175 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493031 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190659 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683690 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47190040 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314175 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53778801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096804 # Total number of read requests seen +system.physmem.writeReqs 813112 # Total number of write requests seen +system.physmem.cpureqs 218338 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966195456 # Total number of bytes read from memory +system.physmem.bytesWritten 52039168 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129429648 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6798088 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 312 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943939 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943442 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943392 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944196 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943979 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943150 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943272 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943868 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943799 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943285 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943215 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943605 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943692 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943079 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 942978 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943601 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 50831 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50410 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50407 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50182 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50278 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50867 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51364 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50898 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51185 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51240 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50713 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50631 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51151 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50915 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50185 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50277 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51366 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50795 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51181 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51246 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50711 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50625 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51223 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32499 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533113625500 # Total gap between requests +system.physmem.numWrRetry 32505 # Number of times wr buffer was full causing retry +system.physmem.totGap 2533111047500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154589 # Categorize read packet sizes +system.physmem.readPktSize::6 154560 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59114 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1039924 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981034 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950254 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2676520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2688059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60688 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59177 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108732 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16575 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20010 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 12714 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59094 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1040132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981079 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2676469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2688032 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649605 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60687 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108699 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157561 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16731 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20063 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 12693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see @@ -151,46 +139,46 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32695 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 32647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32522 # What write queue length does an incoming req see -system.physmem.totQLat 393203348000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485594944250 # Sum of mem lat for all requests -system.physmem.totBusLat 75482355000 # Total cycles spent in databus access -system.physmem.totBankLat 16909241250 # Total cycles spent in bank access -system.physmem.avgQLat 26046.04 # Average queueing delay per request -system.physmem.avgBankLat 1120.08 # Average bank access latency per request +system.physmem.wrQLenPdf::27 32623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32524 # What write queue length does an incoming req see +system.physmem.totQLat 393223335500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485617965500 # Sum of mem lat for all requests +system.physmem.totBusLat 75482460000 # Total cycles spent in databus access +system.physmem.totBankLat 16912170000 # Total cycles spent in bank access +system.physmem.avgQLat 26047.33 # Average queueing delay per request +system.physmem.avgBankLat 1120.27 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32166.12 # Average memory access latency +system.physmem.avgMemAccLat 32167.60 # Average memory access latency system.physmem.avgRdBW 381.43 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.10 # Average consumed read bandwidth in MB/s @@ -198,50 +186,62 @@ system.physmem.avgConsumedWrBW 2.68 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.19 # Average read queue length over time -system.physmem.avgWrQLen 12.50 # Average write queue length over time -system.physmem.readRowHits 15020252 # Number of row buffer hits during reads -system.physmem.writeRowHits 793086 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.50 # Row buffer hit rate for reads +system.physmem.avgWrQLen 11.09 # Average write queue length over time +system.physmem.readRowHits 15020204 # Number of row buffer hits during reads +system.physmem.writeRowHits 793057 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes -system.physmem.avgGap 159215.54 # Average gap between requests +system.physmem.avgGap 159215.87 # Average gap between requests +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14667150 # Number of BP lookups -system.cpu.branchPred.condPredicted 11753528 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704564 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9796618 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7939850 # Number of BTB hits +system.cpu.branchPred.lookups 14674954 # Number of BP lookups +system.cpu.branchPred.condPredicted 11760315 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 703452 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9798337 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7946170 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.046847 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1399135 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72592 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.097129 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1399969 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72392 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51396830 # DTB read hits -system.cpu.dtb.read_misses 64077 # DTB read misses -system.cpu.dtb.write_hits 11700143 # DTB write hits -system.cpu.dtb.write_misses 15896 # DTB write misses +system.cpu.dtb.read_hits 51400725 # DTB read hits +system.cpu.dtb.read_misses 64230 # DTB read misses +system.cpu.dtb.write_hits 11699827 # DTB write hits +system.cpu.dtb.write_misses 15817 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3561 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2438 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 402 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3560 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2361 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 419 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1367 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51460907 # DTB read accesses -system.cpu.dtb.write_accesses 11716039 # DTB write accesses +system.cpu.dtb.perms_faults 1347 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51464955 # DTB read accesses +system.cpu.dtb.write_accesses 11715644 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63096973 # DTB hits -system.cpu.dtb.misses 79973 # DTB misses -system.cpu.dtb.accesses 63176946 # DTB accesses -system.cpu.itb.inst_hits 12326910 # ITB inst hits -system.cpu.itb.inst_misses 11389 # ITB inst misses +system.cpu.dtb.hits 63100552 # DTB hits +system.cpu.dtb.misses 80047 # DTB misses +system.cpu.dtb.accesses 63180599 # DTB accesses +system.cpu.itb.inst_hits 12329192 # ITB inst hits +system.cpu.itb.inst_misses 11376 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -250,148 +250,148 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2475 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2472 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2902 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2865 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12338299 # ITB inst accesses -system.cpu.itb.hits 12326910 # DTB hits -system.cpu.itb.misses 11389 # DTB misses -system.cpu.itb.accesses 12338299 # DTB accesses -system.cpu.numCycles 471812928 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12340568 # ITB inst accesses +system.cpu.itb.hits 12329192 # DTB hits +system.cpu.itb.misses 11376 # DTB misses +system.cpu.itb.accesses 12340568 # DTB accesses +system.cpu.numCycles 471811908 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30572325 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 95988347 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14667150 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9338985 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21158726 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5294508 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 123624 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95546847 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2524 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 86189 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195223 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 338 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12323529 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 899693 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5440 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151321070 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.784862 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.149553 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30566850 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 96025902 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14674954 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9346139 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21161280 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5294268 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122956 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95541161 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2622 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 86967 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195337 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 356 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12325832 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 900070 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5461 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151313220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.785216 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.150211 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130177628 86.03% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1303626 0.86% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1711813 1.13% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2496487 1.65% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2227867 1.47% 91.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1109718 0.73% 91.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2758277 1.82% 93.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745468 0.49% 94.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8790186 5.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130167339 86.03% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1302330 0.86% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1712200 1.13% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2496857 1.65% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2222542 1.47% 91.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1109034 0.73% 91.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2758411 1.82% 93.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745566 0.49% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8798941 5.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151321070 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031087 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.203446 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32524080 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95179608 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19189171 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962117 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3466094 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1956870 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171719 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112629435 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 567829 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3466094 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34464944 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36679462 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52534223 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18153241 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6023106 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106095889 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20512 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 985946 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4064605 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 763 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110475366 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485429679 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485339109 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90570 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78390245 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32085120 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830681 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 737048 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12150768 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20327707 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13516010 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1973803 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2472084 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97885695 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983581 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124302750 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167746 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21700961 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 56920385 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501172 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151321070 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.821450 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.535276 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151313220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031103 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.203526 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32523025 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95170118 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19191132 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 962347 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3466598 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1956722 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171732 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112651707 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 566963 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3466598 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34464368 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36692438 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52511672 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18154881 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6023263 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106120156 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20539 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 985607 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4064974 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 783 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110525870 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485527409 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485436293 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91116 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78390038 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32135831 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830318 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736784 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12149928 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20332565 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13516637 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1977838 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2480356 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97929601 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983934 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124328965 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167666 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21748794 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 57017345 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501539 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151313220 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.821666 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.535351 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107116828 70.79% 70.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13508917 8.93% 79.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7078442 4.68% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5929928 3.92% 88.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12595030 8.32% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2803233 1.85% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1696659 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 465338 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 126695 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107094975 70.78% 70.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13518793 8.93% 79.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7075318 4.68% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5935233 3.92% 88.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12598116 8.33% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2801723 1.85% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1697051 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 465636 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 126375 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151321070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151313220 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61883 0.70% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8366537 94.63% 95.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413041 4.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62335 0.71% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8363613 94.62% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413579 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58607180 47.15% 47.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93099 0.07% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58629316 47.16% 47.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93112 0.07% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued @@ -404,10 +404,10 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 18 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 17 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 4 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued @@ -415,353 +415,353 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52915799 42.57% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12320844 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52921084 42.57% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12319626 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124302750 # Type of FU issued -system.cpu.iq.rate 0.263458 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8841465 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071128 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 408992248 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121586509 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85934655 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23175 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12492 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10289 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132768239 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12310 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623420 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124328965 # Type of FU issued +system.cpu.iq.rate 0.263514 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8839530 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071098 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409034606 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121678500 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85964427 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23410 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12602 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10310 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132792371 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12458 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623186 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4673095 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6218 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29888 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1783885 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4678002 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6260 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29908 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1784543 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107776 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 892693 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107773 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 892534 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3466094 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27949012 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 433143 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100090532 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 202747 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20327707 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13516010 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410284 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 112802 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3586 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29888 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350750 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269018 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619768 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121511519 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52083610 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2791231 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3466598 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27942266 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 433430 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100134856 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 201220 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20332565 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13516637 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410804 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113293 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3501 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29908 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350102 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268608 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 618710 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121542985 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52087637 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2785980 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221256 # number of nop insts executed -system.cpu.iew.exec_refs 64295473 # number of memory reference insts executed -system.cpu.iew.exec_branches 11548935 # Number of branches executed -system.cpu.iew.exec_stores 12211863 # Number of stores executed -system.cpu.iew.exec_rate 0.257542 # Inst execution rate -system.cpu.iew.wb_sent 120354811 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85944944 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47248906 # num instructions producing a value -system.cpu.iew.wb_consumers 88214174 # num instructions consuming a value +system.cpu.iew.exec_nop 221321 # number of nop insts executed +system.cpu.iew.exec_refs 64299335 # number of memory reference insts executed +system.cpu.iew.exec_branches 11558025 # Number of branches executed +system.cpu.iew.exec_stores 12211698 # Number of stores executed +system.cpu.iew.exec_rate 0.257609 # Inst execution rate +system.cpu.iew.wb_sent 120384508 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85974737 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47254500 # num instructions producing a value +system.cpu.iew.wb_consumers 88210457 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182159 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535616 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182222 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535702 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21435223 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482409 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535384 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147854976 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.525852 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.516269 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21478461 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482395 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 534359 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147846622 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.525881 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.516310 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120428562 81.45% 81.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13320107 9.01% 90.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3879152 2.62% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2123376 1.44% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1928119 1.30% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 968604 0.66% 96.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1604726 1.09% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 701143 0.47% 98.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2901187 1.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120416670 81.45% 81.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13325889 9.01% 90.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3878179 2.62% 93.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2122601 1.44% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1929203 1.30% 95.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 968068 0.65% 96.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1602055 1.08% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 701521 0.47% 98.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2902436 1.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147854976 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60458293 # Number of instructions committed -system.cpu.commit.committedOps 77749888 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147846622 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60458107 # Number of instructions committed +system.cpu.commit.committedOps 77749667 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386737 # Number of memory references committed -system.cpu.commit.loads 15654612 # Number of loads committed -system.cpu.commit.membars 403603 # Number of memory barriers committed -system.cpu.commit.branches 9961369 # Number of branches committed +system.cpu.commit.refs 27386657 # Number of memory references committed +system.cpu.commit.loads 15654563 # Number of loads committed +system.cpu.commit.membars 403601 # Number of memory barriers committed +system.cpu.commit.branches 9961339 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68855092 # Number of committed integer instructions. -system.cpu.commit.function_calls 991267 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2901187 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68854898 # Number of committed integer instructions. +system.cpu.commit.function_calls 991261 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2902436 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242290263 # The number of ROB reads -system.cpu.rob.rob_writes 201932483 # The number of ROB writes -system.cpu.timesIdled 1770811 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320491858 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4594333550 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307912 # Number of Instructions Simulated -system.cpu.committedOps 77599507 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307912 # Number of Instructions Simulated -system.cpu.cpi 7.823400 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.823400 # CPI: Total CPI of All Threads +system.cpu.rob.rob_reads 242323721 # The number of ROB reads +system.cpu.rob.rob_writes 202019018 # The number of ROB writes +system.cpu.timesIdled 1771597 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320498688 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4594329392 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60307726 # Number of Instructions Simulated +system.cpu.committedOps 77599286 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60307726 # Number of Instructions Simulated +system.cpu.cpi 7.823407 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.823407 # CPI: Total CPI of All Threads system.cpu.ipc 0.127822 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.127822 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550176555 # number of integer regfile reads -system.cpu.int_regfile_writes 88426576 # number of integer regfile writes -system.cpu.fp_regfile_reads 8298 # number of floating regfile reads -system.cpu.fp_regfile_writes 2914 # number of floating regfile writes -system.cpu.misc_regfile_reads 30119271 # number of misc regfile reads -system.cpu.misc_regfile_writes 831902 # number of misc regfile writes -system.cpu.icache.replacements 980182 # number of replacements -system.cpu.icache.tagsinuse 511.616610 # Cycle average of tags in use -system.cpu.icache.total_refs 11263184 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980694 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.484912 # Average number of references to valid blocks. +system.cpu.int_regfile_reads 550308715 # number of integer regfile reads +system.cpu.int_regfile_writes 88462540 # number of integer regfile writes +system.cpu.fp_regfile_reads 8334 # number of floating regfile reads +system.cpu.fp_regfile_writes 2902 # number of floating regfile writes +system.cpu.misc_regfile_reads 30122249 # number of misc regfile reads +system.cpu.misc_regfile_writes 831893 # number of misc regfile writes +system.cpu.icache.replacements 979554 # number of replacements +system.cpu.icache.tagsinuse 511.616693 # Cycle average of tags in use +system.cpu.icache.total_refs 11266265 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980066 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.495415 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6410377000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.616610 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 511.616693 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999251 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999251 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11263184 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11263184 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11263184 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11263184 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11263184 # number of overall hits -system.cpu.icache.overall_hits::total 11263184 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060219 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060219 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060219 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060219 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060219 # number of overall misses -system.cpu.icache.overall_misses::total 1060219 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14018220995 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14018220995 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14018220995 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14018220995 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14018220995 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14018220995 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12323403 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12323403 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12323403 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12323403 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12323403 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12323403 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086033 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.086033 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.086033 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.086033 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.086033 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.086033 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13222.005072 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13222.005072 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13222.005072 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13222.005072 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13222.005072 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13222.005072 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4586 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 11266265 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11266265 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11266265 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11266265 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11266265 # number of overall hits +system.cpu.icache.overall_hits::total 11266265 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1059442 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1059442 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1059442 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1059442 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1059442 # number of overall misses +system.cpu.icache.overall_misses::total 1059442 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13996692496 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13996692496 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13996692496 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13996692496 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13996692496 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13996692496 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12325707 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12325707 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12325707 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12325707 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12325707 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12325707 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085954 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.085954 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.085954 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.085954 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.085954 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.085954 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13211.381554 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13211.381554 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13211.381554 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13211.381554 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13211.381554 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13211.381554 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5064 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 802 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 300 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 15.286667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 17.050505 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 802 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79489 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79489 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79489 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79489 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79489 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79489 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980730 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980730 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980730 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980730 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980730 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980730 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11392389495 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11392389495 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11392389495 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11392389495 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11392389495 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11392389495 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79338 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79338 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79338 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79338 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79338 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79338 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980104 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 980104 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 980104 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 980104 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 980104 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 980104 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11377433497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11377433497 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11377433497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11377433497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11377433497 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11377433497 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7555000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7555000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7555000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7555000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079583 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079583 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079583 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.079583 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079583 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.079583 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11616.234331 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11616.234331 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11616.234331 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11616.234331 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11616.234331 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11616.234331 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079517 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079517 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079517 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.079517 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079517 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.079517 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11608.394106 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11608.394106 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11608.394106 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11608.394106 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11608.394106 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11608.394106 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64360 # number of replacements -system.cpu.l2cache.tagsinuse 51336.859008 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1885213 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129758 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.528684 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2523139048000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36935.695243 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 23.234452 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.003892 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8162.031134 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6215.894286 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563594 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000355 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 64331 # number of replacements +system.cpu.l2cache.tagsinuse 51338.673427 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1885045 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129724 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.531197 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2498168723000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36938.437105 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.056413 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 8154.476716 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6219.702844 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.563636 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000398 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.124543 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.094847 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.783338 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52172 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10475 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 967239 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 386976 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1416862 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607588 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607588 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 42 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112931 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112931 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 52172 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10475 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 967239 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 499907 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1529793 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 52172 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10475 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 967239 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 499907 # number of overall hits -system.cpu.l2cache.overall_hits::total 1529793 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 36 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12355 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10700 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23094 # number of ReadReq misses +system.cpu.l2cache.occ_percent::cpu.inst 0.124427 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.094905 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.783366 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52232 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10453 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 966649 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 387163 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1416497 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607765 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607765 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 40 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 40 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 14 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 14 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 112922 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112922 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 52232 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10453 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 966649 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 500085 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1529419 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 52232 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10453 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 966649 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 500085 # number of overall hits +system.cpu.l2cache.overall_hits::total 1529419 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 40 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12328 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10698 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23068 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2920 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133206 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133206 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 36 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12355 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143906 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156300 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 36 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12355 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143906 # number of overall misses -system.cpu.l2cache.overall_misses::total 156300 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2484000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 186500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 703826000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 629251500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1335748000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 410500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 410500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6753390000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6753390000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2484000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 186500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 703826000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7382641500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8089138000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2484000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 186500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 703826000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7382641500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8089138000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52208 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10478 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 979594 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 397676 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1439956 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607588 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607588 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2962 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2962 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246137 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246137 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52208 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10478 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 979594 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 643813 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1686093 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52208 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10478 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 979594 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 643813 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1686093 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000690 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000286 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012612 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026906 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016038 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985820 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985820 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541186 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541186 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000690 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000286 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012612 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223521 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.092700 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000690 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000286 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012612 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223521 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.092700 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 69000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 62166.666667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56966.895994 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58808.551402 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 57839.612020 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 140.582192 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 140.582192 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50698.842394 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50698.842394 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 69000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 62166.666667 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56966.895994 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51301.832446 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51753.921945 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 69000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 62166.666667 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56966.895994 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51301.832446 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51753.921945 # average overall miss latency +system.cpu.l2cache.ReadExReq_misses::cpu.data 133207 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133207 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 40 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 12328 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143905 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156275 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 40 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 12328 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143905 # number of overall misses +system.cpu.l2cache.overall_misses::total 156275 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2857500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 695307000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 633744500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1332027000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 479000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 479000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6744999000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6744999000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2857500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 695307000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7378743500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8077026000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2857500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 695307000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7378743500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8077026000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52272 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10455 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 978977 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 397861 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1439565 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 607765 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 607765 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2960 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2960 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 17 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 17 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246129 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246129 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52272 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10455 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 978977 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 643990 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1685694 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52272 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10455 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 978977 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 643990 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1685694 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000765 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000191 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012593 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026889 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016024 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986486 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986486 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.176471 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.176471 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541208 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541208 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000765 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000191 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012593 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223458 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.092707 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000765 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000191 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012593 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223458 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.092707 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 71437.500000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56400.632706 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59239.530753 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 57743.497486 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 164.041096 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 164.041096 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50635.469607 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50635.469607 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 71437.500000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56400.632706 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51275.101630 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51684.696849 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 71437.500000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56400.632706 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51275.101630 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51684.696849 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -770,109 +770,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59114 # number of writebacks -system.cpu.l2cache.writebacks::total 59114 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 59094 # number of writebacks +system.cpu.l2cache.writebacks::total 59094 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 36 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12343 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10640 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23022 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 40 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12316 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10637 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 22995 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2920 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133206 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133206 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 36 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12343 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143846 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156228 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 36 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12343 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143846 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156228 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2033785 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 149502 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 549600048 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 494356239 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1046139574 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133207 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133207 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 40 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12316 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143844 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156202 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 40 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12316 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143844 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156202 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2357290 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93251 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 541399772 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 498823739 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1042674052 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29202920 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29202920 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5093264625 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5093264625 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2033785 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 149502 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 549600048 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5587620864 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6139404199 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2033785 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 149502 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 549600048 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5587620864 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6139404199 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5084805426 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5084805426 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2357290 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93251 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 541399772 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5583629165 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6127479478 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2357290 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93251 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 541399772 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5583629165 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6127479478 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5080830 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002364267 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007445097 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26884342911 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26884342911 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002473267 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007554097 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26911803456 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26911803456 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5080830 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193886707178 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193891788008 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000690 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000286 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026755 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015988 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985820 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985820 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541186 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541186 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000690 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000286 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223428 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092657 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000690 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000286 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223428 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092657 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56494.027778 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 49834 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44527.266305 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.052538 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45440.864130 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193914276723 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193919357553 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000765 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026735 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015974 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986486 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986486 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.176471 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.176471 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541208 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541208 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000765 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223364 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092663 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000765 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223364 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092663 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 58932.250000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43959.059110 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46895.152675 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45343.511720 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38236.000068 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38236.000068 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56494.027778 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 49834 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44527.266305 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38844.464664 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39297.719993 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56494.027778 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 49834 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44527.266305 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38844.464664 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39297.719993 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38172.208863 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38172.208863 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 58932.250000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43959.059110 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38817.254560 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39227.919476 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 58932.250000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43959.059110 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38817.254560 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39227.919476 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -882,161 +882,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643301 # number of replacements +system.cpu.dcache.replacements 643478 # number of replacements system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use -system.cpu.dcache.total_refs 21506564 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 643813 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.404986 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 21510687 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643990 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.402207 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 42245000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13753913 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13753913 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259030 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259030 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242896 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242896 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247606 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247606 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21012943 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21012943 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21012943 # number of overall hits -system.cpu.dcache.overall_hits::total 21012943 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737130 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737130 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2963360 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2963360 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13521 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13521 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3700490 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3700490 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3700490 # number of overall misses -system.cpu.dcache.overall_misses::total 3700490 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9747104000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9747104000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104655662232 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104655662232 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180718000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 180718000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 192000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 114402766232 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 114402766232 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 114402766232 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 114402766232 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14491043 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14491043 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222390 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222390 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256417 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256417 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247618 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247618 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24713433 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24713433 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24713433 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24713433 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050868 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050868 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289889 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289889 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052731 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052731 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149736 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149736 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149736 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149736 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13223.046138 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13223.046138 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35316.553585 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35316.553585 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13365.727387 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13365.727387 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30915.572325 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30915.572325 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30915.572325 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30915.572325 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 30983 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 18747 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2620 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 251 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.825573 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 74.689243 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13758124 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13758124 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7259035 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7259035 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242788 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242788 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247600 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247600 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21017159 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21017159 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21017159 # number of overall hits +system.cpu.dcache.overall_hits::total 21017159 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737277 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737277 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963328 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2963328 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13553 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13553 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 17 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 17 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3700605 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3700605 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3700605 # number of overall misses +system.cpu.dcache.overall_misses::total 3700605 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9762499000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9762499000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104581700226 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104581700226 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181087500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 181087500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 257000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 257000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 114344199226 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 114344199226 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 114344199226 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 114344199226 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14495401 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14495401 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222363 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222363 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256341 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256341 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247617 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247617 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24717764 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24717764 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24717764 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24717764 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050863 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050863 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289887 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289887 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052871 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052871 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000069 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000069 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149714 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149714 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149714 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149714 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13241.290587 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13241.290587 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35291.975855 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35291.975855 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13361.432893 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13361.432893 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15117.647059 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15117.647059 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30898.785260 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30898.785260 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30898.785260 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30898.785260 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 30275 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 18688 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2630 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 248 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.511407 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 75.354839 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607588 # number of writebacks -system.cpu.dcache.writebacks::total 607588 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351544 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351544 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714338 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714338 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1354 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1354 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3065882 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3065882 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3065882 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3065882 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385586 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385586 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249022 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249022 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12167 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12167 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634608 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634608 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634608 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634608 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4803296500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4803296500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8203666916 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8203666916 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141299500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141299500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13006963416 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13006963416 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13006963416 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13006963416 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395564500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395564500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36699724336 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36699724336 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219095288836 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 219095288836 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026609 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026609 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024360 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024360 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047450 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047450 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.writebacks::writebacks 607765 # number of writebacks +system.cpu.dcache.writebacks::total 607765 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351549 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351549 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714318 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714318 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1341 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1341 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065867 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065867 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065867 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065867 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385728 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385728 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249010 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249010 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12212 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12212 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634738 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634738 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634738 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634738 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4809640000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4809640000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8195040415 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8195040415 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141777000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141777000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 223000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 223000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13004680415 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13004680415 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13004680415 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13004680415 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395703000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395703000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36727476899 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36727476899 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219123179899 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 219123179899 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026610 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026610 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024359 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024359 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047640 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047640 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000069 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000069 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.025679 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025679 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12457.134076 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12457.134076 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32943.542803 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32943.542803 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11613.339361 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11613.339361 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20496.059640 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20496.059640 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20496.059640 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20496.059640 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12468.993695 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12468.993695 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32910.487189 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32910.487189 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11609.646250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11609.646250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13117.647059 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13117.647059 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20488.265103 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20488.265103 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20488.265103 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20488.265103 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1058,16 +1058,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229535673761 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229535673761 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229535673761 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229535673761 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229570022553 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229570022553 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229570022553 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229570022553 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83046 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83043 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index b7f8b89e3..0638bf4e8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,166 +1,166 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.400708 # Number of seconds simulated -sim_ticks 2400708253000 # Number of ticks simulated -final_tick 2400708253000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.401342 # Number of seconds simulated +sim_ticks 2401342096000 # Number of ticks simulated +final_tick 2401342096000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141448 # Simulator instruction rate (inst/s) -host_op_rate 181662 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5628731106 # Simulator tick rate (ticks/s) -host_mem_usage 441396 # Number of bytes of host memory used -host_seconds 426.51 # Real time elapsed on the host -sim_insts 60328852 # Number of instructions simulated -sim_ops 77480507 # Number of ops (including micro ops) simulated +host_inst_rate 175097 # Simulator instruction rate (inst/s) +host_op_rate 224879 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6969589731 # Simulator tick rate (ticks/s) +host_mem_usage 401152 # Number of bytes of host memory used +host_seconds 344.55 # Real time elapsed on the host +sim_insts 60328983 # Number of instructions simulated +sim_ops 77480984 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 503328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7113744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7112656 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 84352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 676992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 84416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 676928 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 176960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1286200 # Number of bytes read from this memory -system.physmem.bytes_read::total 124661288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 175488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1287544 # Number of bytes read from this memory +system.physmem.bytes_read::total 124660072 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 503328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 84352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 176960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 764640 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3747008 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu1.inst 84416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 175488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 763232 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3746176 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 1490172 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 199452 # Number of bytes written to this memory system.physmem.bytes_written::cpu2.data 1326192 # Number of bytes written to this memory -system.physmem.bytes_written::total 6762824 # Number of bytes written to this memory +system.physmem.bytes_written::total 6761992 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 14067 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 111186 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 111169 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1318 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10578 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1319 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10577 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2765 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20110 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512418 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58547 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2742 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 20131 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512399 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58534 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 372543 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 49863 # Number of write requests responded to by this memory system.physmem.num_writes::cpu2.data 331548 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812501 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47827166 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 812488 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47814542 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 209658 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2963186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 209603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2961950 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 35136 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 281997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 35154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 281896 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.dtb.walker 133 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 73712 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 535759 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51926879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 209658 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 35136 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 73712 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 318506 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1560793 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 620722 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 83080 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 552417 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2817012 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1560793 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47827166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 73079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 536177 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51912667 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 209603 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 35154 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 73079 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1560034 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 620558 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 83059 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 552271 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2815922 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1560034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47814542 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 209658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3583907 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 209603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3582508 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 35136 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 365077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 35154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 364954 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.dtb.walker 133 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 73712 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1088176 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54743891 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12544378 # Total number of read requests seen -system.physmem.writeReqs 398835 # Total number of write requests seen +system.physmem.bw_total::cpu2.inst 73079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1088448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54728589 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12617688 # Total number of read requests seen +system.physmem.writeReqs 398836 # Total number of write requests seen system.physmem.cpureqs 54540 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 802840192 # Total number of bytes read from memory -system.physmem.bytesWritten 25525440 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 102301752 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2640780 # bytesWritten derated as per pkt->getSize() +system.physmem.bytesRead 807532032 # Total number of bytes read from memory +system.physmem.bytesWritten 25525504 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 102888120 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2640844 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 2352 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 784491 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 784138 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 784232 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 784566 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 784404 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 784106 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 784266 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 784324 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 783997 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 783399 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 783436 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 783681 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 783642 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 783494 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 783837 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 784365 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 24962 # Track writes on a per bank basis +system.physmem.neitherReadNorWrite 2353 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 789096 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 788745 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 788844 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 789174 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 789012 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 788711 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 788870 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 788937 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 788603 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 788021 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 788041 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 788285 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 788254 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 788096 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 788287 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 788712 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 24959 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 24829 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 24774 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 24777 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 25058 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 24838 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 24650 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 24877 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 25285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 25156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 24816 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 24782 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 24769 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 24956 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 24888 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 24972 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 25223 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 24837 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 24647 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 24874 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 25287 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 25154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 24830 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 24779 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 24767 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 24961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 24885 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 24973 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 25219 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 14353 # Number of times wr buffer was full causing retry -system.physmem.totGap 2399673084000 # Total gap between requests +system.physmem.totGap 2400306886500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 14 # Categorize read packet sizes -system.physmem.readPktSize::3 12509600 # Categorize read packet sizes +system.physmem.readPktSize::3 12582912 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 34764 # Categorize read packet sizes +system.physmem.readPktSize::6 34762 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 381411 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 17424 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 811080 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 787373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 793054 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2980679 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2247655 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2247973 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2236496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 48996 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 48907 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 90849 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 132798 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 90866 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 6937 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6901 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6892 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17425 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 815618 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 791939 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 797694 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2998185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2260881 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2261175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2249620 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 49272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 49182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 91374 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 133573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 91390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 6962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6950 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 6930 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -177,30 +177,30 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2985 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 2989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3001 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 17347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 17345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 17341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 17348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 17344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 17339 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 17336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 17328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 17325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 17319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 17315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 17327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 17323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 17318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 17314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17304 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 17301 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 17298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 14410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 14409 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 14399 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 14391 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 14365 # What write queue length does an incoming req see @@ -209,27 +209,27 @@ system.physmem.wrQLenPdf::28 14361 # Wh system.physmem.wrQLenPdf::29 14359 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 14357 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 14355 # What write queue length does an incoming req see -system.physmem.totQLat 275491085000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 350869643750 # Sum of mem lat for all requests -system.physmem.totBusLat 62721890000 # Total cycles spent in databus access -system.physmem.totBankLat 12656668750 # Total cycles spent in bank access -system.physmem.avgQLat 21961.32 # Average queueing delay per request -system.physmem.avgBankLat 1008.95 # Average bank access latency per request +system.physmem.totQLat 277103451000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 352917846000 # Sum of mem lat for all requests +system.physmem.totBusLat 63088440000 # Total cycles spent in databus access +system.physmem.totBankLat 12725955000 # Total cycles spent in bank access +system.physmem.avgQLat 21961.51 # Average queueing delay per request +system.physmem.avgBankLat 1008.58 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27970.27 # Average memory access latency -system.physmem.avgRdBW 334.42 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 27970.09 # Average memory access latency +system.physmem.avgRdBW 336.28 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 10.63 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 42.61 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 42.85 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.70 # Data bus utilization in percentage +system.physmem.busUtil 2.71 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time system.physmem.avgWrQLen 0.39 # Average write queue length over time -system.physmem.readRowHits 12490088 # Number of row buffer hits during reads -system.physmem.writeRowHits 392491 # Number of row buffer hits during writes +system.physmem.readRowHits 12563138 # Number of row buffer hits during reads +system.physmem.writeRowHits 392488 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads system.physmem.writeRowHitRate 98.41 # Row buffer hit rate for writes -system.physmem.avgGap 185400.11 # Average gap between requests +system.physmem.avgGap 184404.60 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -242,291 +242,291 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 63256 # number of replacements -system.l2c.tagsinuse 50350.042137 # Cycle average of tags in use -system.l2c.total_refs 1749849 # Total number of references to valid blocks. -system.l2c.sampled_refs 128650 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.601625 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2374435455000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36844.077748 # Average occupied blocks per requestor +system.l2c.replacements 63237 # number of replacements +system.l2c.tagsinuse 50354.010104 # Cycle average of tags in use +system.l2c.total_refs 1750448 # Total number of references to valid blocks. +system.l2c.sampled_refs 128633 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.608079 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2374435270500 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36848.768831 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5153.281590 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3773.823073 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 0.993316 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 798.045066 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 747.763007 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.dtb.walker 4.909443 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.itb.walker 0.003957 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1438.233653 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 1588.911142 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.562196 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.inst 5153.236731 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3773.370268 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 798.048897 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 747.701698 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.dtb.walker 4.908414 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.itb.walker 0.004219 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1438.199404 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 1588.778182 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.562268 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.078633 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.057584 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.078632 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.057577 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.inst 0.012177 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.011410 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.011409 # Average percentage of cache occupancy system.l2c.occ_percent::cpu2.dtb.walker 0.000075 # Average percentage of cache occupancy system.l2c.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.021946 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.024245 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.768281 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 8858 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3206 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 462948 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 169043 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2530 # number of ReadReq hits +system.l2c.occ_percent::cpu2.inst 0.021945 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.024243 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.768341 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 8872 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3222 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 463260 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 169090 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2536 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 1092 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 132569 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 65266 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18106 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4114 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 284351 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 139144 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1291227 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597831 # number of Writeback hits -system.l2c.Writeback_hits::total 597831 # number of Writeback hits +system.l2c.ReadReq_hits::cpu1.inst 132093 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 65269 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 18228 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4214 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 284683 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 139174 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1291733 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597885 # number of Writeback hits +system.l2c.Writeback_hits::total 597885 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 15 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 32 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 60787 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 19416 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 33391 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113594 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8858 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3206 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 462948 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 229830 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 2530 # number of demand (read+write) hits +system.l2c.SCUpgradeReq_hits::cpu2.data 4 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 60858 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 19337 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 33381 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113576 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 8872 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3222 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 463260 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 229948 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 2536 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 1092 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 132569 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 84682 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 18106 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 4114 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 284351 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 172535 # number of demand (read+write) hits -system.l2c.demand_hits::total 1404821 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 8858 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3206 # number of overall hits -system.l2c.overall_hits::cpu0.inst 462948 # number of overall hits -system.l2c.overall_hits::cpu0.data 229830 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 2530 # number of overall hits +system.l2c.demand_hits::cpu1.inst 132093 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 84606 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 18228 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 4214 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 284683 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 172555 # number of demand (read+write) hits +system.l2c.demand_hits::total 1405309 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 8872 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3222 # number of overall hits +system.l2c.overall_hits::cpu0.inst 463260 # number of overall hits +system.l2c.overall_hits::cpu0.data 229948 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 2536 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 1092 # number of overall hits -system.l2c.overall_hits::cpu1.inst 132569 # number of overall hits -system.l2c.overall_hits::cpu1.data 84682 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 18106 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 4114 # number of overall hits -system.l2c.overall_hits::cpu2.inst 284351 # number of overall hits -system.l2c.overall_hits::cpu2.data 172535 # number of overall hits -system.l2c.overall_hits::total 1404821 # number of overall hits +system.l2c.overall_hits::cpu1.inst 132093 # number of overall hits +system.l2c.overall_hits::cpu1.data 84606 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 18228 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 4214 # number of overall hits +system.l2c.overall_hits::cpu2.inst 284683 # number of overall hits +system.l2c.overall_hits::cpu2.data 172555 # number of overall hits +system.l2c.overall_hits::total 1405309 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.inst 7451 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6381 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6380 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1318 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1194 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1319 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1192 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.dtb.walker 5 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 2765 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 2549 # number of ReadReq misses -system.l2c.ReadReq_misses::total 21668 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1421 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu2.inst 2742 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 2555 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21649 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1422 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 507 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 980 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2908 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 976 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2905 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu2.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 105561 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 9656 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 18147 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133364 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 105543 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 9659 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 18165 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133367 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.inst 7451 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 111942 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 111923 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1318 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10850 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1319 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10851 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.dtb.walker 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 2765 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 20696 # number of demand (read+write) misses -system.l2c.demand_misses::total 155032 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 2742 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 20720 # number of demand (read+write) misses +system.l2c.demand_misses::total 155016 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses system.l2c.overall_misses::cpu0.inst 7451 # number of overall misses -system.l2c.overall_misses::cpu0.data 111942 # number of overall misses +system.l2c.overall_misses::cpu0.data 111923 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1318 # number of overall misses -system.l2c.overall_misses::cpu1.data 10850 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1319 # number of overall misses +system.l2c.overall_misses::cpu1.data 10851 # number of overall misses system.l2c.overall_misses::cpu2.dtb.walker 5 # number of overall misses system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu2.inst 2765 # number of overall misses -system.l2c.overall_misses::cpu2.data 20696 # number of overall misses -system.l2c.overall_misses::total 155032 # number of overall misses +system.l2c.overall_misses::cpu2.inst 2742 # number of overall misses +system.l2c.overall_misses::cpu2.data 20720 # number of overall misses +system.l2c.overall_misses::total 155016 # number of overall misses system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 69000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 73618000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 68964500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 73672500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 68200500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 344500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.itb.walker 69000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 180915000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 155129499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 479109499 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 115000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 90000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 205000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 433667500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 956422000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1390089500 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 180939000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 155784998 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 479079498 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 114500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 137000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 251500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 433368500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 962108000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1395476500 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 69000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 73618000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 502632000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 73672500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 501569000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2.dtb.walker 344500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2.itb.walker 69000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 180915000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1111551499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 1869198999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 180939000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1117892998 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 1874555998 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 69000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 73618000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 502632000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 73672500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 501569000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.dtb.walker 344500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.itb.walker 69000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 180915000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1111551499 # number of overall miss cycles -system.l2c.overall_miss_latency::total 1869198999 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 8859 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3208 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 470399 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 175424 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 2531 # number of ReadReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu2.inst 180939000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1117892998 # number of overall miss cycles +system.l2c.overall_miss_latency::total 1874555998 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 8873 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3224 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 470711 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 175470 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 2537 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 1092 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 133887 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 66460 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 18111 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 4115 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 287116 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 141693 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1312895 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 597831 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 597831 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1434 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 133412 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 66461 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 18233 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 4215 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 287425 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 141729 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1313382 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 597885 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 597885 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1435 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 511 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 995 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2940 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu2.data 4 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 166348 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 29072 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 51538 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246958 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8859 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3208 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 470399 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 341772 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 2531 # number of demand (read+write) accesses +system.l2c.UpgradeReq_accesses::cpu2.data 991 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2937 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu2.data 5 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 166401 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 28996 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 51546 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246943 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8873 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3224 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 470711 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 341871 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 2537 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 1092 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 133887 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 95532 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 18111 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 4115 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 287116 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 193231 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1559853 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8859 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3208 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 470399 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 341772 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 2531 # number of overall (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 133412 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 95457 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 18233 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 4215 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 287425 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 193275 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1560325 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8873 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3224 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 470711 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 341871 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 2537 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 1092 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 133887 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 95532 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 18111 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 4115 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 287116 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 193231 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1559853 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 133412 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 95457 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 18233 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 4215 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 287425 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 193275 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1560325 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000113 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000623 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015840 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036375 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000395 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009844 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.017966 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000276 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000243 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.009630 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.017990 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016504 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990934 # miss rate for UpgradeReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000620 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015829 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036359 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000394 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009887 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.017935 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000274 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000237 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.009540 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.018027 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016483 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990941 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992172 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.984925 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.989116 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.250000 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.634579 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.332141 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.352109 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.540027 # miss rate for ReadExReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.984864 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.989105 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.200000 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.200000 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.634269 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.333115 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.352404 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.540072 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000113 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000623 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015840 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.327534 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000395 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009844 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.113575 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000276 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.itb.walker 0.000243 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.009630 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.107105 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.099389 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000620 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015829 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.327384 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000394 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009887 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.113674 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000274 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.itb.walker 0.000237 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.009540 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.107205 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.099349 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000113 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000623 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015840 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.327534 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000395 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009844 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.113575 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000276 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.itb.walker 0.000243 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.009630 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.107105 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.099389 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000620 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015829 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.327384 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000394 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009887 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.113674 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000274 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.itb.walker 0.000237 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.009540 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.107205 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.099349 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 69000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 55855.842185 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 57759.212730 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 55854.814253 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 57215.184564 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 68900 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 69000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 65430.379747 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 60858.963907 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 22111.385407 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 226.824458 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 91.836735 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 70.495186 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 44911.712925 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52704.138425 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 10423.273897 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 65987.964989 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 60972.601957 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 22129.405423 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 225.838264 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 140.368852 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 86.574871 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 44866.808158 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52964.932563 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 10463.431733 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 55855.842185 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 46325.529954 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 55854.814253 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 46223.297392 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 68900 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2.itb.walker 69000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 65430.379747 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 53708.518506 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 12056.859223 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 65987.964989 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 53952.364768 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 12092.661390 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 55855.842185 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 46325.529954 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 55854.814253 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 46223.297392 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 68900 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.itb.walker 69000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 65430.379747 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 53708.518506 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 12056.859223 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 65987.964989 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 53952.364768 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 12092.661390 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -535,8 +535,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 58547 # number of writebacks -system.l2c.writebacks::total 58547 # number of writebacks +system.l2c.writebacks::writebacks 58534 # number of writebacks +system.l2c.writebacks::total 58534 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu2.data 8 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu2.data 8 # number of demand (read+write) MSHR hits @@ -544,142 +544,142 @@ system.l2c.demand_mshr_hits::total 8 # nu system.l2c.overall_mshr_hits::cpu2.data 8 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 8 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1318 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1194 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1319 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1192 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 5 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 2765 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 2541 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 7825 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 2742 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 2547 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 7807 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu1.data 507 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 980 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 1487 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 976 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 1483 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 1 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 9656 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 18147 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 27803 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 9659 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 18165 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 27824 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1318 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 10850 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1319 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 10851 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.dtb.walker 5 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 2765 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 20688 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 35628 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 2742 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 20712 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 35631 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1318 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 10850 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1319 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 10851 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.dtb.walker 5 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 2765 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 20688 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 35628 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 2742 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 20712 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 35631 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 56251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 57085318 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 54060944 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 57127819 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 53323692 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 281255 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 56251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 146465179 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 123133891 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 381139089 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5113480 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 9800980 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 14914460 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 146773160 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 123717895 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 381336323 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5104986 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 9760976 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 14865962 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 10001 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 313418646 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 730113588 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1043532234 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 313086148 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 735597828 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1048683976 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 57085318 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 367479590 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 57127819 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 366409840 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 281255 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 56251 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 146465179 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 853247479 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1424671323 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 146773160 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 859315723 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1430020299 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 56251 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 57085318 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 367479590 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 57127819 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 366409840 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 281255 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 56251 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 146465179 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 853247479 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1424671323 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25256982500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26555773011 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 51812755511 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 643112863 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9826950545 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 10470063408 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25900095363 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 36382723556 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 62282818919 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000395 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009844 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017966 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000276 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000243 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009630 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.017933 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.005960 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_miss_latency::cpu2.inst 146773160 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 859315723 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1430020299 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25256698500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26538798011 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 51795496511 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 642972863 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9826952545 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 10469925408 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25899671363 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 36365750556 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 62265421919 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009887 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017935 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000274 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000237 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009540 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.017971 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.005944 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992172 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.984925 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.505782 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.332141 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.352109 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.112582 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000395 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009844 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.113575 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000276 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000243 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009630 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.107064 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.022841 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000395 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009844 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.113575 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000276 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000243 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009630 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.107064 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.022841 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.984864 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.504937 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.333115 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.352404 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.112674 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009887 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.113674 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000274 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000237 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009540 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.107163 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.022836 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009887 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.113674 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000274 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000237 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009540 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.107163 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.022836 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43312.077390 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45277.172529 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43311.462472 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 44734.640940 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 56251 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 52971.131646 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 48458.831562 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 48707.870799 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10085.759369 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 53527.775346 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 48573.967413 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 48845.436531 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10069.005917 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10029.899126 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10024.249494 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32458.434756 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40233.294098 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 37533.080387 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32413.929806 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40495.338728 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 37689.907131 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43312.077390 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33869.086636 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43311.462472 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33767.379965 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 56251 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 52971.131646 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41243.594306 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39987.406618 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 53527.775346 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41488.785390 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40134.161236 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43312.077390 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33869.086636 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43311.462472 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33767.379965 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 56251 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 52971.131646 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41243.594306 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39987.406618 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 53527.775346 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41488.785390 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40134.161236 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -698,436 +698,436 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8066044 # DTB read hits -system.cpu0.dtb.read_misses 6218 # DTB read misses -system.cpu0.dtb.write_hits 6637384 # DTB write hits -system.cpu0.dtb.write_misses 2035 # DTB write misses +system.cpu0.dtb.read_hits 8063471 # DTB read hits +system.cpu0.dtb.read_misses 6217 # DTB read misses +system.cpu0.dtb.write_hits 6637313 # DTB write hits +system.cpu0.dtb.write_misses 2039 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 692 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 691 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5688 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5696 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 121 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 115 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8072262 # DTB read accesses -system.cpu0.dtb.write_accesses 6639419 # DTB write accesses +system.cpu0.dtb.perms_faults 213 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8069688 # DTB read accesses +system.cpu0.dtb.write_accesses 6639352 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14703428 # DTB hits -system.cpu0.dtb.misses 8253 # DTB misses -system.cpu0.dtb.accesses 14711681 # DTB accesses -system.cpu0.itb.inst_hits 32696148 # ITB inst hits -system.cpu0.itb.inst_misses 3481 # ITB inst misses +system.cpu0.dtb.hits 14700784 # DTB hits +system.cpu0.dtb.misses 8256 # DTB misses +system.cpu0.dtb.accesses 14709040 # DTB accesses +system.cpu0.itb.inst_hits 32681637 # ITB inst hits +system.cpu0.itb.inst_misses 3491 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 692 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 691 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2588 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2596 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32699629 # ITB inst accesses -system.cpu0.itb.hits 32696148 # DTB hits -system.cpu0.itb.misses 3481 # DTB misses -system.cpu0.itb.accesses 32699629 # DTB accesses -system.cpu0.numCycles 114001235 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32685128 # ITB inst accesses +system.cpu0.itb.hits 32681637 # DTB hits +system.cpu0.itb.misses 3491 # DTB misses +system.cpu0.itb.accesses 32685128 # DTB accesses +system.cpu0.numCycles 114010154 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 32202356 # Number of instructions committed -system.cpu0.committedOps 42405748 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37555932 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5136 # Number of float alu accesses -system.cpu0.num_func_calls 1189098 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4237826 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37555932 # number of integer instructions -system.cpu0.num_fp_insts 5136 # number of float instructions -system.cpu0.num_int_register_reads 191328019 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39633304 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3646 # number of times the floating registers were read +system.cpu0.committedInsts 32191031 # Number of instructions committed +system.cpu0.committedOps 42397842 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37550478 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5152 # Number of float alu accesses +system.cpu0.num_func_calls 1189151 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4236395 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37550478 # number of integer instructions +system.cpu0.num_fp_insts 5152 # number of float instructions +system.cpu0.num_int_register_reads 191293724 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39622664 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3662 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1492 # number of times the floating registers were written -system.cpu0.num_mem_refs 15368046 # number of memory refs -system.cpu0.num_load_insts 8434010 # Number of load instructions -system.cpu0.num_store_insts 6934036 # Number of store instructions -system.cpu0.num_idle_cycles 13414288023.648659 # Number of idle cycles -system.cpu0.num_busy_cycles -13300286788.648659 # Number of busy cycles -system.cpu0.not_idle_fraction -116.667918 # Percentage of non-idle cycles -system.cpu0.idle_fraction 117.667918 # Percentage of idle cycles +system.cpu0.num_mem_refs 15365306 # number of memory refs +system.cpu0.num_load_insts 8431456 # Number of load instructions +system.cpu0.num_store_insts 6933850 # Number of store instructions +system.cpu0.num_idle_cycles 13419590967.275719 # Number of idle cycles +system.cpu0.num_busy_cycles -13305580813.275719 # Number of busy cycles +system.cpu0.not_idle_fraction -116.705226 # Percentage of non-idle cycles +system.cpu0.idle_fraction 117.705226 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82893 # number of quiesce instructions executed -system.cpu0.icache.replacements 892329 # number of replacements -system.cpu0.icache.tagsinuse 511.602586 # Cycle average of tags in use -system.cpu0.icache.total_refs 44224471 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 892841 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 49.532303 # Average number of references to valid blocks. +system.cpu0.icache.replacements 892475 # number of replacements +system.cpu0.icache.tagsinuse 511.602627 # Cycle average of tags in use +system.cpu0.icache.total_refs 44228984 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 892987 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 49.529259 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 8120621000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 478.364653 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 17.665639 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 15.572294 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.934306 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.034503 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.030415 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 478.244790 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 17.725575 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu2.inst 15.632262 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.934072 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.034620 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu2.inst 0.030532 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.999224 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 32227698 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8245303 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3751470 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 44224471 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32227698 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8245303 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3751470 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 44224471 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32227698 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8245303 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3751470 # number of overall hits -system.cpu0.icache.overall_hits::total 44224471 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 471122 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 134159 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 311537 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 916818 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 471122 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 134159 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 311537 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 916818 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 471122 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 134159 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 311537 # number of overall misses -system.cpu0.icache.overall_misses::total 916818 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1808055500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4158384493 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5966439993 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1808055500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4158384493 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5966439993 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1808055500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4158384493 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5966439993 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32698820 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 8379462 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 4063007 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 45141289 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32698820 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 8379462 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 4063007 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 45141289 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32698820 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 8379462 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 4063007 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 45141289 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014408 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016010 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076676 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.020310 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014408 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016010 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076676 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.020310 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014408 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016010 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076676 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.020310 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13476.960174 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13347.963462 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6507.769255 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13476.960174 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13347.963462 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6507.769255 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13476.960174 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13347.963462 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6507.769255 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5517 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 32212887 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 8260747 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3755350 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 44228984 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 32212887 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 8260747 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3755350 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 44228984 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 32212887 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 8260747 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3755350 # number of overall hits +system.cpu0.icache.overall_hits::total 44228984 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 471430 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 133687 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 311925 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 917042 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 471430 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 133687 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 311925 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 917042 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 471430 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 133687 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 311925 # number of overall misses +system.cpu0.icache.overall_misses::total 917042 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1801927500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4162865992 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5964793492 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1801927500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4162865992 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5964793492 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1801927500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4162865992 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5964793492 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32684317 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 8394434 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 4067275 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 45146026 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 32684317 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 8394434 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 4067275 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 45146026 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32684317 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 8394434 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 4067275 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 45146026 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014424 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015926 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076691 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.020313 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014424 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015926 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076691 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.020313 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014424 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015926 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076691 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.020313 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13478.703988 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13345.727313 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6504.384196 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13478.703988 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13345.727313 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6504.384196 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13478.703988 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13345.727313 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6504.384196 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5091 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 195 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 198 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 28.292308 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.712121 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23964 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 23964 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 23964 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 23964 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 23964 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 23964 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 134159 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 287573 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 421732 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 134159 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 287573 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 421732 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 134159 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 287573 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 421732 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1539737500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3392264993 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4932002493 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1539737500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3392264993 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4932002493 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1539737500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3392264993 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4932002493 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016010 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070778 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009342 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016010 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070778 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009342 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016010 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070778 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009342 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11476.960174 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11796.187379 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11694.636625 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11476.960174 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11796.187379 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11694.636625 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11476.960174 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11796.187379 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11694.636625 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24041 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 24041 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 24041 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 24041 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 24041 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 24041 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 133687 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 287884 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 421571 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 133687 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 287884 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 421571 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 133687 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 287884 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 421571 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1534553500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3395985992 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4930539492 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1534553500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3395985992 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4930539492 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1534553500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3395985992 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4930539492 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015926 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070781 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009338 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015926 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070781 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009338 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015926 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070781 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009338 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11478.703988 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11796.369343 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11695.632508 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11478.703988 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11796.369343 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11695.632508 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11478.703988 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11796.369343 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11695.632508 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 630023 # number of replacements -system.cpu0.dcache.tagsinuse 511.997115 # Cycle average of tags in use -system.cpu0.dcache.total_refs 23223254 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 630535 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 36.831031 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 630091 # number of replacements +system.cpu0.dcache.tagsinuse 511.997116 # Cycle average of tags in use +system.cpu0.dcache.total_refs 23225610 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 630603 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 36.830795 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 495.880002 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 9.605532 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu2.data 6.511582 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.968516 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.018761 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu2.data 0.012718 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 495.760102 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 9.700202 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu2.data 6.536812 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.968281 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.018946 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu2.data 0.012767 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6947766 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1882163 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4477345 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13307274 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5958886 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1342354 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2125973 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9427213 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131324 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 34069 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 72982 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 238375 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137698 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 35791 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73904 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247393 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12906652 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 3224517 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6603318 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 22734487 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12906652 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 3224517 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6603318 # number of overall hits -system.cpu0.dcache.overall_hits::total 22734487 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 169050 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 64738 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 285084 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 518872 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 167782 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 29583 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 591784 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 789149 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6374 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1722 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3871 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11967 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 4 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 336832 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 94321 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 876868 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1308021 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 336832 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 94321 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 876868 # number of overall misses -system.cpu0.dcache.overall_misses::total 1308021 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 902894500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4121906000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5024800500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 728179000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 17993273399 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 18721452399 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22543500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 52244000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 74787500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 64000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 64000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 1631073500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 22115179399 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 23746252899 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 1631073500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 22115179399 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 23746252899 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7116816 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1946901 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4762429 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13826146 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6126668 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1371937 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2717757 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits::cpu0.data 6944978 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1884503 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4480327 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13309808 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5958718 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1341197 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2127096 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9427011 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131371 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 33990 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73049 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 238410 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137743 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 35715 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73934 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247392 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12903696 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 3225700 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6607423 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 22736819 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12903696 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 3225700 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6607423 # number of overall hits +system.cpu0.dcache.overall_hits::total 22736819 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 169098 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 64736 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 284633 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 518467 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 167836 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 29507 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 592008 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 789351 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6372 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1725 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3872 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11969 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 5 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 336934 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 94243 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 876641 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1307818 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 336934 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 94243 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 876641 # number of overall misses +system.cpu0.dcache.overall_misses::total 1307818 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 902119000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4115909000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5018028000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 726856500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18065670403 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 18792526903 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22582000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 52183000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 74765000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 77000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 77000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 1628975500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 22181579403 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 23810554903 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 1628975500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 22181579403 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 23810554903 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7114076 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1949239 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4764960 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13828275 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6126554 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1370704 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2719104 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 10216362 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137698 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35791 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 76853 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250342 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137698 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35791 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 73908 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137743 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35715 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 76921 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 250379 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137743 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35715 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 73939 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247397 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13243484 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3318838 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7480186 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24042508 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13243484 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3318838 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7480186 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24042508 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023754 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033252 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.059861 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037528 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027386 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021563 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.217747 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.077244 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046290 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.048113 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050369 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047803 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000054 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000016 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025434 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028420 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.117225 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.054405 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025434 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028420 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.117225 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.054405 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13946.901356 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14458.566598 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9684.084900 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 24614.778758 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30405.136670 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 23723.596430 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13091.463415 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13496.254198 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6249.477730 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17292.792697 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25220.648261 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 18154.336130 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17292.792697 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25220.648261 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18154.336130 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8894 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 919 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1121 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 44 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.933988 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 20.886364 # average number of cycles each access was blocked +system.cpu0.dcache.demand_accesses::cpu0.data 13240630 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 3319943 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7484064 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24044637 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13240630 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 3319943 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7484064 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24044637 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023769 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033211 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.059735 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037493 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027395 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021527 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.217722 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.077263 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046260 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.048299 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050337 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047804 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000068 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000020 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025447 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028387 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.117134 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.054391 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025447 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028387 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.117134 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.054391 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13935.352818 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14460.406910 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9678.587065 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 24633.358186 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30515.922763 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 23807.567106 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13091.014493 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13477.014463 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6246.553597 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 15400 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15400 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17284.843437 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25302.922637 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 18206.321448 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17284.843437 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25302.922637 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18206.321448 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8914 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 958 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1123 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 47 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.937667 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 20.382979 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597831 # number of writebacks -system.cpu0.dcache.writebacks::total 597831 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 146824 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 146824 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 539280 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 539280 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 409 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 409 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 686104 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 686104 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 686104 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 686104 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 64738 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 138260 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 202998 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29583 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52504 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 82087 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1722 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3462 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5184 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 4 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 94321 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 190764 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 285085 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 94321 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 190764 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 285085 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 773418500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1795552000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2568970500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 669013000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1403739991 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2072752991 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19099500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40608500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59708000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 56000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 56000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1442431500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3199291991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 4641723491 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1442431500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3199291991 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 4641723491 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27592956500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28992541000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56585497500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1276098000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14147117763 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15423215763 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28869054500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43139658763 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 72008713263 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033252 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.029031 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014682 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021563 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019319 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008035 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048113 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.045047 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020708 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000016 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028420 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025503 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011858 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028420 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025503 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011858 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11946.901356 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12986.778533 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12655.151775 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22614.778758 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26735.867572 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25250.685139 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11091.463415 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11729.780474 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11517.746914 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15292.792697 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16770.942059 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16281.893088 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15292.792697 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16770.942059 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16281.893088 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597885 # number of writebacks +system.cpu0.dcache.writebacks::total 597885 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 146334 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 146334 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 539505 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 539505 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 408 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 408 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 685839 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 685839 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 685839 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 685839 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 64736 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 138299 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 203035 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29507 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52503 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 82010 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1725 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3464 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5189 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 5 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 94243 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 190802 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 285045 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 94243 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 190802 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 285045 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 772647000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1796404500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2569051500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 667842500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1409486493 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2077328993 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19132000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40548500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59680500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 67000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 67000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1440489500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3205890993 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 4646380493 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1440489500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3205890993 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4646380493 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27592646000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28973998000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56566644000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1275946000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14147122763 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15423068763 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28868592000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43121120763 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71989712763 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033211 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.029024 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014683 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021527 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019309 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008027 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048299 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.045033 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020725 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000068 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000020 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028387 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025494 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011855 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028387 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025494 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011855 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11935.352818 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12989.280472 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12653.244514 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22633.358186 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26845.827724 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25330.191355 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11091.014493 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11705.687067 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11501.349008 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 13400 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15284.843437 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16802.187571 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16300.515683 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15284.843437 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16802.187571 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16300.515683 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1140,26 +1140,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2162379 # DTB read hits -system.cpu1.dtb.read_misses 2097 # DTB read misses -system.cpu1.dtb.write_hits 1458481 # DTB write hits -system.cpu1.dtb.write_misses 389 # DTB write misses +system.cpu1.dtb.read_hits 2164639 # DTB read hits +system.cpu1.dtb.read_misses 2112 # DTB read misses +system.cpu1.dtb.write_hits 1457171 # DTB write hits +system.cpu1.dtb.write_misses 388 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 242 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 237 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1709 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1711 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 41 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2164476 # DTB read accesses -system.cpu1.dtb.write_accesses 1458870 # DTB write accesses +system.cpu1.dtb.read_accesses 2166751 # DTB read accesses +system.cpu1.dtb.write_accesses 1457559 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3620860 # DTB hits -system.cpu1.dtb.misses 2486 # DTB misses -system.cpu1.dtb.accesses 3623346 # DTB accesses -system.cpu1.itb.inst_hits 8379462 # ITB inst hits +system.cpu1.dtb.hits 3621810 # DTB hits +system.cpu1.dtb.misses 2500 # DTB misses +system.cpu1.dtb.accesses 3624310 # DTB accesses +system.cpu1.itb.inst_hits 8394434 # ITB inst hits system.cpu1.itb.inst_misses 1132 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1167,7 +1167,7 @@ system.cpu1.itb.write_hits 0 # DT system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 242 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 237 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID system.cpu1.itb.flush_entries 830 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions @@ -1176,216 +1176,216 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8380594 # ITB inst accesses -system.cpu1.itb.hits 8379462 # DTB hits +system.cpu1.itb.inst_accesses 8395566 # ITB inst accesses +system.cpu1.itb.hits 8394434 # DTB hits system.cpu1.itb.misses 1132 # DTB misses -system.cpu1.itb.accesses 8380594 # DTB accesses -system.cpu1.numCycles 573333879 # number of cpu cycles simulated +system.cpu1.itb.accesses 8395566 # DTB accesses +system.cpu1.numCycles 574616929 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 8178203 # Number of instructions committed -system.cpu1.committedOps 10418210 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9330752 # Number of integer alu accesses +system.cpu1.committedInsts 8189721 # Number of instructions committed +system.cpu1.committedOps 10425154 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9334484 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1998 # Number of float alu accesses -system.cpu1.num_func_calls 315480 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1141385 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9330752 # number of integer instructions +system.cpu1.num_func_calls 315358 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1143455 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9334484 # number of integer instructions system.cpu1.num_fp_insts 1998 # number of float instructions -system.cpu1.num_int_register_reads 53785556 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10103056 # number of times the integer registers were written +system.cpu1.num_int_register_reads 53815468 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10115295 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1549 # number of times the floating registers were read system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written -system.cpu1.num_mem_refs 3793769 # number of memory refs -system.cpu1.num_load_insts 2257716 # Number of load instructions -system.cpu1.num_store_insts 1536053 # Number of store instructions -system.cpu1.num_idle_cycles 537669981.200710 # Number of idle cycles -system.cpu1.num_busy_cycles 35663897.799290 # Number of busy cycles -system.cpu1.not_idle_fraction 0.062204 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.937796 # Percentage of idle cycles +system.cpu1.num_mem_refs 3794179 # number of memory refs +system.cpu1.num_load_insts 2259735 # Number of load instructions +system.cpu1.num_store_insts 1534444 # Number of store instructions +system.cpu1.num_idle_cycles 532869113.789336 # Number of idle cycles +system.cpu1.num_busy_cycles 41747815.210664 # Number of busy cycles +system.cpu1.not_idle_fraction 0.072653 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.927347 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4726334 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3843092 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 222010 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 2958856 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2529751 # Number of BTB hits +system.cpu2.branchPred.lookups 4726542 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3843019 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 222839 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 2968663 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2529901 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 85.497604 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 412073 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21648 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 85.220215 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 412372 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21902 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10884010 # DTB read hits -system.cpu2.dtb.read_misses 22849 # DTB read misses -system.cpu2.dtb.write_hits 3265307 # DTB write hits -system.cpu2.dtb.write_misses 5901 # DTB write misses +system.cpu2.dtb.read_hits 10882413 # DTB read hits +system.cpu2.dtb.read_misses 22825 # DTB read misses +system.cpu2.dtb.write_hits 3267303 # DTB write hits +system.cpu2.dtb.write_misses 5867 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 505 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 511 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2317 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 675 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 176 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2312 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 661 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 167 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 462 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10906859 # DTB read accesses -system.cpu2.dtb.write_accesses 3271208 # DTB write accesses +system.cpu2.dtb.perms_faults 479 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10905238 # DTB read accesses +system.cpu2.dtb.write_accesses 3273170 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14149317 # DTB hits -system.cpu2.dtb.misses 28750 # DTB misses -system.cpu2.dtb.accesses 14178067 # DTB accesses -system.cpu2.itb.inst_hits 4064296 # ITB inst hits -system.cpu2.itb.inst_misses 4509 # ITB inst misses +system.cpu2.dtb.hits 14149716 # DTB hits +system.cpu2.dtb.misses 28692 # DTB misses +system.cpu2.dtb.accesses 14178408 # DTB accesses +system.cpu2.itb.inst_hits 4068625 # ITB inst hits +system.cpu2.itb.inst_misses 4512 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 505 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 511 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1562 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1570 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 968 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1019 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4068805 # ITB inst accesses -system.cpu2.itb.hits 4064296 # DTB hits -system.cpu2.itb.misses 4509 # DTB misses -system.cpu2.itb.accesses 4068805 # DTB accesses -system.cpu2.numCycles 88279018 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4073137 # ITB inst accesses +system.cpu2.itb.hits 4068625 # DTB hits +system.cpu2.itb.misses 4512 # DTB misses +system.cpu2.itb.accesses 4073137 # DTB accesses +system.cpu2.numCycles 88262186 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9458864 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32433194 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4726334 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2941824 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6832879 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1816174 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 51286 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 19337351 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 2080 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 975 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 33815 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 56915 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 312 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4063011 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 310021 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1911 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 37021672 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.050656 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.436806 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9466966 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32442756 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4726542 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2942273 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6836207 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1818602 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 52204 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 19340391 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 1503 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 949 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 33911 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 57026 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 350 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4067278 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 310494 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1937 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37038296 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.050561 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.436650 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30193705 81.56% 81.56% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 383800 1.04% 82.59% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 509282 1.38% 83.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 813035 2.20% 86.17% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 655040 1.77% 87.93% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 344627 0.93% 88.87% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1013096 2.74% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 238978 0.65% 92.25% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2870109 7.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30207118 81.56% 81.56% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 383553 1.04% 82.59% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 510773 1.38% 83.97% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 813677 2.20% 86.17% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 655447 1.77% 87.94% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 344842 0.93% 88.87% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1012614 2.73% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 239002 0.65% 92.25% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2871270 7.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 37021672 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053539 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.367394 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10074280 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19273281 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6183203 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 295071 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1194753 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 612486 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53708 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36748038 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 181597 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1194753 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10649029 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6564844 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11163009 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5883991 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1564995 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34501786 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2424 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 422794 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 878812 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 93 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37014698 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 157694934 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 157667196 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 27738 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 25798325 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11216372 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 231057 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 207527 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3357295 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6536002 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3838530 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 533894 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 787090 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 31736542 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 511835 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34275347 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 54662 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7411950 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19918044 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 155690 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 37021672 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.925818 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.580792 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37038296 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053551 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.367573 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10082561 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19277386 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6185445 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 295546 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1196299 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 612714 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53722 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36760071 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 181639 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1196299 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10657194 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6561283 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11169878 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5886650 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1565975 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34511546 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2439 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 423021 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 879548 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 92 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37019837 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 157748297 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 157720764 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 27533 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 25797181 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11222655 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 231296 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 207724 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3360285 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6539665 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3841357 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 538392 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 797336 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 31744288 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 511908 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34279119 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 54882 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7417436 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19927896 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 155705 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37038296 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.925505 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.580259 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24452597 66.05% 66.05% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3909614 10.56% 76.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2349010 6.34% 82.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1972018 5.33% 88.28% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2798812 7.56% 95.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 886009 2.39% 98.23% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 484017 1.31% 99.54% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 134496 0.36% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 35099 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24460082 66.04% 66.04% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3918248 10.58% 76.62% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2351220 6.35% 82.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1973788 5.33% 88.30% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2795799 7.55% 95.84% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 886051 2.39% 98.24% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 483364 1.31% 99.54% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 134520 0.36% 99.90% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 35224 0.10% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 37021672 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37038296 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 18701 1.22% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1408658 91.63% 92.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 109949 7.15% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 18440 1.20% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1407717 91.67% 92.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 109411 7.13% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61376 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19371931 56.52% 56.70% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61375 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19374131 56.52% 56.70% # Type of FU issued system.cpu2.iq.FU_type_0::IntMult 25889 0.08% 56.77% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.77% # Type of FU issued system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.77% # Type of FU issued @@ -1399,129 +1399,129 @@ system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.77% # Ty system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.77% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.77% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 5 0.00% 56.77% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.77% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 5 0.00% 56.77% # Type of FU issued system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.77% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.77% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.77% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.77% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.77% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 382 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 381 0.00% 56.77% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 56.77% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11383572 33.21% 89.99% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3432179 10.01% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11382838 33.21% 89.98% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3434489 10.02% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34275347 # Type of FU issued -system.cpu2.iq.rate 0.388262 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1537308 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044852 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 107186070 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39665615 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 27402348 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 6887 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3783 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3156 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 35747644 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3635 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 208180 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34279119 # Type of FU issued +system.cpu2.iq.rate 0.388378 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1535568 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044796 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 107208634 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39678959 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 27407916 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 6919 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3775 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3148 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 35749638 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3674 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 207865 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1582611 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1901 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9388 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 582353 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1585739 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1960 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9442 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 583385 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5366761 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 352360 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5362930 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 352406 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1194753 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4874895 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 91791 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32329432 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 60600 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6536002 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3838530 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 369520 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 31433 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2533 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9388 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 105889 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 88624 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 194513 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33284218 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11095059 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 991129 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1196299 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4872349 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 91583 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32337356 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 60924 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6539665 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3841357 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 369639 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 31243 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2490 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9442 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 106503 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 88749 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 195252 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33287010 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11093708 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 992109 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 81055 # number of nop insts executed -system.cpu2.iew.exec_refs 14494094 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3696710 # Number of branches executed -system.cpu2.iew.exec_stores 3399035 # Number of stores executed -system.cpu2.iew.exec_rate 0.377034 # Inst execution rate -system.cpu2.iew.wb_sent 32864100 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 27405504 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 15677727 # num instructions producing a value -system.cpu2.iew.wb_consumers 28502633 # num instructions consuming a value +system.cpu2.iew.exec_nop 81160 # number of nop insts executed +system.cpu2.iew.exec_refs 14495137 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3696488 # Number of branches executed +system.cpu2.iew.exec_stores 3401429 # Number of stores executed +system.cpu2.iew.exec_rate 0.377138 # Inst execution rate +system.cpu2.iew.wb_sent 32866107 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 27411064 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 15680721 # num instructions producing a value +system.cpu2.iew.wb_consumers 28515439 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.310442 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.550045 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.310564 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.549903 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7348668 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356145 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 169071 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35826783 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.689728 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.717733 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7354772 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 356203 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 169868 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35841861 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.689480 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.717059 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27184585 75.88% 75.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4182145 11.67% 87.55% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1258559 3.51% 91.06% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 654760 1.83% 92.89% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 571167 1.59% 94.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 316320 0.88% 95.37% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 401210 1.12% 96.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 290625 0.81% 97.30% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 967412 2.70% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27192796 75.87% 75.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4189244 11.69% 87.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1258322 3.51% 91.07% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 656013 1.83% 92.90% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 572033 1.60% 94.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 315336 0.88% 95.37% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 400135 1.12% 96.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 291160 0.81% 97.30% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 966822 2.70% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35826783 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20002486 # Number of instructions committed -system.cpu2.commit.committedOps 24710742 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35841861 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20002488 # Number of instructions committed +system.cpu2.commit.committedOps 24712245 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8209568 # Number of memory references committed -system.cpu2.commit.loads 4953391 # Number of loads committed -system.cpu2.commit.membars 94240 # Number of memory barriers committed -system.cpu2.commit.branches 3168906 # Number of branches committed -system.cpu2.commit.fp_insts 3119 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 21931175 # Number of committed integer instructions. -system.cpu2.commit.function_calls 294969 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 967412 # number cycles where commit BW limit reached +system.cpu2.commit.refs 8211898 # Number of memory references committed +system.cpu2.commit.loads 4953926 # Number of loads committed +system.cpu2.commit.membars 94216 # Number of memory barriers committed +system.cpu2.commit.branches 3168186 # Number of branches committed +system.cpu2.commit.fp_insts 3103 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 21932897 # Number of committed integer instructions. +system.cpu2.commit.function_calls 294982 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 966822 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66393860 # The number of ROB reads -system.cpu2.rob.rob_writes 65354684 # The number of ROB writes -system.cpu2.timesIdled 360581 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51257346 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3567291742 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 19948293 # Number of Instructions Simulated -system.cpu2.committedOps 24656549 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 19948293 # Number of Instructions Simulated -system.cpu2.cpi 4.425392 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.425392 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.225969 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.225969 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 153783407 # number of integer regfile reads -system.cpu2.int_regfile_writes 29255277 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22374 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20830 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9021591 # number of misc regfile reads -system.cpu2.misc_regfile_writes 240632 # number of misc regfile writes +system.cpu2.rob.rob_reads 66417184 # The number of ROB reads +system.cpu2.rob.rob_writes 65371468 # The number of ROB writes +system.cpu2.timesIdled 360346 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51223890 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3567293863 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 19948231 # Number of Instructions Simulated +system.cpu2.committedOps 24657988 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 19948231 # Number of Instructions Simulated +system.cpu2.cpi 4.424562 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.424562 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.226011 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.226011 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 153801675 # number of integer regfile reads +system.cpu2.int_regfile_writes 29257373 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22358 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20826 # number of floating regfile writes +system.cpu2.misc_regfile_reads 9025255 # number of misc regfile reads +system.cpu2.misc_regfile_writes 240725 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1536,10 +1536,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 975317722127 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 975317722127 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 975317722127 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 975317722127 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981026264436 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 981026264436 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981026264436 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 981026264436 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index eb64a2a8c..83e83b33f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,145 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.543226 # Number of seconds simulated -sim_ticks 2543226083000 # Number of ticks simulated -final_tick 2543226083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.543301 # Number of seconds simulated +sim_ticks 2543301032500 # Number of ticks simulated +final_tick 2543301032500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48764 # Simulator instruction rate (inst/s) -host_op_rate 62745 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2056325427 # Simulator tick rate (ticks/s) -host_mem_usage 443444 # Number of bytes of host memory used -host_seconds 1236.78 # Real time elapsed on the host -sim_insts 60309820 # Number of instructions simulated -sim_ops 77602107 # Number of ops (including micro ops) simulated +host_inst_rate 74756 # Simulator instruction rate (inst/s) +host_op_rate 96190 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3152487696 # Simulator tick rate (ticks/s) +host_mem_usage 404224 # Number of bytes of host memory used +host_seconds 806.76 # Real time elapsed on the host +sim_insts 60309843 # Number of instructions simulated +sim_ops 77602131 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 2112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 2048 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 511168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4147472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 290304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4947228 # Number of bytes read from this memory -system.physmem.bytes_read::total 131010156 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 511168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 290304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 801472 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3787712 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 508544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4232464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 292032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4862300 # Number of bytes read from this memory +system.physmem.bytes_read::total 131009324 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 508544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 292032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 800576 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3788480 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 1346148 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 1669964 # Number of bytes written to this memory -system.physmem.bytes_written::total 6803824 # Number of bytes written to this memory +system.physmem.bytes_written::total 6804592 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 33 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 32 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7987 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 64838 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4536 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 77307 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293538 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59183 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7946 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 66166 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4563 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 75980 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293525 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59195 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 336537 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 417491 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813211 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47620826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 830 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813223 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47619423 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 805 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 200992 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1630792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 478 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 114148 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1945257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51513374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 200992 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 114148 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315140 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1489334 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 529307 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 656632 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2675273 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1489334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47620826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 199954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1664162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 114824 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1911807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51511529 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 199954 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 114824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314778 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1489592 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 529292 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 656613 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2675496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1489592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47619423 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 805 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 200992 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2160099 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 114148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2601889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54188647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293538 # Total number of read requests seen -system.physmem.writeReqs 813211 # Total number of write requests seen -system.physmem.cpureqs 218552 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978786432 # Total number of bytes read from memory -system.physmem.bytesWritten 52045504 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131010156 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6803824 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu0.inst 199954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2193453 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 114824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2568420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54187025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293525 # Total number of read requests seen +system.physmem.writeReqs 813223 # Total number of write requests seen +system.physmem.cpureqs 218526 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978785600 # Total number of bytes read from memory +system.physmem.bytesWritten 52046272 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131009324 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6804592 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4690 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956233 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 4665 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956243 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 955738 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955679 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956493 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956273 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955443 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955569 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956157 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956101 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955609 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955527 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955677 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956490 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 956276 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955444 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955565 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 956160 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956100 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955526 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 955934 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956035 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955435 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 955318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955983 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50828 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50414 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50437 # Track writes on a per bank basis +system.physmem.perBankRdReqs::12 956026 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 955429 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 955315 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955980 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50841 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50418 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50434 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 51162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50915 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50189 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50286 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51367 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50807 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51194 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51255 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50732 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50629 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51231 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50916 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50190 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50284 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50863 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51375 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50908 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50806 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51196 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51248 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50726 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50627 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32473 # Number of times wr buffer was full causing retry -system.physmem.totGap 2543224928500 # Total gap between requests +system.physmem.numWrRetry 32474 # Number of times wr buffer was full causing retry +system.physmem.totGap 2543299855000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 43 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154679 # Categorize read packet sizes +system.physmem.readPktSize::6 154666 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754028 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59183 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1054814 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 991597 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 961229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3605153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2718410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2722334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2700441 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 59924 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 109988 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 160459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 109884 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9981 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 10663 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 9196 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59195 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1054830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 991608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3605146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2718488 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2722266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2700528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 59953 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59337 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 109948 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 160370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 109866 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10050 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 9990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 9203 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see @@ -156,59 +156,59 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35249 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35222 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 32763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32598 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 32527 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 32514 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 32504 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 32495 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 32489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32479 # What write queue length does an incoming req see -system.physmem.totQLat 346835420750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 440002912000 # Sum of mem lat for all requests -system.physmem.totBusLat 76467635000 # Total cycles spent in databus access -system.physmem.totBankLat 16699856250 # Total cycles spent in bank access -system.physmem.avgQLat 22678.58 # Average queueing delay per request -system.physmem.avgBankLat 1091.96 # Average bank access latency per request +system.physmem.wrQLenPdf::31 32480 # What write queue length does an incoming req see +system.physmem.totQLat 346872048750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 440039818750 # Sum of mem lat for all requests +system.physmem.totBusLat 76467570000 # Total cycles spent in databus access +system.physmem.totBankLat 16700200000 # Total cycles spent in bank access +system.physmem.avgQLat 22680.99 # Average queueing delay per request +system.physmem.avgBankLat 1091.98 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28770.53 # Average memory access latency -system.physmem.avgRdBW 384.86 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 28772.97 # Average memory access latency +system.physmem.avgRdBW 384.85 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.46 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.51 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.17 # Data bus utilization in percentage system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 1.12 # Average write queue length over time -system.physmem.readRowHits 15218407 # Number of row buffer hits during reads -system.physmem.writeRowHits 794595 # Number of row buffer hits during writes +system.physmem.avgWrQLen 1.13 # Average write queue length over time +system.physmem.readRowHits 15218379 # Number of row buffer hits during reads +system.physmem.writeRowHits 794608 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.71 # Row buffer hit rate for writes -system.physmem.avgGap 157898.09 # Average gap between requests +system.physmem.avgGap 157902.75 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory @@ -221,225 +221,225 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64447 # number of replacements -system.l2c.tagsinuse 51415.469971 # Cycle average of tags in use -system.l2c.total_refs 1904213 # Total number of references to valid blocks. -system.l2c.sampled_refs 129841 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.665730 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2506268100000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36946.421058 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 20.318328 # Average occupied blocks per requestor +system.l2c.replacements 64434 # number of replacements +system.l2c.tagsinuse 51415.067512 # Cycle average of tags in use +system.l2c.total_refs 1904100 # Total number of references to valid blocks. +system.l2c.sampled_refs 129827 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.666441 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2506327384000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36945.837156 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 20.213783 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000349 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5214.605130 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3261.076745 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 16.327658 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2998.760808 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2957.959894 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563758 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000310 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.inst 5214.159096 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3260.668190 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 16.334221 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2999.640373 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2958.214345 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563749 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000308 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.079569 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.049760 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.079562 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.049754 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000249 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.045757 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.045135 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.784538 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 33050 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 7442 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 494450 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 217567 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 29984 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6613 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 477029 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 169593 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1435728 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 607829 # number of Writeback hits -system.l2c.Writeback_hits::total 607829 # number of Writeback hits +system.l2c.occ_percent::cpu1.inst 0.045771 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.045139 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.784532 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 32674 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 7484 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 493926 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 214255 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30206 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6691 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 477455 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 172903 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1435594 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 607840 # number of Writeback hits +system.l2c.Writeback_hits::total 607840 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 11 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 29 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 3 # number of SCUpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 14 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 32 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 4 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 5 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57675 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 55157 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112832 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 33050 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 7442 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 494450 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 275242 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 29984 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6613 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 477029 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 224750 # number of demand (read+write) hits -system.l2c.demand_hits::total 1548560 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 33050 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 7442 # number of overall hits -system.l2c.overall_hits::cpu0.inst 494450 # number of overall hits -system.l2c.overall_hits::cpu0.data 275242 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 29984 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6613 # number of overall hits -system.l2c.overall_hits::cpu1.inst 477029 # number of overall hits -system.l2c.overall_hits::cpu1.data 224750 # number of overall hits -system.l2c.overall_hits::total 1548560 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 33 # number of ReadReq misses +system.l2c.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 57831 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 55019 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112850 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 32674 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 7484 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 493926 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 272086 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 30206 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6691 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 477455 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 227922 # number of demand (read+write) hits +system.l2c.demand_hits::total 1548444 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 32674 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 7484 # number of overall hits +system.l2c.overall_hits::cpu0.inst 493926 # number of overall hits +system.l2c.overall_hits::cpu0.data 272086 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30206 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6691 # number of overall hits +system.l2c.overall_hits::cpu1.inst 477455 # number of overall hits +system.l2c.overall_hits::cpu1.data 227922 # number of overall hits +system.l2c.overall_hits::total 1548444 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 32 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7877 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6086 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 19 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4540 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4624 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23181 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1632 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1283 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2915 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 59765 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 73463 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133228 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 33 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 7836 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6093 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 20 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 4567 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4625 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23175 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1542 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1367 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2909 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 61052 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 72150 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133202 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 32 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7877 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 65851 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 19 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4540 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 78087 # number of demand (read+write) misses -system.l2c.demand_misses::total 156409 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 33 # number of overall misses +system.l2c.demand_misses::cpu0.inst 7836 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 67145 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 20 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 4567 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 76775 # number of demand (read+write) misses +system.l2c.demand_misses::total 156377 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 32 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7877 # number of overall misses -system.l2c.overall_misses::cpu0.data 65851 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 19 # number of overall misses -system.l2c.overall_misses::cpu1.inst 4540 # number of overall misses -system.l2c.overall_misses::cpu1.data 78087 # number of overall misses -system.l2c.overall_misses::total 156409 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2765500 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu0.inst 7836 # number of overall misses +system.l2c.overall_misses::cpu0.data 67145 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 20 # number of overall misses +system.l2c.overall_misses::cpu1.inst 4567 # number of overall misses +system.l2c.overall_misses::cpu1.data 76775 # number of overall misses +system.l2c.overall_misses::total 156377 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2696500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 118000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 434812500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 348876500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1306000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 265734500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 270200000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1323813000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 205500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 182500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 388000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3099799500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3655844500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6755644000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 2765500 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 433331500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 351362499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1374500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 265787000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 271348500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1326018499 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 182500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 204500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 387000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3189901000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3583059500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6772960500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 2696500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 118000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 434812500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3448676000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1306000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 265734500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3926044500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8079457000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 2765500 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 433331500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3541263499 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1374500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 265787000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3854408000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8098978999 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 2696500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 118000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 434812500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3448676000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1306000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 265734500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3926044500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8079457000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 33083 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 7444 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 502327 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 223653 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 30003 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6613 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 481569 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 174217 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1458909 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 607829 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 607829 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1650 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1294 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2944 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 3 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu0.inst 433331500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3541263499 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1374500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 265787000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3854408000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8098978999 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 32706 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 7486 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 501762 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 220348 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 30226 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 6691 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 482022 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 177528 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1458769 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 607840 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 607840 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1560 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1381 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2941 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 4 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 5 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 8 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 117440 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 128620 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246060 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 33083 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 7444 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 502327 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 341093 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 30003 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6613 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 481569 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 302837 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1704969 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 33083 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 7444 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 502327 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 341093 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 30003 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6613 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 481569 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 302837 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1704969 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000997 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000269 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015681 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.027212 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000633 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009428 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.026542 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015889 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989091 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991499 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.990149 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.508898 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.571163 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541445 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000997 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000269 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015681 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.193059 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000633 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009428 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.257852 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.091737 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000997 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000269 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015681 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.193059 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000633 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009428 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.257852 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.091737 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83803.030303 # average ReadReq miss latency +system.l2c.SCUpgradeReq_accesses::total 9 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 118883 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 127169 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246052 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 32706 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 7486 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 501762 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 339231 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 30226 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6691 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 482022 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 304697 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1704821 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 32706 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 7486 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 501762 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 339231 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 30226 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6691 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 482022 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 304697 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1704821 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000978 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000267 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015617 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.027652 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000662 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009475 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.026052 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015887 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.988462 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989862 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.989119 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.513547 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.567355 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.541357 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000978 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000267 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015617 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.197933 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000662 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009475 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.251972 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.091726 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000978 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000267 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015617 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.197933 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000662 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009475 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.251972 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.091726 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 84265.625000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 59000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55200.266599 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 57324.433125 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 68736.842105 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 58531.828194 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 58434.256055 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 57107.674389 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 125.919118 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 142.244739 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 133.104631 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 51866.468669 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 49764.432435 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 50707.388837 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83803.030303 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55300.089331 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 57666.584441 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 68725 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 58197.284870 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 58669.945946 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 57217.626710 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 118.352789 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 149.597659 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 133.035407 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52248.918954 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 49661.254331 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 50847.288329 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 84265.625000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 55200.266599 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52370.897936 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 68736.842105 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 58531.828194 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 50277.824734 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 51655.959695 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83803.030303 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 55300.089331 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52740.539117 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 68725 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 58197.284870 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 50203.946597 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 51791.369568 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 84265.625000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 55200.266599 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52370.897936 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 68736.842105 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 58531.828194 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 50277.824734 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 51655.959695 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 55300.089331 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52740.539117 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 68725 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 58197.284870 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 50203.946597 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 51791.369568 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -448,8 +448,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 59183 # number of writebacks -system.l2c.writebacks::total 59183 # number of writebacks +system.l2c.writebacks::writebacks 59195 # number of writebacks +system.l2c.writebacks::total 59195 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 9 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu0.data 42 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits @@ -465,141 +465,141 @@ system.l2c.overall_mshr_hits::cpu0.data 42 # nu system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 19 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 33 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 32 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 7868 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6044 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 19 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 4536 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4605 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23107 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1632 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1283 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2915 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 59765 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 73463 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133228 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 33 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 7827 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6051 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 20 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 4563 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4606 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 23101 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1542 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1367 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2909 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 61052 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 72150 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133202 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 32 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 7868 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 65809 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 19 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 4536 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 78068 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 156335 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 33 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 7827 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 67103 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 20 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 4563 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 76756 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 156303 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 32 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 7868 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 65809 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 19 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 4536 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 78068 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 156335 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2354282 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu0.inst 7827 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 67103 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 20 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 4563 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 76756 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 156303 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2297031 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 93251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 336517819 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 271517668 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1068769 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 209058491 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 211521322 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1032131602 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 16321632 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 12832782 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 29154414 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2354223480 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2740919006 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5095142486 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2354282 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 335537534 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 273929174 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1125020 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 208772018 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 212715078 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1034469106 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 15421542 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13671367 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 29092909 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2428445133 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2684323323 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5112768456 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2297031 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93251 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 336517819 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2625741148 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1068769 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 209058491 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2952440328 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6127274088 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2354282 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 335537534 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2702374307 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1125020 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 208772018 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2897038401 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6147237562 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2297031 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93251 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 336517819 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2625741148 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1068769 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 209058491 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2952440328 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6127274088 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 335537534 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2702374307 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1125020 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 208772018 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2897038401 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6147237562 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5052330 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83994636767 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82967803004 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166967492101 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 10493457778 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 13230278140 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 23723735918 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84065259767 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82897447004 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166967759101 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 10492990778 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 13230163640 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 23723154418 # number of WriteReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 76253 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 76253 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 30003 # number of StoreCondReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::total 30003 # number of StoreCondReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5052330 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94488094545 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 96198081144 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 190691228019 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000997 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000269 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015663 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027024 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000633 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009419 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026433 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015839 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.989091 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991499 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.990149 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.508898 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.571163 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541445 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000997 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000269 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015663 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.192936 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000633 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009419 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.257789 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.091694 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000997 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000269 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015663 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.192936 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000633 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009419 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.257789 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091694 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71341.878788 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94558250545 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 96127610644 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 190690913519 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000978 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000267 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015599 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027461 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000662 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009466 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025945 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015836 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988462 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989862 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.989119 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.513547 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567355 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541357 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000978 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000267 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015599 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.197809 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000662 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009466 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.251909 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091683 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000978 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000267 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015599 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.197809 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000662 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009466 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.251909 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091683 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71782.218750 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42770.439629 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44923.505625 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42869.239044 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45270.066766 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 46088.732584 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45932.968947 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 44667.486130 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 45753.236467 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46182.170647 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 44780.273841 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.168355 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.514237 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39391.340751 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37310.197052 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 38243.781232 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71341.878788 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39776.667972 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37204.758462 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 38383.571238 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71782.218750 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42770.439629 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 39899.423301 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42869.239044 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40272.034142 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 46088.732584 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37818.828816 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39193.233044 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71341.878788 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 45753.236467 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37743.478047 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39328.980007 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71782.218750 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42770.439629 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 39899.423301 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42869.239044 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40272.034142 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46088.732584 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37818.828816 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39193.233044 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 45753.236467 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37743.478047 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39328.980007 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -622,680 +622,680 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 7719049 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6144205 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 388400 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 5016002 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4082948 # Number of BTB hits +system.cpu0.branchPred.lookups 7635591 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6085397 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 382495 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4962348 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4056906 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.398452 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 737953 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39729 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.753759 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 731596 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39324 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 26145640 # DTB read hits -system.cpu0.dtb.read_misses 41213 # DTB read misses -system.cpu0.dtb.write_hits 5906110 # DTB write hits -system.cpu0.dtb.write_misses 9202 # DTB write misses +system.cpu0.dtb.read_hits 26057064 # DTB read hits +system.cpu0.dtb.read_misses 40223 # DTB read misses +system.cpu0.dtb.write_hits 5918699 # DTB write hits +system.cpu0.dtb.write_misses 9531 # DTB write misses system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5753 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1471 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 281 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5688 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1419 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 294 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 691 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 26186853 # DTB read accesses -system.cpu0.dtb.write_accesses 5915312 # DTB write accesses +system.cpu0.dtb.perms_faults 673 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 26097287 # DTB read accesses +system.cpu0.dtb.write_accesses 5928230 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 32051750 # DTB hits -system.cpu0.dtb.misses 50415 # DTB misses -system.cpu0.dtb.accesses 32102165 # DTB accesses -system.cpu0.itb.inst_hits 6183534 # ITB inst hits -system.cpu0.itb.inst_misses 7751 # ITB inst misses +system.cpu0.dtb.hits 31975763 # DTB hits +system.cpu0.dtb.misses 49754 # DTB misses +system.cpu0.dtb.accesses 32025517 # DTB accesses +system.cpu0.itb.inst_hits 6123062 # ITB inst hits +system.cpu0.itb.inst_misses 7629 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2745 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2663 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1565 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1589 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6191285 # ITB inst accesses -system.cpu0.itb.hits 6183534 # DTB hits -system.cpu0.itb.misses 7751 # DTB misses -system.cpu0.itb.accesses 6191285 # DTB accesses -system.cpu0.numCycles 239079415 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6130691 # ITB inst accesses +system.cpu0.itb.hits 6123062 # DTB hits +system.cpu0.itb.misses 7629 # DTB misses +system.cpu0.itb.accesses 6130691 # DTB accesses +system.cpu0.numCycles 239038664 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15644570 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 48338125 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7719049 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4820901 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10703205 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2596540 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 94746 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 49591987 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1783 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1964 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 53331 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 101492 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 276 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6181495 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 400642 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3259 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77992242 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.765373 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.123716 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15574951 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 47914738 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7635591 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4788502 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10629711 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2569699 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 94247 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 49519281 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1748 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 2018 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 51773 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 101169 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 218 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6121027 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 398928 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3254 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77753565 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.762466 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.119834 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67296980 86.29% 86.29% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 702662 0.90% 87.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 892389 1.14% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1243235 1.59% 89.93% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1139067 1.46% 91.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 581520 0.75% 92.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1338462 1.72% 93.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 402047 0.52% 94.36% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4395880 5.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67131545 86.34% 86.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 691431 0.89% 87.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 886662 1.14% 88.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1230744 1.58% 89.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1150970 1.48% 91.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 576090 0.74% 92.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1323248 1.70% 93.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 399344 0.51% 94.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4363531 5.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77992242 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.032287 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.202184 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16701716 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49328258 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9693840 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 556609 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1709696 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1049154 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 91765 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56812427 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 306906 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1709696 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17642458 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 18978880 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27077809 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9239108 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3342271 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 53967560 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 13437 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 629408 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2165949 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 513 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 56184131 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 245540949 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 245492809 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 48140 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 40778039 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 15406092 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 434005 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 385260 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6805574 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10494917 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6795022 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1080492 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1313371 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 50078322 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1031134 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 63522685 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 99823 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10628436 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 26923896 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 250828 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77992242 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.814474 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.519995 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77753565 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031943 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.200448 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16625563 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49255605 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9626158 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 554470 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1689651 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1030343 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 91400 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56424531 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 305535 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1689651 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17561755 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 18982691 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27011773 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9171817 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3333839 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 53601005 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 13486 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 625862 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2162558 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 496 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 55732914 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 244003598 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 243955563 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 48035 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 40460066 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 15272848 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 429896 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 381627 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6785358 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10376846 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6807542 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1061382 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1293746 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 49728955 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1043658 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 63251434 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 97401 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10543512 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 26574090 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 266492 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77753565 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.813486 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.519509 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 55011307 70.53% 70.53% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7277871 9.33% 79.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3728534 4.78% 84.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3132981 4.02% 88.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6315907 8.10% 96.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1400012 1.80% 98.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 822343 1.05% 99.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 235239 0.30% 99.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 68048 0.09% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54887435 70.59% 70.59% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7226514 9.29% 79.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3706413 4.77% 84.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3121683 4.01% 88.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6295236 8.10% 96.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1399247 1.80% 98.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 816831 1.05% 99.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 232768 0.30% 99.91% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 67438 0.09% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77992242 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77753565 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 33040 0.74% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 3 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4225834 94.61% 95.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 207543 4.65% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 32377 0.72% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 4 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4226171 94.63% 95.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 207252 4.64% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 193689 0.30% 0.30% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 30176884 47.51% 47.81% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47977 0.08% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 8 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1219 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26869653 42.30% 90.19% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6233244 9.81% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 195848 0.31% 0.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29986404 47.41% 47.72% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47518 0.08% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 4 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 2 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1215 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26774233 42.33% 90.12% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6246205 9.88% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 63522685 # Type of FU issued -system.cpu0.iq.rate 0.265697 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4466420 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.070312 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 209641938 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61746831 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 44505201 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12130 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6615 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5501 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 67789033 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6383 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 329345 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 63251434 # Type of FU issued +system.cpu0.iq.rate 0.264608 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4465804 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.070604 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 208856960 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61325058 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 44235430 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12232 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6621 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5553 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 67514929 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6461 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 324203 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2321629 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3668 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 16120 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 899548 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2284618 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3570 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 16131 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 894521 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17127140 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 367757 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17140357 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 367566 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1709696 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14213295 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 236264 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 51235944 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 105063 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10494917 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6795022 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 726682 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 58301 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3691 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 16120 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 190260 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 151203 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 341463 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 62339008 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26506413 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1183677 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1689651 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14217323 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 235152 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50889581 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 104636 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10376846 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6807542 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 742609 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 56975 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3444 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 16131 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 187025 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 148295 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 335320 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 62072955 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26415193 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1178479 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 126488 # number of nop insts executed -system.cpu0.iew.exec_refs 32682490 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6088882 # Number of branches executed -system.cpu0.iew.exec_stores 6176077 # Number of stores executed -system.cpu0.iew.exec_rate 0.260746 # Inst execution rate -system.cpu0.iew.wb_sent 61801058 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 44510702 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24520944 # num instructions producing a value -system.cpu0.iew.wb_consumers 44899908 # num instructions consuming a value +system.cpu0.iew.exec_nop 116968 # number of nop insts executed +system.cpu0.iew.exec_refs 32604278 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6035543 # Number of branches executed +system.cpu0.iew.exec_stores 6189085 # Number of stores executed +system.cpu0.iew.exec_rate 0.259677 # Inst execution rate +system.cpu0.iew.wb_sent 61541297 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 44240983 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24348710 # num instructions producing a value +system.cpu0.iew.wb_consumers 44715244 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.186175 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.546125 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.185079 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.544528 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 10516243 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 780306 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 297973 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 76282546 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.527732 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.509463 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 10387971 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 777166 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 292435 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 76063914 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.525878 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.507211 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61930092 81.19% 81.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6958991 9.12% 90.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2075873 2.72% 93.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1156776 1.52% 94.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1044437 1.37% 95.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 552027 0.72% 96.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 702446 0.92% 97.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 372143 0.49% 98.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1489761 1.95% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61806692 81.26% 81.26% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6917678 9.09% 90.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2055110 2.70% 93.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1140236 1.50% 94.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1042779 1.37% 95.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 551797 0.73% 96.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 701755 0.92% 97.57% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 371851 0.49% 98.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1476016 1.94% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 76282546 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 31604949 # Number of instructions committed -system.cpu0.commit.committedOps 40256713 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 76063914 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 31320190 # Number of instructions committed +system.cpu0.commit.committedOps 40000322 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14068762 # Number of memory references committed -system.cpu0.commit.loads 8173288 # Number of loads committed -system.cpu0.commit.membars 214624 # Number of memory barriers committed -system.cpu0.commit.branches 5267155 # Number of branches committed -system.cpu0.commit.fp_insts 5449 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 35547917 # Number of committed integer instructions. -system.cpu0.commit.function_calls 518151 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1489761 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14005249 # Number of memory references committed +system.cpu0.commit.loads 8092228 # Number of loads committed +system.cpu0.commit.membars 212474 # Number of memory barriers committed +system.cpu0.commit.branches 5211695 # Number of branches committed +system.cpu0.commit.fp_insts 5465 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 35344589 # Number of committed integer instructions. +system.cpu0.commit.function_calls 514446 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1476016 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 124585414 # The number of ROB reads -system.cpu0.rob.rob_writes 103297804 # The number of ROB writes -system.cpu0.timesIdled 884994 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 161087173 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2289793652 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 31519096 # Number of Instructions Simulated -system.cpu0.committedOps 40170860 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 31519096 # Number of Instructions Simulated -system.cpu0.cpi 7.585224 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.585224 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.131835 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.131835 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 282333154 # number of integer regfile reads -system.cpu0.int_regfile_writes 45811922 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22666 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19880 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15681354 # number of misc regfile reads -system.cpu0.misc_regfile_writes 434463 # number of misc regfile writes -system.cpu0.icache.replacements 984470 # number of replacements -system.cpu0.icache.tagsinuse 511.608417 # Cycle average of tags in use -system.cpu0.icache.total_refs 11039436 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 984982 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 11.207754 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 123998072 # The number of ROB reads +system.cpu0.rob.rob_writes 102508386 # The number of ROB writes +system.cpu0.timesIdled 885261 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 161285099 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2289741427 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 31240748 # Number of Instructions Simulated +system.cpu0.committedOps 39920880 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 31240748 # Number of Instructions Simulated +system.cpu0.cpi 7.651503 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 7.651503 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.130693 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.130693 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 281024230 # number of integer regfile reads +system.cpu0.int_regfile_writes 45498524 # number of integer regfile writes +system.cpu0.fp_regfile_reads 22712 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19798 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15634103 # number of misc regfile reads +system.cpu0.misc_regfile_writes 430225 # number of misc regfile writes +system.cpu0.icache.replacements 984356 # number of replacements +system.cpu0.icache.tagsinuse 511.608403 # Cycle average of tags in use +system.cpu0.icache.total_refs 11036978 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 984868 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 11.206556 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6537508000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 358.593548 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 153.014869 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.700378 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.298857 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 359.190801 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 152.417601 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.701545 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.297691 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.999235 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5636954 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5402482 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 11039436 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5636954 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5402482 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 11039436 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5636954 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5402482 # number of overall hits -system.cpu0.icache.overall_hits::total 11039436 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 544416 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 521534 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065950 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 544416 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 521534 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065950 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 544416 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 521534 # number of overall misses -system.cpu0.icache.overall_misses::total 1065950 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7382097491 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6930257996 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14312355487 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7382097491 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6930257996 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14312355487 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7382097491 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6930257996 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14312355487 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6181370 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5924016 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 12105386 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6181370 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5924016 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 12105386 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6181370 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5924016 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 12105386 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088074 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.088037 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.088056 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088074 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.088037 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.088056 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088074 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.088037 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.088056 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13559.662999 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13288.218977 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13426.854437 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13559.662999 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13288.218977 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13426.854437 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13559.662999 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13288.218977 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13426.854437 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5254 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 5577013 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5459965 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 11036978 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5577013 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5459965 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 11036978 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5577013 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5459965 # number of overall hits +system.cpu0.icache.overall_hits::total 11036978 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 543890 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 521924 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1065814 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 543890 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 521924 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1065814 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 543890 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 521924 # number of overall misses +system.cpu0.icache.overall_misses::total 1065814 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7368318492 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6936357997 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14304676489 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7368318492 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6936357997 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14304676489 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7368318492 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6936357997 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14304676489 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6120903 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5981889 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 12102792 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6120903 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5981889 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 12102792 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6120903 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5981889 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 12102792 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088858 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087251 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.088063 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088858 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087251 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.088063 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088858 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087251 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.088063 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13547.442483 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13289.977079 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13421.362910 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13547.442483 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13289.977079 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13421.362910 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13547.442483 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13289.977079 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13421.362910 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4739 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 847 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 386 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 348 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.611399 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.617816 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets 847 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41493 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39456 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 80949 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 41493 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 39456 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 80949 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 41493 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 39456 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 80949 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 502923 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 482078 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 985001 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 502923 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 482078 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 985001 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 502923 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 482078 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 985001 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6018484991 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5644614996 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11663099987 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6018484991 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5644614996 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11663099987 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6018484991 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5644614996 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11663099987 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41550 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39375 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 80925 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 41550 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 39375 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 80925 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 41550 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 39375 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 80925 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 502340 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 482549 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 984889 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 502340 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 482549 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 984889 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 502340 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 482549 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 984889 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6009302492 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5650286997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11659589489 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6009302492 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5650286997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11659589489 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6009302492 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5650286997 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11659589489 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7527500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7527500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7527500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7527500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081361 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081377 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081369 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081361 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.081377 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.081369 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.081361 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.081377 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.081369 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11967.010837 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11708.924689 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11840.698626 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11967.010837 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11708.924689 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11840.698626 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11967.010837 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11708.924689 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11840.698626 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.082070 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.080668 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081377 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.082070 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.080668 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.081377 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.082070 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.080668 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.081377 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11962.619923 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11709.250246 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11838.480772 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11962.619923 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11709.250246 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11838.480772 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11962.619923 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11709.250246 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11838.480772 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 643418 # number of replacements +system.cpu0.dcache.replacements 643416 # number of replacements system.cpu0.dcache.tagsinuse 511.992721 # Cycle average of tags in use -system.cpu0.dcache.total_refs 21533730 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 643930 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.441104 # Average number of references to valid blocks. +system.cpu0.dcache.total_refs 21533980 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 643928 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.441596 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 43205000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 319.254285 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 192.738436 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.623544 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.376442 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 319.135976 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 192.856745 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.623312 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.376673 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7222864 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6555051 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13777915 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3783291 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3477957 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7261248 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 126614 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117265 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243879 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 128750 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 118867 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247617 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11006155 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10033008 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21039163 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11006155 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10033008 # number of overall hits -system.cpu0.dcache.overall_hits::total 21039163 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 443968 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 305583 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 749551 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1380597 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1580939 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2961536 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6950 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6643 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13593 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3 # number of StoreCondReq misses +system.cpu0.dcache.ReadReq_hits::cpu0.data 7135768 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6642238 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13778006 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3777278 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3484344 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7261622 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 125855 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117826 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243681 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127868 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 119748 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247616 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10913046 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 10126582 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 21039628 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10913046 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 10126582 # number of overall hits +system.cpu0.dcache.overall_hits::total 21039628 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 434985 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 314667 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 749652 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1404591 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1556569 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2961160 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6908 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6675 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13583 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 5 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1824565 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1886522 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3711087 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1824565 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1886522 # number of overall misses -system.cpu0.dcache.overall_misses::total 3711087 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6592316000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 4802887000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11395203000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52073406352 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 62127905305 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 114201311657 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 94083500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 92681000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 186764500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 39000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1839576 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 1871236 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3710812 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1839576 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1871236 # number of overall misses +system.cpu0.dcache.overall_misses::total 3710812 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6475247500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 4924263000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11399510500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 53630269354 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 60756601793 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 114386871147 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 93311000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 93587500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 186898500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 52000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 65000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 104000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 58665722352 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 66930792305 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 125596514657 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 58665722352 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 66930792305 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 125596514657 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7666832 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6860634 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14527466 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5163888 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5058896 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10222784 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 133564 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 123908 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 257472 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 128753 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 118872 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_miss_latency::total 117000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 60105516854 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 65680864793 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 125786381647 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 60105516854 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 65680864793 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 125786381647 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7570753 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6956905 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 14527658 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5181869 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5040913 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10222782 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132763 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 124501 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 257264 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127872 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 119753 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247625 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12830720 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11919530 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24750250 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12830720 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 11919530 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24750250 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.057908 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.044542 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051595 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.267356 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.312507 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289700 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.052035 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.053612 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052794 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000023 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 12752622 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 11997818 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24750440 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12752622 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 11997818 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24750440 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.057456 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.045231 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.051602 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.271059 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.308787 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.289663 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.052033 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.053614 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052798 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000031 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000042 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000032 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.142203 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.158272 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.149941 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.142203 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.158272 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.149941 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14848.628730 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15717.127589 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15202.705353 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37718.035279 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39298.104041 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38561.513909 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13537.194245 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13951.678459 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13739.755757 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000036 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.144251 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.155965 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.149929 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.144251 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.155965 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.149929 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14886.139752 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15649.124312 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15206.403104 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38182.125155 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39032.385839 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38629.074804 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13507.672264 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14020.599251 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13759.736435 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32153.265218 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35478.405396 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33843.592095 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32153.265218 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35478.405396 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33843.592095 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 34838 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 14844 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3534 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 260 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.857951 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 57.092308 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32673.570896 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35100.257152 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33897.266056 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32673.570896 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35100.257152 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33897.266056 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 35700 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 14875 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3523 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 259 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.133409 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 57.432432 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 607829 # number of writebacks -system.cpu0.dcache.writebacks::total 607829 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 226509 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 137269 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 363778 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1261567 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1451066 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2712633 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 696 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 699 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1395 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1488076 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1588335 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3076411 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1488076 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1588335 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3076411 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 217459 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 168314 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 385773 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119030 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 129873 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 248903 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6254 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5944 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12198 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3 # number of StoreCondReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 607840 # number of writebacks +system.cpu0.dcache.writebacks::total 607840 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 220807 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 143078 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 363885 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1284196 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1428063 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2712259 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 690 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 692 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1382 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1505003 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1571141 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3076144 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1505003 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1571141 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3076144 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 214178 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 171589 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 385767 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 120395 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 128506 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 248901 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6218 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5983 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12201 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 5 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 336489 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 298187 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 634676 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 336489 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 298187 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 634676 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2948842500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2284266500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5233109000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3938983490 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4499310442 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8438293932 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 73127000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72549000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145676000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 33000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 334573 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 300095 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 634668 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 334573 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 300095 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 634668 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2912392000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2322926000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5235318000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4032811992 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4423017439 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8455829431 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72820000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73471000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146291000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 44000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 55000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 88000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6887825990 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6783576942 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13671402932 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6887825990 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6783576942 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13671402932 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91735466000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90620432500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182355898500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14921149436 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18671847220 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33592996656 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 99000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6945203992 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6745943439 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13691147431 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6945203992 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6745943439 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13691147431 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91812195000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90543970000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182356165000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14920751936 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18671646220 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33592398156 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106656615436 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109292279720 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215948895156 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028364 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024533 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026555 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023050 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025672 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106732946936 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109215616220 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215948563156 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028290 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024665 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026554 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023234 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025493 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024348 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046824 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047971 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047376 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000023 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046835 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048056 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047426 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000031 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000042 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000032 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026225 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025017 # mshr miss rate for demand accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000036 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026236 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025012 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.025643 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026225 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025017 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026236 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025012 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.025643 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13560.452775 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13571.458702 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13565.254696 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33092.358985 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34643.924773 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33901.937429 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11692.836585 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12205.417227 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11942.613543 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13597.997927 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13537.732605 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13571.191937 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33496.507264 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34418.762073 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33972.661544 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11711.161145 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12279.959886 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11990.082780 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20469.691402 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22749.405380 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21540.759272 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20469.691402 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22749.405380 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21540.759272 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20758.411444 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22479.359666 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21572.140759 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20758.411444 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22479.359666 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21572.140759 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1310,324 +1310,324 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 6924581 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5562771 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 336228 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4476731 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3769892 # Number of BTB hits +system.cpu1.branchPred.lookups 7008518 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5622209 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 340954 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4512372 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3795619 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 84.210823 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 665809 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 34604 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 84.115826 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 671281 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 35132 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25217799 # DTB read hits -system.cpu1.dtb.read_misses 35648 # DTB read misses -system.cpu1.dtb.write_hits 5810779 # DTB write hits -system.cpu1.dtb.write_misses 9529 # DTB write misses +system.cpu1.dtb.read_hits 25306381 # DTB read hits +system.cpu1.dtb.read_misses 36302 # DTB read misses +system.cpu1.dtb.write_hits 5796978 # DTB write hits +system.cpu1.dtb.write_misses 9188 # DTB write misses system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5398 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1388 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 230 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5467 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1344 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 228 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 634 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25253447 # DTB read accesses -system.cpu1.dtb.write_accesses 5820308 # DTB write accesses +system.cpu1.dtb.perms_faults 638 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25342683 # DTB read accesses +system.cpu1.dtb.write_accesses 5806166 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31028578 # DTB hits -system.cpu1.dtb.misses 45177 # DTB misses -system.cpu1.dtb.accesses 31073755 # DTB accesses -system.cpu1.itb.inst_hits 5925943 # ITB inst hits -system.cpu1.itb.inst_misses 6573 # ITB inst misses +system.cpu1.dtb.hits 31103359 # DTB hits +system.cpu1.dtb.misses 45490 # DTB misses +system.cpu1.dtb.accesses 31148849 # DTB accesses +system.cpu1.itb.inst_hits 5983864 # ITB inst hits +system.cpu1.itb.inst_misses 6799 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2476 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2574 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1382 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1412 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5932516 # ITB inst accesses -system.cpu1.itb.hits 5925943 # DTB hits -system.cpu1.itb.misses 6573 # DTB misses -system.cpu1.itb.accesses 5932516 # DTB accesses -system.cpu1.numCycles 234244847 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5990663 # ITB inst accesses +system.cpu1.itb.hits 5983864 # DTB hits +system.cpu1.itb.misses 6799 # DTB misses +system.cpu1.itb.accesses 5990663 # DTB accesses +system.cpu1.numCycles 234290379 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15045426 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46051404 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 6924581 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4435701 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10180178 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2576164 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 79323 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 47488838 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 962 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 2036 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 40665 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 94257 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 230 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5924019 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 441347 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2911 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 74691954 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.768024 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.131487 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 15116451 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46466902 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7008518 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4466900 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10252429 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2600331 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 81459 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 47550524 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 905 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 2006 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 43802 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 94777 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 144 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5981892 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 442637 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2912 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 74921475 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.771035 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.135527 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 64519001 86.38% 86.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 606919 0.81% 87.19% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 824654 1.10% 88.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1190723 1.59% 89.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1057088 1.42% 91.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 528345 0.71% 92.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1354186 1.81% 93.83% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 346670 0.46% 94.29% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4264368 5.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 64676712 86.33% 86.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 618864 0.83% 87.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 829977 1.11% 88.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1202840 1.61% 89.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1044061 1.39% 91.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 533999 0.71% 91.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1368584 1.83% 93.80% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 349498 0.47% 94.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4296940 5.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 74691954 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.029561 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.196595 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 16048040 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 47278235 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9237318 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 448383 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1677844 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 921418 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 84751 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54328734 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 282420 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1677844 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16980429 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18581446 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 25685933 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8674589 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3089642 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51185611 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 7172 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 483859 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2112197 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 97 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53156547 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 235159359 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 235117285 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 42074 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 37614805 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15541741 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 399062 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 353498 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6213195 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9696990 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6683769 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 865241 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1058674 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47161259 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 954916 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60450494 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 77232 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10409443 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 27466585 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 252722 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 74691954 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.809331 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.520957 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 74921475 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.029914 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.198330 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 16127430 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 47340991 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9302277 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 452157 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1696491 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 939788 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 85014 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54712393 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 283938 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1696491 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17063579 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 18568678 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 25752424 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8740556 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3097679 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51550474 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 7120 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 486939 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2114664 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 95 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53606265 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 236686025 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 236643642 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 42383 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 37932809 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15673455 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 402617 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 356688 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6237356 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9815438 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6669487 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 880329 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1133832 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47508806 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 941900 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60718178 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 80732 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10491137 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 27821920 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 236570 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 74921475 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.810424 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.521077 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53120438 71.12% 71.12% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6581682 8.81% 79.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3495899 4.68% 84.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2849080 3.81% 88.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6224305 8.33% 96.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1417719 1.90% 98.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 735156 0.98% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 208377 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 59298 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53226617 71.04% 71.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6639225 8.86% 79.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3521147 4.70% 84.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2865539 3.82% 88.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6243808 8.33% 96.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1415606 1.89% 98.65% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 739373 0.99% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 210738 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 59422 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 74691954 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 74921475 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 25658 0.59% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4148051 94.78% 95.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 202723 4.63% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 26168 0.60% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 1 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4150795 94.85% 95.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 199100 4.55% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 169977 0.28% 0.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28184247 46.62% 46.90% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 45636 0.08% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 4 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 892 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 25945360 42.92% 89.90% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6104366 10.10% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 167818 0.28% 0.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28373691 46.73% 47.01% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46091 0.08% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 896 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26040141 42.89% 89.97% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6089511 10.03% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60450494 # Type of FU issued -system.cpu1.iq.rate 0.258065 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4376432 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.072397 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 200080953 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 58533998 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41393677 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 10638 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5781 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4780 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 64651317 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5632 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 296486 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 60718178 # Type of FU issued +system.cpu1.iq.rate 0.259158 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4376064 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.072072 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 200849206 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 58949996 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41661656 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 10739 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5891 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4795 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 64920728 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5696 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 301587 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2215043 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3144 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 14677 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 846684 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2252430 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3185 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 14519 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 849951 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16976661 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 457892 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16963490 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 458141 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1677844 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14002380 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 233104 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48212114 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 96608 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9696990 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6683769 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 685390 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 50588 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3685 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 14677 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 163070 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 129112 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 292182 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59083319 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25544592 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1367175 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1696491 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 13989696 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 234454 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48555942 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 97471 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9815438 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6669487 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 669348 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 52364 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3770 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 14519 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 165263 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 131892 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 297155 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59347630 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25635579 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1370548 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 95939 # number of nop insts executed -system.cpu1.iew.exec_refs 31597721 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5452623 # Number of branches executed -system.cpu1.iew.exec_stores 6053129 # Number of stores executed -system.cpu1.iew.exec_rate 0.252229 # Inst execution rate -system.cpu1.iew.wb_sent 58512296 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41398457 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 22553116 # num instructions producing a value -system.cpu1.iew.wb_consumers 41520902 # num instructions consuming a value +system.cpu1.iew.exec_nop 105236 # number of nop insts executed +system.cpu1.iew.exec_refs 31674399 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5507310 # Number of branches executed +system.cpu1.iew.exec_stores 6038820 # Number of stores executed +system.cpu1.iew.exec_rate 0.253308 # Inst execution rate +system.cpu1.iew.wb_sent 58770434 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41666451 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 22724136 # num instructions producing a value +system.cpu1.iew.wb_consumers 41696356 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.176732 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.543175 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.177841 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.544991 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 10281991 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 702194 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 252752 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 73014110 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.513541 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.493879 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 10406617 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 705330 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 257195 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 73224984 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.515564 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.495876 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 59627220 81.67% 81.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6596697 9.03% 90.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1882997 2.58% 93.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 995941 1.36% 94.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 953813 1.31% 95.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 518436 0.71% 96.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 701051 0.96% 97.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 372117 0.51% 98.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1365838 1.87% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 59733735 81.58% 81.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6648402 9.08% 90.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1900730 2.60% 93.25% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1014899 1.39% 94.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 955667 1.31% 95.94% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 519546 0.71% 96.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 702094 0.96% 97.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 374619 0.51% 98.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1375292 1.88% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 73014110 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 28855252 # Number of instructions committed -system.cpu1.commit.committedOps 37495775 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 73224984 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 29140034 # Number of instructions committed +system.cpu1.commit.committedOps 37752190 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13319032 # Number of memory references committed -system.cpu1.commit.loads 7481947 # Number of loads committed -system.cpu1.commit.membars 189014 # Number of memory barriers committed -system.cpu1.commit.branches 4694468 # Number of branches committed -system.cpu1.commit.fp_insts 4763 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33309565 # Number of committed integer instructions. -system.cpu1.commit.function_calls 473164 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1365838 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13382544 # Number of memory references committed +system.cpu1.commit.loads 7563008 # Number of loads committed +system.cpu1.commit.membars 191164 # Number of memory barriers committed +system.cpu1.commit.branches 4749934 # Number of branches committed +system.cpu1.commit.fp_insts 4747 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33512913 # Number of committed integer instructions. +system.cpu1.commit.function_calls 476869 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1375292 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 118557028 # The number of ROB reads -system.cpu1.rob.rob_writes 97285221 # The number of ROB writes -system.cpu1.timesIdled 872406 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159552893 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2285658129 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 28790724 # Number of Instructions Simulated -system.cpu1.committedOps 37431247 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 28790724 # Number of Instructions Simulated -system.cpu1.cpi 8.136122 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.136122 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.122909 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.122909 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 267548470 # number of integer regfile reads -system.cpu1.int_regfile_writes 42457075 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22098 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19630 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14600215 # number of misc regfile reads -system.cpu1.misc_regfile_writes 398004 # number of misc regfile writes +system.cpu1.rob.rob_reads 119137293 # The number of ROB reads +system.cpu1.rob.rob_writes 98065994 # The number of ROB writes +system.cpu1.timesIdled 872405 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159368904 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2285729995 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 29069095 # Number of Instructions Simulated +system.cpu1.committedOps 37681251 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 29069095 # Number of Instructions Simulated +system.cpu1.cpi 8.059775 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.059775 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.124073 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.124073 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 268846383 # number of integer regfile reads +system.cpu1.int_regfile_writes 42770958 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22164 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19740 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14685681 # number of misc regfile reads +system.cpu1.misc_regfile_writes 402240 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1642,17 +1642,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192831582801 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1192831582801 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192831582801 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1192831582801 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192848371945 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1192848371945 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192848371945 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1192848371945 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83052 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83051 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |