diff options
| author | Steve Reinhardt <stever@gmail.com> | 2009-04-22 01:55:52 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2009-04-22 01:55:52 -0400 |
| commit | 7b40c36fbd1c348e5ef43231325923aae1cd0809 (patch) | |
| tree | b1d142d10229a7ca68eff864aa9aae672230e41a /tests/long | |
| parent | 6629d9b2bc58a885bfebce1517fd12483497b6e4 (diff) | |
| download | gem5-7b40c36fbd1c348e5ef43231325923aae1cd0809.tar.xz | |
Update stats for new single bad-address responder.
Mostly just config.ini updates, though the different response
latency for bad addresses caused very minor timing changes
in the O3 Linux boot tests.
Diffstat (limited to 'tests/long')
106 files changed, 1187 insertions, 1329 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index a28c57257..96f36a5ca 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -104,11 +104,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -277,11 +276,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -313,11 +311,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -356,12 +353,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/gzip +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index 45435b4fd..9ba264ef1 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 14 2009 23:40:03 -M5 revision 4208b24ee3ad 6033 default qtip tip new-thread-status-stats-update -M5 started Apr 14 2009 23:40:05 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 17:09:58 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 5e89094d1..090a41f44 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 252050 # Simulator instruction rate (inst/s) -host_mem_usage 207828 # Number of bytes of host memory used -host_seconds 2243.81 # Real time elapsed on the host -host_tick_rate 74461791 # Simulator tick rate (ticks/s) +host_inst_rate 211142 # Simulator instruction rate (inst/s) +host_mem_usage 204372 # Number of bytes of host memory used +host_seconds 2678.54 # Real time elapsed on the host +host_tick_rate 62376647 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated sim_seconds 0.167078 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout index 512d13649..760b4567a 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:34:49 -M5 executing on maize +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:39:08 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt index aa16ad6b4..ecc08006d 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 5975527 # Simulator instruction rate (inst/s) -host_mem_usage 197448 # Number of bytes of host memory used -host_seconds 100.72 # Real time elapsed on the host -host_tick_rate 2987780856 # Simulator tick rate (ticks/s) +host_inst_rate 3845310 # Simulator instruction rate (inst/s) +host_mem_usage 195720 # Number of bytes of host memory used +host_seconds 156.52 # Real time elapsed on the host +host_tick_rate 1922667398 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.300931 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index b0f992d6d..014dd0eae 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -40,11 +40,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -76,11 +75,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -112,11 +110,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout index 20994514f..3f5339a48 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:34:42 -M5 executing on maize +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 17:10:28 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index d4bd93848..c10711f5d 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3011769 # Simulator instruction rate (inst/s) -host_mem_usage 204988 # Number of bytes of host memory used -host_seconds 199.84 # Real time elapsed on the host -host_tick_rate 3893225431 # Simulator tick rate (ticks/s) +host_inst_rate 1860782 # Simulator instruction rate (inst/s) +host_mem_usage 203344 # Number of bytes of host memory used +host_seconds 323.44 # Real time elapsed on the host +host_tick_rate 2405379783 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.778004 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 4fb648418..b155134f9 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -104,11 +104,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -277,11 +276,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -313,11 +311,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -356,12 +353,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing +cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/gzip +executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index 6ef7c085b..42dccffd2 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 14 2009 21:09:22 -M5 revision 4208b24ee3ad 6033 default qtip tip new-thread-status-stats-update -M5 started Apr 14 2009 23:40:01 -M5 executing on phenom -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing +M5 compiled Apr 21 2009 18:04:32 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 18:17:54 +M5 executing on zizzer +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index cec6a0403..7ce31fb30 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 120324 # Simulator instruction rate (inst/s) -host_mem_usage 213384 # Number of bytes of host memory used -host_seconds 11681.98 # Real time elapsed on the host -host_tick_rate 94389741 # Simulator tick rate (ticks/s) +host_inst_rate 110757 # Simulator instruction rate (inst/s) +host_mem_usage 206360 # Number of bytes of host memory used +host_seconds 12690.99 # Real time elapsed on the host +host_tick_rate 86885218 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1405618365 # Number of instructions simulated sim_seconds 1.102659 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout index 2a36b7985..c6ea04920 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:31:00 -M5 executing on maize +M5 compiled Apr 21 2009 18:04:32 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 18:04:58 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt index 077429fb4..99ed606e5 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3659022 # Simulator instruction rate (inst/s) -host_mem_usage 199544 # Number of bytes of host memory used -host_seconds 407.08 # Real time elapsed on the host -host_tick_rate 1829515892 # Simulator tick rate (ticks/s) +host_inst_rate 2585505 # Simulator instruction rate (inst/s) +host_mem_usage 197792 # Number of bytes of host memory used +host_seconds 576.11 # Real time elapsed on the host +host_tick_rate 1292756549 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated sim_seconds 0.744764 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index 7de5a10fa..2b302db2e 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -40,11 +40,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -76,11 +75,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -112,11 +110,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout index 73072ad1d..87c6b0d93 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:32:24 -M5 executing on maize +M5 compiled Apr 21 2009 18:04:32 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 18:13:21 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt index f480451f2..2bdd6d4c0 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1898996 # Simulator instruction rate (inst/s) -host_mem_usage 207084 # Number of bytes of host memory used -host_seconds 784.37 # Real time elapsed on the host -host_tick_rate 2646697045 # Simulator tick rate (ticks/s) +host_inst_rate 1263053 # Simulator instruction rate (inst/s) +host_mem_usage 205412 # Number of bytes of host memory used +host_seconds 1179.30 # Real time elapsed on the host +host_tick_rate 1760361196 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated sim_seconds 2.076001 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout index 7edeeca7b..86ee4acee 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 12 2009 13:26:17 -M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch -M5 started Apr 12 2009 13:32:20 -M5 executing on tater +M5 compiled Apr 21 2009 19:00:07 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 19:00:32 +M5 executing on zizzer command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt index 47ae4ef00..f2c9a60d4 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1453243 # Simulator instruction rate (inst/s) -host_mem_usage 197380 # Number of bytes of host memory used -host_seconds 1114.31 # Real time elapsed on the host -host_tick_rate 864146267 # Simulator tick rate (ticks/s) +host_inst_rate 2698152 # Simulator instruction rate (inst/s) +host_mem_usage 198060 # Number of bytes of host memory used +host_seconds 600.18 # Real time elapsed on the host +host_tick_rate 1604410387 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1619365954 # Number of instructions simulated sim_seconds 0.962929 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini index 3764c63b0..033ea4c68 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -40,11 +40,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -76,11 +75,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -112,11 +110,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index 6282dd2c2..852b3d501 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 12 2009 13:26:17 -M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch -M5 started Apr 12 2009 13:31:26 -M5 executing on tater +M5 compiled Apr 21 2009 19:00:07 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 19:10:33 +M5 executing on zizzer command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index fd5733aad..88ced5522 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 995738 # Simulator instruction rate (inst/s) -host_mem_usage 205000 # Number of bytes of host memory used -host_seconds 1626.30 # Real time elapsed on the host -host_tick_rate 1115968300 # Simulator tick rate (ticks/s) +host_inst_rate 1809758 # Simulator instruction rate (inst/s) +host_mem_usage 205688 # Number of bytes of host memory used +host_seconds 894.80 # Real time elapsed on the host +host_tick_rate 2028277640 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1619365954 # Number of instructions simulated sim_seconds 1.814897 # Number of seconds simulated diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index e37ceeeed..7a3c73d3d 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -130,11 +130,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -303,11 +302,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -437,11 +435,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -610,11 +607,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -704,14 +700,13 @@ port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio syst [system.iocache] type=BaseCache -addr_range=0:18446744073709551615 +addr_range=0:8589934591 assoc=8 block_size=64 -cpu_side_filter_ranges=549755813888:18446744073709551615 +forward_snoops=false hash_delay=1 latency=50000 max_miss_count=0 -mem_side_filter_ranges=0:18446744073709551615 mshrs=20 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -739,11 +734,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=8 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=92 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -768,20 +762,20 @@ mem_side=system.membus.port[3] [system.membus] type=Bus -children=responder +children=badaddr_responder block_size=64 bus_id=1 clock=1000 header_cycles=1 responder_set=false width=64 -default=system.membus.responder.pio +default=system.membus.badaddr_responder.pio port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side -[system.membus.responder] +[system.membus.badaddr_responder] type=IsaFake pio_addr=0 -pio_latency=1 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -824,32 +818,14 @@ port=3456 [system.toL2Bus] type=Bus -children=responder block_size=64 bus_id=0 clock=1000 header_cycles=1 responder_set=false width=64 -default=system.toL2Bus.responder.pio port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side -[system.toL2Bus.responder] -type=IsaFake -pio_addr=0 -pio_latency=1 -pio_size=8 -platform=system.tsunami -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.toL2Bus.default - [system.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 5616a9db3..41fbd38b3 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:30:05 -M5 executing on maize +M5 compiled Apr 21 2009 17:45:48 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 17:52:26 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 00fb3cdfd..fe62d358c 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,36 +1,36 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 198409 # Simulator instruction rate (inst/s) -host_mem_usage 296696 # Number of bytes of host memory used -host_seconds 283.21 # Real time elapsed on the host -host_tick_rate 6736112914 # Simulator tick rate (ticks/s) +host_inst_rate 130489 # Simulator instruction rate (inst/s) +host_mem_usage 295320 # Number of bytes of host memory used +host_seconds 430.62 # Real time elapsed on the host +host_tick_rate 4430183157 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 56190549 # Number of instructions simulated sim_seconds 1.907705 # Number of seconds simulated sim_ticks 1907705384500 # Number of ticks simulated system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.BTBHits 4976196 # Number of BTB hits -system.cpu0.BPredUnit.BTBLookups 9270308 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 4976194 # Number of BTB hits +system.cpu0.BPredUnit.BTBLookups 9270305 # Number of BTB lookups system.cpu0.BPredUnit.RASInCorrect 24350 # Number of incorrect RAS predictions. system.cpu0.BPredUnit.condIncorrect 550496 # Number of conditional branches incorrect -system.cpu0.BPredUnit.condPredicted 8475186 # Number of conditional branches predicted -system.cpu0.BPredUnit.lookups 10093436 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 8475185 # Number of conditional branches predicted +system.cpu0.BPredUnit.lookups 10093433 # Number of BP lookups system.cpu0.BPredUnit.usedRAS 690374 # Number of times the RAS was used to get a target. system.cpu0.commit.COM:branches 5979895 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 670394 # number cycles where commit BW limit reached +system.cpu0.commit.COM:bw_lim_events 670392 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu0.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle.samples 69432721 +system.cpu0.commit.COM:committed_per_cycle.samples 69432713 system.cpu0.commit.COM:committed_per_cycle.min_value 0 - 0 52134013 7508.57% - 1 7662361 1103.57% - 2 4443978 640.04% - 3 2023859 291.48% + 0 52133999 7508.56% + 1 7662367 1103.57% + 2 4443977 640.04% + 3 2023862 291.49% 4 1473823 212.27% - 5 453847 65.37% - 6 276435 39.81% - 7 294011 42.34% - 8 670394 96.55% + 5 453845 65.36% + 6 276436 39.81% + 7 294012 42.34% + 8 670392 96.55% system.cpu0.commit.COM:committed_per_cycle.max_value 8 system.cpu0.commit.COM:committed_per_cycle.end_dist @@ -42,7 +42,7 @@ system.cpu0.commit.COM:swp_count 0 # Nu system.cpu0.commit.branchMispredicts 524450 # The number of times a branch was mispredicted system.cpu0.commit.commitCommittedInsts 39866260 # The number of committed instructions system.cpu0.commit.commitNonSpecStalls 458375 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 6218747 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 6218733 # The number of squashed insts skipped by commit system.cpu0.committedInsts 37660679 # Number of Instructions Simulated system.cpu0.committedInsts_total 37660679 # Number of Instructions Simulated system.cpu0.cpi 2.679241 # CPI: Cycles Per Instruction @@ -58,97 +58,97 @@ system.cpu0.dcache.LoadLockedReq_mshr_hits 3210 # system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 109971000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.062680 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_misses 9257 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses 6414696 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 28975.378056 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 28716.351233 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_accesses 6414671 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 28975.322669 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 28717.577320 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits 5468142 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 27426760000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.147560 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 946554 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 250845 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 19978224000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.108455 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_hits 5468114 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 27426794500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.147561 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 946557 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 250848 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 19979077000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.108456 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_misses 695709 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 639862500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_accesses 156551 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency 54667.977283 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51667.977283 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency 54668.039693 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51668.039693 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_hits 140528 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 875945000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency 875946000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_rate 0.102350 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_misses 16023 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 827876000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 827877000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.102350 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_misses 16023 # number of StoreCondReq MSHR misses system.cpu0.dcache.WriteReq_accesses 4258061 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 48857.574152 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53930.516019 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency 48857.609099 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53930.542507 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_hits 2612712 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 80387760774 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency 80387818274 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_rate 0.386408 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_misses 1645349 # number of WriteReq misses system.cpu0.dcache.WriteReq_mshr_hits 1362208 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 15269940236 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency 15269947736 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_rate 0.066495 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_misses 283141 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1050786497 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.avg_blocked_cycles_no_mshrs 9307.072518 # average number of cycles each access was blocked +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1050789497 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles_no_mshrs 9307.081114 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles_no_targets 16250 # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 9.224260 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 9.224233 # Average number of references to valid blocks. system.cpu0.dcache.blocked_no_mshrs 116343 # number of cycles access was blocked system.cpu0.dcache.blocked_no_targets 2 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_mshrs 1082812738 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 1082813738 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_targets 32500 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 10672757 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 41596.664989 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 36009.770890 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 8080854 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 107814520774 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.242852 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 2591903 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 1613053 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 35248164236 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_accesses 10672732 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 41596.652338 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 36010.649983 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 8080826 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 107814612774 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.242853 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 2591906 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 1613056 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 35249024736 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_rate 0.091715 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_misses 978850 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 10672757 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 41596.664989 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 36009.770890 # average overall mshr miss latency +system.cpu0.dcache.overall_accesses 10672732 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 41596.652338 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 36010.649983 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 8080854 # number of overall hits -system.cpu0.dcache.overall_miss_latency 107814520774 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.242852 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 2591903 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 1613053 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 35248164236 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_hits 8080826 # number of overall hits +system.cpu0.dcache.overall_miss_latency 107814612774 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.242853 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 2591906 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 1613056 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 35249024736 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_rate 0.091715 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_misses 978850 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 1690648997 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency 1690651997 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.dcache.replacements 922726 # number of replacements system.cpu0.dcache.sampled_refs 923123 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.dcache.tagsinuse 442.178159 # Cycle average of tags in use -system.cpu0.dcache.total_refs 8515127 # Total number of references to valid blocks. +system.cpu0.dcache.total_refs 8515102 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 297339 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 33638498 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:BlockedCycles 33638519 # Number of cycles decode is blocked system.cpu0.decode.DECODE:BranchMispred 26518 # Number of times decode detected a branch misprediction -system.cpu0.decode.DECODE:BranchResolved 401379 # Number of times decode resolved a branch -system.cpu0.decode.DECODE:DecodedInsts 50930127 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 25726100 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 9143957 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 1094068 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:BranchResolved 401378 # Number of times decode resolved a branch +system.cpu0.decode.DECODE:DecodedInsts 50930123 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 25726073 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 9143955 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 1094070 # Number of cycles decode is squashing system.cpu0.decode.DECODE:SquashedInsts 84180 # Number of squashed instructions handled by decode system.cpu0.decode.DECODE:UnblockCycles 924165 # Number of cycles decode is unblocking system.cpu0.dtb.data_accesses 812672 # DTB accesses system.cpu0.dtb.data_acv 801 # DTB access violations -system.cpu0.dtb.data_hits 11625470 # DTB hits +system.cpu0.dtb.data_hits 11625422 # DTB hits system.cpu0.dtb.data_misses 28525 # DTB misses system.cpu0.dtb.fetch_accesses 0 # ITB accesses system.cpu0.dtb.fetch_acv 0 # ITB acv @@ -156,81 +156,81 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.read_accesses 605265 # DTB read accesses system.cpu0.dtb.read_acv 596 # DTB read access violations -system.cpu0.dtb.read_hits 7063685 # DTB read hits +system.cpu0.dtb.read_hits 7063658 # DTB read hits system.cpu0.dtb.read_misses 24056 # DTB read misses system.cpu0.dtb.write_accesses 207407 # DTB write accesses system.cpu0.dtb.write_acv 205 # DTB write access violations -system.cpu0.dtb.write_hits 4561785 # DTB write hits +system.cpu0.dtb.write_hits 4561764 # DTB write hits system.cpu0.dtb.write_misses 4469 # DTB write misses -system.cpu0.fetch.Branches 10093436 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 6456939 # Number of cache lines fetched -system.cpu0.fetch.Cycles 16710993 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 292607 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 52006564 # Number of instructions fetch has processed -system.cpu0.fetch.MiscStallCycles 345 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.SquashCycles 660338 # Number of cycles fetch has spent squashing +system.cpu0.fetch.Branches 10093433 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 6456937 # Number of cache lines fetched +system.cpu0.fetch.Cycles 16710986 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 292610 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 52006541 # Number of instructions fetch has processed +system.cpu0.fetch.MiscStallCycles 347 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.SquashCycles 660337 # Number of cycles fetch has spent squashing system.cpu0.fetch.branchRate 0.100032 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 6456939 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 5666570 # Number of branches that fetch has predicted taken +system.cpu0.fetch.icacheStallCycles 6456937 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 5666568 # Number of branches that fetch has predicted taken system.cpu0.fetch.rate 0.515416 # Number of inst fetches per cycle system.cpu0.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist.samples 70526789 +system.cpu0.fetch.rateDist.samples 70526783 system.cpu0.fetch.rateDist.min_value 0 - 0 60303520 8550.44% - 1 761818 108.02% - 2 1433854 203.31% - 3 636079 90.19% - 4 2329702 330.33% + 0 60303519 8550.44% + 1 761816 108.02% + 2 1433855 203.31% + 3 636077 90.19% + 4 2329701 330.33% 5 474692 67.31% - 6 552513 78.34% - 7 815433 115.62% - 8 3219178 456.45% + 6 552515 78.34% + 7 815434 115.62% + 8 3219174 456.45% system.cpu0.fetch.rateDist.max_value 8 system.cpu0.fetch.rateDist.end_dist -system.cpu0.icache.ReadReq_accesses 6456939 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 15194.131269 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.657762 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 5806696 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 9879877499 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_accesses 6456937 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 15194.125887 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.650508 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 5806694 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 9879873999 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_rate 0.100705 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_misses 650243 # number of ReadReq misses system.cpu0.icache.ReadReq_mshr_hits 29877 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 7526067999 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency 7526063499 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate 0.096077 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_misses 620366 # number of ReadReq MSHR misses system.cpu0.icache.avg_blocked_cycles_no_mshrs 11808.794118 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 9.361637 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 9.361634 # Average number of references to valid blocks. system.cpu0.icache.blocked_no_mshrs 34 # number of cycles access was blocked system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_mshrs 401499 # number of cycles access was blocked system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 6456939 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 15194.131269 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 12131.657762 # average overall mshr miss latency -system.cpu0.icache.demand_hits 5806696 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 9879877499 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_accesses 6456937 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 15194.125887 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 12131.650508 # average overall mshr miss latency +system.cpu0.icache.demand_hits 5806694 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 9879873999 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_rate 0.100705 # miss rate for demand accesses system.cpu0.icache.demand_misses 650243 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 29877 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 7526067999 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 7526063499 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_rate 0.096077 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_misses 620366 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 6456939 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 15194.131269 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 12131.657762 # average overall mshr miss latency +system.cpu0.icache.overall_accesses 6456937 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 15194.125887 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12131.650508 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 5806696 # number of overall hits -system.cpu0.icache.overall_miss_latency 9879877499 # number of overall miss cycles +system.cpu0.icache.overall_hits 5806694 # number of overall hits +system.cpu0.icache.overall_miss_latency 9879873999 # number of overall miss cycles system.cpu0.icache.overall_miss_rate 0.100705 # miss rate for overall accesses system.cpu0.icache.overall_misses 650243 # number of overall misses system.cpu0.icache.overall_mshr_hits 29877 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 7526067999 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 7526063499 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_rate 0.096077 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_misses 620366 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -239,58 +239,58 @@ system.cpu0.icache.replacements 619753 # nu system.cpu0.icache.sampled_refs 620265 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.tagsinuse 509.829037 # Cycle average of tags in use -system.cpu0.icache.total_refs 5806696 # Total number of references to valid blocks. +system.cpu0.icache.total_refs 5806694 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 25308080000 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idleCycles 30375232 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.EXEC:branches 6436271 # Number of branches executed -system.cpu0.iew.EXEC:nop 2512861 # number of nop insts executed -system.cpu0.iew.EXEC:rate 0.402649 # Inst execution rate -system.cpu0.iew.EXEC:refs 11740634 # number of memory reference insts executed -system.cpu0.iew.EXEC:stores 4575971 # Number of stores executed +system.cpu0.idleCycles 30375240 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 6436261 # Number of branches executed +system.cpu0.iew.EXEC:nop 2512857 # number of nop insts executed +system.cpu0.iew.EXEC:rate 0.402648 # Inst execution rate +system.cpu0.iew.EXEC:refs 11740586 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 4575950 # Number of stores executed system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 24161361 # num instructions consuming a value -system.cpu0.iew.WB:count 40226140 # cumulative count of insts written-back +system.cpu0.iew.WB:consumers 24161341 # num instructions consuming a value +system.cpu0.iew.WB:count 40226053 # cumulative count of insts written-back system.cpu0.iew.WB:fanout 0.779058 # average fanout of values written-back system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 18823101 # num instructions producing a value -system.cpu0.iew.WB:rate 0.398665 # insts written-back per cycle -system.cpu0.iew.WB:sent 40293974 # cumulative count of insts sent to commit +system.cpu0.iew.WB:producers 18823082 # num instructions producing a value +system.cpu0.iew.WB:rate 0.398664 # insts written-back per cycle +system.cpu0.iew.WB:sent 40293911 # cumulative count of insts sent to commit system.cpu0.iew.branchMispredicts 568843 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewBlockCycles 7178022 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 7553751 # Number of dispatched load instructions +system.cpu0.iew.iewBlockCycles 7178019 # Number of cycles IEW is blocking +system.cpu0.iew.iewDispLoadInsts 7553743 # Number of dispatched load instructions system.cpu0.iew.iewDispNonSpecInsts 1229599 # Number of dispatched non-speculative instructions system.cpu0.iew.iewDispSquashedInsts 771955 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 4835994 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 46191067 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 7164663 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 359395 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 40628051 # Number of executed instructions -system.cpu0.iew.iewIQFullEvents 33755 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewDispStoreInsts 4836003 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 46191057 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 7164636 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 359402 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 40627967 # Number of executed instructions +system.cpu0.iew.iewIQFullEvents 33758 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu0.iew.iewLSQFullEvents 4184 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 1094068 # Number of cycles IEW is squashing -system.cpu0.iew.iewUnblockCycles 453365 # Number of cycles IEW is unblocking +system.cpu0.iew.iewSquashCycles 1094070 # Number of cycles IEW is squashing +system.cpu0.iew.iewUnblockCycles 453368 # Number of cycles IEW is unblocking system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread.0.cacheBlocked 243041 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.lsq.thread.0.forwLoads 357779 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread.0.ignoredResponses 8886 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 34084 # Number of memory ordering violations -system.cpu0.iew.lsq.thread.0.rescheduledLoads 12238 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 1149277 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 408828 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 34084 # Number of memory order violations +system.cpu0.iew.lsq.thread.0.memOrderViolation 34087 # Number of memory ordering violations +system.cpu0.iew.lsq.thread.0.rescheduledLoads 12236 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread.0.squashedLoads 1149269 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 408837 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 34087 # Number of memory order violations system.cpu0.iew.predictedNotTakenIncorrect 255799 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.predictedTakenIncorrect 313044 # Number of branches that were predicted taken incorrectly system.cpu0.ipc 0.373240 # IPC: Instructions Per Cycle system.cpu0.ipc_total 0.373240 # IPC: Total IPC of All Threads -system.cpu0.iq.ISSUE:FU_type_0 40987446 # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0 40987369 # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0.start_dist No_OpClass 3326 0.01% # Type of FU issued - IntAlu 28267902 68.97% # Type of FU issued + IntAlu 28267868 68.97% # Type of FU issued IntMult 42211 0.10% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 12076 0.03% # Type of FU issued @@ -299,12 +299,12 @@ system.cpu0.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 1657 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 7398183 18.05% # Type of FU issued - MemWrite 4612040 11.25% # Type of FU issued + MemRead 7398159 18.05% # Type of FU issued + MemWrite 4612021 11.25% # Type of FU issued IprAccess 650051 1.59% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0.end_dist -system.cpu0.iq.ISSUE:fu_busy_cnt 290461 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_cnt 290458 # FU busy when requested system.cpu0.iq.ISSUE:fu_busy_rate 0.007087 # FU busy rate (busy events/executed inst) system.cpu0.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available @@ -317,36 +317,36 @@ system.cpu0.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 185625 63.91% # attempts to use FU when none available - MemWrite 71334 24.56% # attempts to use FU when none available + MemRead 185621 63.91% # attempts to use FU when none available + MemWrite 71335 24.56% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full.end_dist -system.cpu0.iq.ISSUE:issued_per_cycle::samples 70526789 +system.cpu0.iq.ISSUE:issued_per_cycle::samples 70526783 system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu0.iq.ISSUE:issued_per_cycle::0-1 49764698 70.56% -system.cpu0.iq.ISSUE:issued_per_cycle::1-2 10507711 14.90% -system.cpu0.iq.ISSUE:issued_per_cycle::2-3 4625293 6.56% -system.cpu0.iq.ISSUE:issued_per_cycle::3-4 2839060 4.03% -system.cpu0.iq.ISSUE:issued_per_cycle::4-5 1729945 2.45% -system.cpu0.iq.ISSUE:issued_per_cycle::5-6 663621 0.94% -system.cpu0.iq.ISSUE:issued_per_cycle::6-7 315226 0.45% -system.cpu0.iq.ISSUE:issued_per_cycle::7-8 67152 0.10% -system.cpu0.iq.ISSUE:issued_per_cycle::8 14083 0.02% +system.cpu0.iq.ISSUE:issued_per_cycle::0-1 49764700 70.56% +system.cpu0.iq.ISSUE:issued_per_cycle::1-2 10507721 14.90% +system.cpu0.iq.ISSUE:issued_per_cycle::2-3 4625277 6.56% +system.cpu0.iq.ISSUE:issued_per_cycle::3-4 2839073 4.03% +system.cpu0.iq.ISSUE:issued_per_cycle::4-5 1729944 2.45% +system.cpu0.iq.ISSUE:issued_per_cycle::5-6 663617 0.94% +system.cpu0.iq.ISSUE:issued_per_cycle::6-7 315224 0.45% +system.cpu0.iq.ISSUE:issued_per_cycle::7-8 67146 0.10% +system.cpu0.iq.ISSUE:issued_per_cycle::8 14081 0.02% system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu0.iq.ISSUE:issued_per_cycle::total 70526789 +system.cpu0.iq.ISSUE:issued_per_cycle::total 70526783 system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.581161 -system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.133095 +system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.581160 +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.133092 system.cpu0.iq.ISSUE:rate 0.406210 # Inst issue rate -system.cpu0.iq.iqInstsAdded 42280485 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 40987446 # Number of instructions issued +system.cpu0.iq.iqInstsAdded 42280479 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 40987369 # Number of instructions issued system.cpu0.iq.iqNonSpecInstsAdded 1397721 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 5737873 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedInstsIssued 23379 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5737875 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedInstsIssued 23380 # Number of squashed instructions issued system.cpu0.iq.iqSquashedNonSpecRemoved 939346 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 3058467 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedOperandsExamined 3058582 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_hits 0 # DTB hits @@ -397,11 +397,11 @@ system.cpu0.kern.ipl_good_22 1931 2.00% 51.13% # nu system.cpu0.kern.ipl_good_30 17 0.02% 51.14% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_31 47097 48.86% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_ticks 1907288793500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1871606924500 98.13% 98.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1871606920000 98.13% 98.13% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_21 101495000 0.01% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 397995000 0.02% 98.16% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 398001000 0.02% 98.16% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_30 9331000 0.00% 98.16% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 35173048000 1.84% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 35173046500 1.84% 100.00% # number of cycles we spent at this ipl system.cpu0.kern.ipl_used_0 0.986391 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl @@ -451,51 +451,51 @@ system.cpu0.kern.syscall_98 2 0.90% 97.75% # nu system.cpu0.kern.syscall_132 1 0.45% 98.20% # number of syscalls executed system.cpu0.kern.syscall_144 2 0.90% 99.10% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.90% 100.00% # number of syscalls executed -system.cpu0.memDep0.conflictingLoads 2050532 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1832540 # Number of conflicting stores. -system.cpu0.memDep0.insertedLoads 7553751 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 4835994 # Number of stores inserted to the mem dependence unit. -system.cpu0.numCycles 100902021 # number of cpu cycles simulated -system.cpu0.rename.RENAME:BlockCycles 10627682 # Number of cycles rename is blocking +system.cpu0.memDep0.conflictingLoads 2050556 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1832562 # Number of conflicting stores. +system.cpu0.memDep0.insertedLoads 7553743 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 4836003 # Number of stores inserted to the mem dependence unit. +system.cpu0.numCycles 100902023 # number of cpu cycles simulated +system.cpu0.rename.RENAME:BlockCycles 10627685 # Number of cycles rename is blocking system.cpu0.rename.RENAME:CommittedMaps 27337911 # Number of HB maps that are committed -system.cpu0.rename.RENAME:IQFullEvents 742849 # Number of times rename has blocked due to IQ full -system.cpu0.rename.RENAME:IdleCycles 26930411 # Number of cycles rename is idle +system.cpu0.rename.RENAME:IQFullEvents 742850 # Number of times rename has blocked due to IQ full +system.cpu0.rename.RENAME:IdleCycles 26930386 # Number of cycles rename is idle system.cpu0.rename.RENAME:LSQFullEvents 1646609 # Number of times rename has blocked due to LSQ full system.cpu0.rename.RENAME:ROBFullEvents 16617 # Number of times rename has blocked due to ROB full -system.cpu0.rename.RENAME:RenameLookups 58880309 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 48158423 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 32535865 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 9104795 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 1094068 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 3612727 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 5197954 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:serializeStallCycles 19157104 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:RenameLookups 58880297 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 48158408 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 32535845 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 9104791 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 1094070 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 3612728 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 5197934 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:serializeStallCycles 19157121 # count of cycles rename stalled for serializing inst system.cpu0.rename.RENAME:serializingInsts 1163461 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 8536821 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:skidInsts 8536823 # count of insts added to the skid buffer system.cpu0.rename.RENAME:tempSerializingInsts 181475 # count of temporary serializing insts renamed -system.cpu0.timesIdled 904725 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.timesIdled 904727 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.BTBHits 2271370 # Number of BTB hits -system.cpu1.BPredUnit.BTBLookups 5052293 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 2271371 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 5052294 # Number of BTB lookups system.cpu1.BPredUnit.RASInCorrect 16405 # Number of incorrect RAS predictions. system.cpu1.BPredUnit.condIncorrect 327507 # Number of conditional branches incorrect system.cpu1.BPredUnit.condPredicted 4551940 # Number of conditional branches predicted system.cpu1.BPredUnit.lookups 5538388 # Number of BP lookups -system.cpu1.BPredUnit.usedRAS 417429 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.usedRAS 417428 # Number of times the RAS was used to get a target. system.cpu1.commit.COM:branches 2947825 # Number of branches committed system.cpu1.commit.COM:bw_lim_events 401526 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu1.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle.samples 37477455 +system.cpu1.commit.COM:committed_per_cycle.samples 37477420 system.cpu1.commit.COM:committed_per_cycle.min_value 0 - 0 29419466 7849.91% - 1 3577484 954.57% + 0 29419430 7849.91% + 1 3577485 954.57% 2 1728132 461.11% - 3 1049888 280.14% - 4 708571 189.07% - 5 265965 70.97% + 3 1049887 280.14% + 4 708572 189.07% + 5 265966 70.97% 6 180885 48.27% - 7 145538 38.83% + 7 145537 38.83% 8 401526 107.14% system.cpu1.commit.COM:committed_per_cycle.max_value 8 system.cpu1.commit.COM:committed_per_cycle.end_dist @@ -508,7 +508,7 @@ system.cpu1.commit.COM:swp_count 0 # Nu system.cpu1.commit.branchMispredicts 311117 # The number of times a branch was mispredicted system.cpu1.commit.commitCommittedInsts 19663805 # The number of committed instructions system.cpu1.commit.commitNonSpecStalls 255745 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 3736987 # The number of squashed insts skipped by commit +system.cpu1.commit.commitSquashedInsts 3737019 # The number of squashed insts skipped by commit system.cpu1.committedInsts 18529870 # Number of Instructions Simulated system.cpu1.committedInsts_total 18529870 # Number of Instructions Simulated system.cpu1.cpi 2.312190 # CPI: Cycles Per Instruction @@ -524,19 +524,19 @@ system.cpu1.dcache.LoadLockedReq_mshr_hits 2016 # system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 115024000 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.142362 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_misses 10268 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses 3589521 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 15546.334532 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11998.783257 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_accesses 3589394 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 15546.336868 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12022.349090 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits 2947311 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 9984011500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.178912 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_hits 2947184 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 9984013000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.178919 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_misses 642210 # number of ReadReq misses system.cpu1.dcache.ReadReq_mshr_hits 211141 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 5172303500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.120091 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_latency 5182462000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.120095 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_misses 431069 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 298579500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 298578500 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.StoreCondReq_accesses 68169 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_avg_miss_latency 54676.100066 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 51676.100066 # average StoreCondReq mshr miss latency @@ -548,73 +548,73 @@ system.cpu1.dcache.StoreCondReq_mshr_miss_latency 865523000 system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.245698 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_misses 16749 # number of StoreCondReq MSHR misses system.cpu1.dcache.WriteReq_accesses 2234886 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 49366.448141 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54247.795546 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency 49366.459666 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54247.809571 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.WriteReq_hits 1540754 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 34266831381 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency 34266839381 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_rate 0.310589 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_misses 694132 # number of WriteReq misses system.cpu1.dcache.WriteReq_mshr_hits 551528 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 7735952636 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 7735954636 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_rate 0.063808 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_misses 142604 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 526042500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 526038500 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.avg_blocked_cycles_no_mshrs 13994.026145 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles_no_targets 5000 # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 8.879315 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 8.879077 # Average number of references to valid blocks. system.cpu1.dcache.blocked_no_mshrs 31364 # number of cycles access was blocked system.cpu1.dcache.blocked_no_targets 1 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles_no_mshrs 438908636 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles_no_targets 5000 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 5824407 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 33113.411747 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 22501.069662 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 4488065 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 44250842881 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.229438 # miss rate for demand accesses +system.cpu1.dcache.demand_accesses 5824280 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 33113.418856 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 22518.780971 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 4487938 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 44250852381 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.229443 # miss rate for demand accesses system.cpu1.dcache.demand_misses 1336342 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 762669 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 12908256136 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.098495 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_latency 12918416636 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.098497 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_misses 573673 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.overall_accesses 5824407 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 33113.411747 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 22501.069662 # average overall mshr miss latency +system.cpu1.dcache.overall_accesses 5824280 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 33113.418856 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 22518.780971 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 4488065 # number of overall hits -system.cpu1.dcache.overall_miss_latency 44250842881 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.229438 # miss rate for overall accesses +system.cpu1.dcache.overall_hits 4487938 # number of overall hits +system.cpu1.dcache.overall_miss_latency 44250852381 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.229443 # miss rate for overall accesses system.cpu1.dcache.overall_misses 1336342 # number of overall misses system.cpu1.dcache.overall_mshr_hits 762669 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 12908256136 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.098495 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_latency 12918416636 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.098497 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_misses 573673 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 824622000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency 824617000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.dcache.replacements 531784 # number of replacements system.cpu1.dcache.sampled_refs 532296 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.dcache.tagsinuse 487.083551 # Cycle average of tags in use -system.cpu1.dcache.total_refs 4726424 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 39405721000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.total_refs 4726297 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 39405720000 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 158239 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 17789626 # Number of cycles decode is blocked +system.cpu1.decode.DECODE:BlockedCycles 17789619 # Number of cycles decode is blocked system.cpu1.decode.DECODE:BranchMispred 18017 # Number of times decode detected a branch misprediction -system.cpu1.decode.DECODE:BranchResolved 246498 # Number of times decode resolved a branch -system.cpu1.decode.DECODE:DecodedInsts 26253438 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 14731458 # Number of cycles decode is idle -system.cpu1.decode.DECODE:RunCycles 4724229 # Number of cycles decode is running -system.cpu1.decode.DECODE:SquashCycles 641522 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:BranchResolved 246499 # Number of times decode resolved a branch +system.cpu1.decode.DECODE:DecodedInsts 26253455 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 14731428 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 4724231 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 641523 # Number of cycles decode is squashing system.cpu1.decode.DECODE:SquashedInsts 52769 # Number of squashed instructions handled by decode system.cpu1.decode.DECODE:UnblockCycles 232141 # Number of cycles decode is unblocking system.cpu1.dtb.data_accesses 433929 # DTB accesses system.cpu1.dtb.data_acv 77 # DTB access violations -system.cpu1.dtb.data_hits 6280849 # DTB hits +system.cpu1.dtb.data_hits 6280304 # DTB hits system.cpu1.dtb.data_misses 17153 # DTB misses system.cpu1.dtb.fetch_accesses 0 # ITB accesses system.cpu1.dtb.fetch_acv 0 # ITB acv @@ -622,47 +622,47 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.read_accesses 314117 # DTB read accesses system.cpu1.dtb.read_acv 13 # DTB read access violations -system.cpu1.dtb.read_hits 3872885 # DTB read hits +system.cpu1.dtb.read_hits 3872751 # DTB read hits system.cpu1.dtb.read_misses 13436 # DTB read misses system.cpu1.dtb.write_accesses 119812 # DTB write accesses system.cpu1.dtb.write_acv 64 # DTB write access violations -system.cpu1.dtb.write_hits 2407964 # DTB write hits +system.cpu1.dtb.write_hits 2407553 # DTB write hits system.cpu1.dtb.write_misses 3717 # DTB write misses system.cpu1.fetch.Branches 5538388 # Number of branches that fetch encountered system.cpu1.fetch.CacheLines 3089103 # Number of cache lines fetched -system.cpu1.fetch.Cycles 8137043 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 192735 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 26826541 # Number of instructions fetch has processed +system.cpu1.fetch.Cycles 8137045 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 192731 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 26826558 # Number of instructions fetch has processed system.cpu1.fetch.MiscStallCycles 1090 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.SquashCycles 373513 # Number of cycles fetch has spent squashing +system.cpu1.fetch.SquashCycles 373512 # Number of cycles fetch has spent squashing system.cpu1.fetch.branchRate 0.129267 # Number of branch fetches per cycle system.cpu1.fetch.icacheStallCycles 3089103 # Number of cycles fetch is stalled on an Icache miss system.cpu1.fetch.predictedBranches 2688799 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 0.626136 # Number of inst fetches per cycle +system.cpu1.fetch.rate 0.626137 # Number of inst fetches per cycle system.cpu1.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist.samples 38118977 +system.cpu1.fetch.rateDist.samples 38118943 system.cpu1.fetch.rateDist.min_value 0 - 0 33077956 8677.56% - 1 338219 88.73% + 0 33077920 8677.55% + 1 338218 88.73% 2 684572 179.59% - 3 401330 105.28% - 4 792380 207.87% - 5 254419 66.74% + 3 401329 105.28% + 4 792382 207.87% + 5 254420 66.74% 6 341251 89.52% 7 404733 106.18% - 8 1824117 478.53% + 8 1824118 478.53% system.cpu1.fetch.rateDist.max_value 8 system.cpu1.fetch.rateDist.end_dist system.cpu1.icache.ReadReq_accesses 3089103 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 14554.963245 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11604.753460 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_miss_latency 14554.957905 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11604.745633 # average ReadReq mshr miss latency system.cpu1.icache.ReadReq_hits 2620972 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 6813629499 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency 6813626999 # number of ReadReq miss cycles system.cpu1.icache.ReadReq_miss_rate 0.151543 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_misses 468131 # number of ReadReq misses system.cpu1.icache.ReadReq_mshr_hits 20962 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 5189286000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency 5189282500 # number of ReadReq MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate 0.144757 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_misses 447169 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles_no_mshrs 11057.692308 # average number of cycles each access was blocked @@ -674,29 +674,29 @@ system.cpu1.icache.blocked_cycles_no_mshrs 287500 # system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.demand_accesses 3089103 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 14554.963245 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11604.753460 # average overall mshr miss latency +system.cpu1.icache.demand_avg_miss_latency 14554.957905 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11604.745633 # average overall mshr miss latency system.cpu1.icache.demand_hits 2620972 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 6813629499 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency 6813626999 # number of demand (read+write) miss cycles system.cpu1.icache.demand_miss_rate 0.151543 # miss rate for demand accesses system.cpu1.icache.demand_misses 468131 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 20962 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 5189286000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 5189282500 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.demand_mshr_miss_rate 0.144757 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_misses 447169 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.overall_accesses 3089103 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 14554.963245 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11604.753460 # average overall mshr miss latency +system.cpu1.icache.overall_avg_miss_latency 14554.957905 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11604.745633 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu1.icache.overall_hits 2620972 # number of overall hits -system.cpu1.icache.overall_miss_latency 6813629499 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency 6813626999 # number of overall miss cycles system.cpu1.icache.overall_miss_rate 0.151543 # miss rate for overall accesses system.cpu1.icache.overall_misses 468131 # number of overall misses system.cpu1.icache.overall_mshr_hits 20962 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 5189286000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 5189282500 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_rate 0.144757 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_misses 447169 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -708,35 +708,35 @@ system.cpu1.icache.tagsinuse 504.476148 # Cy system.cpu1.icache.total_refs 2620972 # Total number of references to valid blocks. system.cpu1.icache.warmup_cycle 54243392000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idleCycles 4725605 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.EXEC:branches 3215748 # Number of branches executed +system.cpu1.idleCycles 4725629 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 3215720 # Number of branches executed system.cpu1.iew.EXEC:nop 1316352 # number of nop insts executed -system.cpu1.iew.EXEC:rate 0.474711 # Inst execution rate -system.cpu1.iew.EXEC:refs 6453696 # number of memory reference insts executed -system.cpu1.iew.EXEC:stores 2419389 # Number of stores executed +system.cpu1.iew.EXEC:rate 0.474690 # Inst execution rate +system.cpu1.iew.EXEC:refs 6453151 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 2418978 # Number of stores executed system.cpu1.iew.EXEC:swp 0 # number of swp insts executed -system.cpu1.iew.WB:consumers 12378269 # num instructions consuming a value -system.cpu1.iew.WB:count 20082329 # cumulative count of insts written-back -system.cpu1.iew.WB:fanout 0.731659 # average fanout of values written-back +system.cpu1.iew.WB:consumers 12377931 # num instructions consuming a value +system.cpu1.iew.WB:count 20081292 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.731656 # average fanout of values written-back system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.WB:producers 9056670 # num instructions producing a value -system.cpu1.iew.WB:rate 0.468725 # insts written-back per cycle -system.cpu1.iew.WB:sent 20124761 # cumulative count of insts sent to commit +system.cpu1.iew.WB:producers 9056386 # num instructions producing a value +system.cpu1.iew.WB:rate 0.468701 # insts written-back per cycle +system.cpu1.iew.WB:sent 20123893 # cumulative count of insts sent to commit system.cpu1.iew.branchMispredicts 338961 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewBlockCycles 2501198 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 4247428 # Number of dispatched load instructions +system.cpu1.iew.iewBlockCycles 2501197 # Number of cycles IEW is blocking +system.cpu1.iew.iewDispLoadInsts 4247431 # Number of dispatched load instructions system.cpu1.iew.iewDispNonSpecInsts 782465 # Number of dispatched non-speculative instructions system.cpu1.iew.iewDispSquashedInsts 352902 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 2557361 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 23476813 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 4034307 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 224585 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 20338799 # Number of executed instructions +system.cpu1.iew.iewDispStoreInsts 2557372 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 23476845 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 4034173 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 224909 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 20337896 # Number of executed instructions system.cpu1.iew.iewIQFullEvents 13271 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu1.iew.iewLSQFullEvents 2314 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 641522 # Number of cycles IEW is squashing +system.cpu1.iew.iewSquashCycles 641523 # Number of cycles IEW is squashing system.cpu1.iew.iewUnblockCycles 92599 # Number of cycles IEW is unblocking system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread.0.cacheBlocked 96430 # Number of times an access to memory failed due to the cache being blocked @@ -744,19 +744,19 @@ system.cpu1.iew.lsq.thread.0.forwLoads 136935 # Nu system.cpu1.iew.lsq.thread.0.ignoredResponses 5812 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 18288 # Number of memory ordering violations -system.cpu1.iew.lsq.thread.0.rescheduledLoads 7650 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 696351 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 246865 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 18288 # Number of memory order violations +system.cpu1.iew.lsq.thread.0.memOrderViolation 18287 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.rescheduledLoads 7643 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread.0.squashedLoads 696354 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 246876 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 18287 # Number of memory order violations system.cpu1.iew.predictedNotTakenIncorrect 160561 # Number of branches that were predicted not taken incorrectly system.cpu1.iew.predictedTakenIncorrect 178400 # Number of branches that were predicted taken incorrectly system.cpu1.ipc 0.432490 # IPC: Instructions Per Cycle system.cpu1.ipc_total 0.432490 # IPC: Total IPC of All Threads -system.cpu1.iq.ISSUE:FU_type_0 20563386 # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0 20562807 # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0.start_dist No_OpClass 3984 0.02% # Type of FU issued - IntAlu 13476321 65.54% # Type of FU issued + IntAlu 13476075 65.54% # Type of FU issued IntMult 28965 0.14% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 13702 0.07% # Type of FU issued @@ -765,13 +765,13 @@ system.cpu1.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 1986 0.01% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 4173926 20.30% # Type of FU issued - MemWrite 2443261 11.88% # Type of FU issued + MemRead 4173782 20.30% # Type of FU issued + MemWrite 2443072 11.88% # Type of FU issued IprAccess 421241 2.05% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0.end_dist -system.cpu1.iq.ISSUE:fu_busy_cnt 221052 # FU busy when requested -system.cpu1.iq.ISSUE:fu_busy_rate 0.010750 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:fu_busy_cnt 221150 # FU busy when requested +system.cpu1.iq.ISSUE:fu_busy_rate 0.010755 # FU busy rate (busy events/executed inst) system.cpu1.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available IntAlu 16139 7.30% # attempts to use FU when none available @@ -783,36 +783,36 @@ system.cpu1.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 131915 59.68% # attempts to use FU when none available - MemWrite 72998 33.02% # attempts to use FU when none available + MemRead 131899 59.64% # attempts to use FU when none available + MemWrite 73112 33.06% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full.end_dist -system.cpu1.iq.ISSUE:issued_per_cycle::samples 38118977 +system.cpu1.iq.ISSUE:issued_per_cycle::samples 38118943 system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu1.iq.ISSUE:issued_per_cycle::0-1 28405823 74.52% -system.cpu1.iq.ISSUE:issued_per_cycle::1-2 4664380 12.24% -system.cpu1.iq.ISSUE:issued_per_cycle::2-3 1989669 5.22% -system.cpu1.iq.ISSUE:issued_per_cycle::3-4 1362790 3.58% -system.cpu1.iq.ISSUE:issued_per_cycle::4-5 979073 2.57% -system.cpu1.iq.ISSUE:issued_per_cycle::5-6 465618 1.22% -system.cpu1.iq.ISSUE:issued_per_cycle::6-7 186895 0.49% -system.cpu1.iq.ISSUE:issued_per_cycle::7-8 52286 0.14% -system.cpu1.iq.ISSUE:issued_per_cycle::8 12443 0.03% +system.cpu1.iq.ISSUE:issued_per_cycle::0-1 28405834 74.52% +system.cpu1.iq.ISSUE:issued_per_cycle::1-2 4664798 12.24% +system.cpu1.iq.ISSUE:issued_per_cycle::2-3 1989487 5.22% +system.cpu1.iq.ISSUE:issued_per_cycle::3-4 1362185 3.57% +system.cpu1.iq.ISSUE:issued_per_cycle::4-5 979454 2.57% +system.cpu1.iq.ISSUE:issued_per_cycle::5-6 465472 1.22% +system.cpu1.iq.ISSUE:issued_per_cycle::6-7 186874 0.49% +system.cpu1.iq.ISSUE:issued_per_cycle::7-8 52652 0.14% +system.cpu1.iq.ISSUE:issued_per_cycle::8 12187 0.03% system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu1.iq.ISSUE:issued_per_cycle::total 38118977 +system.cpu1.iq.ISSUE:issued_per_cycle::total 38118943 system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.539453 -system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.158806 -system.cpu1.iq.ISSUE:rate 0.479953 # Inst issue rate -system.cpu1.iq.iqInstsAdded 21283894 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 20563386 # Number of instructions issued +system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.539438 +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.158785 +system.cpu1.iq.ISSUE:rate 0.479940 # Inst issue rate +system.cpu1.iq.iqInstsAdded 21283926 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 20562807 # Number of instructions issued system.cpu1.iq.iqNonSpecInstsAdded 876567 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 3483485 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedInstsIssued 16725 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 3483517 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedInstsIssued 16728 # Number of squashed instructions issued system.cpu1.iq.iqSquashedNonSpecRemoved 620822 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 1773520 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedOperandsExamined 1775091 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_hits 0 # DTB hits @@ -860,10 +860,10 @@ system.cpu1.kern.ipl_good_22 1928 2.80% 51.40% # nu system.cpu1.kern.ipl_good_30 96 0.14% 51.54% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_31 33320 48.46% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_ticks 1907704531000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 1871986899500 98.13% 98.13% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 352080000 0.02% 98.15% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1871986905500 98.13% 98.13% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 352078000 0.02% 98.15% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_30 40004500 0.00% 98.15% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 35325547000 1.85% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 35325543000 1.85% 100.00% # number of cycles we spent at this ipl system.cpu1.kern.ipl_used_0 0.978707 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl @@ -896,29 +896,29 @@ system.cpu1.kern.syscall_59 1 0.96% 57.69% # nu system.cpu1.kern.syscall_71 31 29.81% 87.50% # number of syscalls executed system.cpu1.kern.syscall_74 10 9.62% 97.12% # number of syscalls executed system.cpu1.kern.syscall_132 3 2.88% 100.00% # number of syscalls executed -system.cpu1.memDep0.conflictingLoads 906322 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 817104 # Number of conflicting stores. -system.cpu1.memDep0.insertedLoads 4247428 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 2557361 # Number of stores inserted to the mem dependence unit. -system.cpu1.numCycles 42844582 # number of cpu cycles simulated -system.cpu1.rename.RENAME:BlockCycles 3655834 # Number of cycles rename is blocking +system.cpu1.memDep0.conflictingLoads 906343 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 817120 # Number of conflicting stores. +system.cpu1.memDep0.insertedLoads 4247431 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 2557372 # Number of stores inserted to the mem dependence unit. +system.cpu1.numCycles 42844572 # number of cpu cycles simulated +system.cpu1.rename.RENAME:BlockCycles 3655833 # Number of cycles rename is blocking system.cpu1.rename.RENAME:CommittedMaps 13191652 # Number of HB maps that are committed system.cpu1.rename.RENAME:IQFullEvents 331503 # Number of times rename has blocked due to IQ full -system.cpu1.rename.RENAME:IdleCycles 15199760 # Number of cycles rename is idle +system.cpu1.rename.RENAME:IdleCycles 15199726 # Number of cycles rename is idle system.cpu1.rename.RENAME:LSQFullEvents 648645 # Number of times rename has blocked due to LSQ full system.cpu1.rename.RENAME:ROBFullEvents 1226 # Number of times rename has blocked due to ROB full -system.cpu1.rename.RENAME:RenameLookups 29419469 # Number of register rename lookups that rename has made -system.cpu1.rename.RENAME:RenamedInsts 24525114 # Number of instructions processed by rename -system.cpu1.rename.RENAME:RenamedOperands 16182590 # Number of destination operands rename has renamed -system.cpu1.rename.RENAME:RunCycles 4333684 # Number of cycles rename is running -system.cpu1.rename.RENAME:SquashCycles 641522 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:RenameLookups 29419521 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 24525143 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 16182603 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 4333690 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 641523 # Number of cycles rename is squashing system.cpu1.rename.RENAME:UnblockCycles 1812010 # Number of cycles rename is unblocking -system.cpu1.rename.RENAME:UndoneMaps 2990936 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:serializeStallCycles 12476165 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:UndoneMaps 2990949 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:serializeStallCycles 12476159 # count of cycles rename stalled for serializing inst system.cpu1.rename.RENAME:serializingInsts 728375 # count of serializing insts renamed system.cpu1.rename.RENAME:skidInsts 4962161 # count of insts added to the skid buffer system.cpu1.rename.RENAME:tempSerializingInsts 86287 # count of temporary serializing insts renamed -system.cpu1.timesIdled 480520 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.timesIdled 480522 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -993,38 +993,38 @@ system.iocache.total_refs 0 # To system.iocache.warmup_cycle 1717170531000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41522 # number of writebacks system.l2c.ReadExReq_accesses 317502 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52375.567080 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40223.034620 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 16629347299 # number of ReadExReq miss cycles +system.l2c.ReadExReq_avg_miss_latency 52375.571804 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40223.037770 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 16629348799 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_misses 317502 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12770893938 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 12770894938 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 317502 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2204255 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 52067.361570 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40026.445360 # average ReadReq mshr miss latency +system.l2c.ReadReq_accesses 2204779 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 51979.602997 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 39977.821348 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_hits 1893900 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16159366000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.140798 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 310355 # number of ReadReq misses +system.l2c.ReadReq_miss_latency 16159367000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.141002 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 310879 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12421727000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.140790 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 310338 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_miss_latency 12427585500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.140995 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 310862 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_uncacheable_latency 840472000 # number of ReadReq MSHR uncacheable cycles system.l2c.UpgradeReq_accesses 141949 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_avg_miss_latency 51066.182164 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.287026 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.290548 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_miss_latency 7248793492 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_misses 141949 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5691202000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 5691202500 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_misses 141949 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1423764498 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1423763998 # number of WriteReq MSHR uncacheable cycles system.l2c.Writeback_accesses 455578 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits 455578 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -1035,38 +1035,38 @@ system.l2c.blocked_no_targets 0 # nu system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2521757 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 52223.218502 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40125.861586 # average overall mshr miss latency +system.l2c.demand_accesses 2522281 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52179.674113 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40101.725175 # average overall mshr miss latency system.l2c.demand_hits 1893900 # number of demand (read+write) hits -system.l2c.demand_miss_latency 32788713299 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.248976 # miss rate for demand accesses -system.l2c.demand_misses 627857 # number of demand (read+write) misses +system.l2c.demand_miss_latency 32788715799 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.249132 # miss rate for demand accesses +system.l2c.demand_misses 628381 # number of demand (read+write) misses system.l2c.demand_mshr_hits 17 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 25192620938 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.248969 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 627840 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 25198480438 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.249125 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 628364 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2521757 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 52223.218502 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40125.861586 # average overall mshr miss latency +system.l2c.overall_accesses 2522281 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52179.674113 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40101.725175 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.l2c.overall_hits 1893900 # number of overall hits -system.l2c.overall_miss_latency 32788713299 # number of overall miss cycles -system.l2c.overall_miss_rate 0.248976 # miss rate for overall accesses -system.l2c.overall_misses 627857 # number of overall misses +system.l2c.overall_miss_latency 32788715799 # number of overall miss cycles +system.l2c.overall_miss_rate 0.249132 # miss rate for overall accesses +system.l2c.overall_misses 628381 # number of overall misses system.l2c.overall_mshr_hits 17 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 25192620938 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.248969 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 627840 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2264236498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 25198480438 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.249125 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 628364 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2264235998 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.replacements 402142 # number of replacements system.l2c.sampled_refs 433669 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 31163.178814 # Cycle average of tags in use +system.l2c.tagsinuse 31163.178813 # Cycle average of tags in use system.l2c.total_refs 2096699 # Total number of references to valid blocks. system.l2c.warmup_cycle 9278348000 # Cycle when the warmup percentage was hit. system.l2c.writebacks 124293 # number of writebacks diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index ee39a929f..0dba7f9ef 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -130,11 +130,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -303,11 +302,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=1 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=4 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -397,14 +395,13 @@ port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio syst [system.iocache] type=BaseCache -addr_range=0:18446744073709551615 +addr_range=0:8589934591 assoc=8 block_size=64 -cpu_side_filter_ranges=549755813888:18446744073709551615 +forward_snoops=false hash_delay=1 latency=50000 max_miss_count=0 -mem_side_filter_ranges=0:18446744073709551615 mshrs=20 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -432,11 +429,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=8 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=92 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -461,20 +457,20 @@ mem_side=system.membus.port[3] [system.membus] type=Bus -children=responder +children=badaddr_responder block_size=64 bus_id=1 clock=1000 header_cycles=1 responder_set=false width=64 -default=system.membus.responder.pio +default=system.membus.badaddr_responder.pio port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side -[system.membus.responder] +[system.membus.badaddr_responder] type=IsaFake pio_addr=0 -pio_latency=1 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -517,32 +513,14 @@ port=3456 [system.toL2Bus] type=Bus -children=responder block_size=64 bus_id=0 clock=1000 header_cycles=1 responder_set=false width=64 -default=system.toL2Bus.responder.pio port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side -[system.toL2Bus.responder] -type=IsaFake -pio_addr=0 -pio_latency=1 -pio_size=8 -platform=system.tsunami -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.toL2Bus.default - [system.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index bb339ffda..fffbf9b56 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:30:19 -M5 executing on maize +M5 compiled Apr 21 2009 17:45:48 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 17:46:13 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1867363148500 because m5_exit instruction encountered +Exiting @ tick 1867362977500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index a49abde89..1a13ce67c 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,314 +1,314 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 201864 # Simulator instruction rate (inst/s) -host_mem_usage 294704 # Number of bytes of host memory used -host_seconds 263.00 # Real time elapsed on the host -host_tick_rate 7100171671 # Simulator tick rate (ticks/s) +host_inst_rate 142678 # Simulator instruction rate (inst/s) +host_mem_usage 293540 # Number of bytes of host memory used +host_seconds 372.10 # Real time elapsed on the host +host_tick_rate 5018472256 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 53090630 # Number of instructions simulated +sim_insts 53090223 # Number of instructions simulated sim_seconds 1.867363 # Number of seconds simulated -sim_ticks 1867363148500 # Number of ticks simulated +sim_ticks 1867362977500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 6937900 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 13339861 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 41537 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 828629 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 12132448 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 14570242 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1034900 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 8461943 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 974606 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 6932886 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 13334785 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 41560 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 829405 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 12127013 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 14563706 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1034705 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 8461925 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 978098 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 100617513 +system.cpu.commit.COM:committed_per_cycle.samples 100629475 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 76371867 7590.32% - 1 10755813 1068.98% - 2 5991818 595.50% - 3 2987930 296.96% - 4 2074332 206.16% - 5 671621 66.75% - 6 397219 39.48% - 7 392307 38.99% - 8 974606 96.86% + 0 76387036 7590.92% + 1 10760374 1069.31% + 2 5981089 594.37% + 3 2990150 297.14% + 4 2079430 206.64% + 5 662647 65.85% + 6 398739 39.62% + 7 391912 38.95% + 8 978098 97.20% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 56284983 # Number of instructions committed -system.cpu.commit.COM:loads 9308629 # Number of loads committed -system.cpu.commit.COM:membars 228003 # Number of memory barriers committed -system.cpu.commit.COM:refs 15700868 # Number of memory references committed +system.cpu.commit.COM:count 56284559 # Number of instructions committed +system.cpu.commit.COM:loads 9308572 # Number of loads committed +system.cpu.commit.COM:membars 228000 # Number of memory barriers committed +system.cpu.commit.COM:refs 15700770 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 787164 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 56284983 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 667781 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 9518126 # The number of squashed insts skipped by commit -system.cpu.committedInsts 53090630 # Number of Instructions Simulated -system.cpu.committedInsts_total 53090630 # Number of Instructions Simulated -system.cpu.cpi 2.580435 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.580435 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 214297 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 15516.058460 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11817.323059 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits 192128 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 343975500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.103450 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 22169 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 4649 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207039500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.081756 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17520 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 9342423 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 23886.371687 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22764.504418 # average ReadReq mshr miss latency +system.cpu.commit.branchMispredicts 787906 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 56284559 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 667787 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 9472622 # The number of squashed insts skipped by commit +system.cpu.committedInsts 53090223 # Number of Instructions Simulated +system.cpu.committedInsts_total 53090223 # Number of Instructions Simulated +system.cpu.cpi 2.580471 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.580471 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 214422 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 15515.537615 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11814.147928 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits 192250 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 344010500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.103404 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 22172 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 4650 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207007500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.081717 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_misses 17522 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses 9342386 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 23884.018523 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22765.012818 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits 7809504 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 36615873000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.164082 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1532919 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 448215 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 24692749000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.116105 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1084704 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904972000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses 219789 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency 56331.265633 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.265633 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits 189804 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 1689093000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate 0.136426 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses 29985 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599138000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.136426 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 29985 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6157295 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 49032.528329 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54492.949680 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_hits 7810012 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 36599249000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.164024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1532374 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 447551 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 24696009500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.116118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1084823 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904976000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses 219797 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency 56331.488950 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.488950 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits 189796 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 1690001000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate 0.136494 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses 30001 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599998000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.136494 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_misses 30001 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6157245 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 49037.572489 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54494.404609 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits 3927003 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 109356855672 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.362219 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2230292 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1833354 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 21630322460 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.064466 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 396938 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235426497 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles_no_mshrs 10009.885310 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 11500 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.828407 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 138181 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 1383175962 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 23000 # number of cycles access was blocked +system.cpu.dcache.WriteReq_hits 3926713 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 109379874638 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.362261 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2230532 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1833591 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 21631063460 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.064467 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 396941 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235842997 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles_no_mshrs 10022.289139 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 16500 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 8.827872 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 137083 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 1373885462 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 66000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 15499718 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 38789.408479 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 31264.685707 # average overall mshr miss latency -system.cpu.dcache.demand_hits 11736507 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 145972728672 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.242792 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3763211 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2281569 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 46323071460 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.095592 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1481642 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 15499631 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 38794.252006 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 31264.812048 # average overall mshr miss latency +system.cpu.dcache.demand_hits 11736725 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 145979123638 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.242774 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3762906 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2281142 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 46327072960 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.095600 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1481764 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 15499718 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 38789.408479 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 31264.685707 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 15499631 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 38794.252006 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 31264.812048 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 11736507 # number of overall hits -system.cpu.dcache.overall_miss_latency 145972728672 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.242792 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3763211 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2281569 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 46323071460 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.095592 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1481642 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2140398497 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_hits 11736725 # number of overall hits +system.cpu.dcache.overall_miss_latency 145979123638 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.242774 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3762906 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2281142 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 46327072960 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.095600 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1481764 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2140818997 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1401991 # number of replacements -system.cpu.dcache.sampled_refs 1402503 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1402110 # number of replacements +system.cpu.dcache.sampled_refs 1402622 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.995429 # Cycle average of tags in use -system.cpu.dcache.total_refs 12381868 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 511.995450 # Cycle average of tags in use +system.cpu.dcache.total_refs 12382168 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 430428 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 48410304 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 42525 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 614935 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 72780900 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 37979006 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 13077120 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1650418 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 134762 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1151082 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 1236420 # DTB accesses -system.cpu.dtb.data_acv 825 # DTB access violations -system.cpu.dtb.data_hits 16772347 # DTB hits -system.cpu.dtb.data_misses 44495 # DTB misses +system.cpu.dcache.writebacks 430447 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 48442278 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 42798 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 614586 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 72711050 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 37969720 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 13062350 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1643233 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 134839 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1155126 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 1236133 # DTB accesses +system.cpu.dtb.data_acv 823 # DTB access violations +system.cpu.dtb.data_hits 16770289 # DTB hits +system.cpu.dtb.data_misses 44393 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 910052 # DTB read accesses -system.cpu.dtb.read_acv 586 # DTB read access violations -system.cpu.dtb.read_hits 10174508 # DTB read hits +system.cpu.dtb.read_accesses 909859 # DTB read accesses +system.cpu.dtb.read_acv 588 # DTB read access violations +system.cpu.dtb.read_hits 10173052 # DTB read hits system.cpu.dtb.read_misses 36219 # DTB read misses -system.cpu.dtb.write_accesses 326368 # DTB write accesses -system.cpu.dtb.write_acv 239 # DTB write access violations -system.cpu.dtb.write_hits 6597839 # DTB write hits -system.cpu.dtb.write_misses 8276 # DTB write misses -system.cpu.fetch.Branches 14570242 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 9007841 # Number of cache lines fetched -system.cpu.fetch.Cycles 23500316 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 455597 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 74326781 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 2461 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 969865 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.106355 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 9007841 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 7972800 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.542543 # Number of inst fetches per cycle +system.cpu.dtb.write_accesses 326274 # DTB write accesses +system.cpu.dtb.write_acv 235 # DTB write access violations +system.cpu.dtb.write_hits 6597237 # DTB write hits +system.cpu.dtb.write_misses 8174 # DTB write misses +system.cpu.fetch.Branches 14563706 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 8997144 # Number of cache lines fetched +system.cpu.fetch.Cycles 23480265 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 455601 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 74265234 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 2366 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 967433 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.106306 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 8997144 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 7967591 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.542091 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 102267931 +system.cpu.fetch.rateDist.samples 102272708 system.cpu.fetch.rateDist.min_value 0 - 0 87815810 8586.84% - 1 1050742 102.74% - 2 2021882 197.70% - 3 969421 94.79% - 4 3003437 293.68% - 5 686434 67.12% - 6 832579 81.41% - 7 1218388 119.14% - 8 4669238 456.57% + 0 87829962 8587.82% + 1 1051726 102.84% + 2 2021481 197.66% + 3 968950 94.74% + 4 2998384 293.18% + 5 688876 67.36% + 6 831559 81.31% + 7 1217734 119.07% + 8 4664036 456.04% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 9007841 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 14905.597019 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.422251 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 7960337 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15613672500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.116288 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1047504 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 51957 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11854398500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.110520 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 995547 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs 11175.438596 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_accesses 8997144 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 14906.743449 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.437092 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 7949609 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15615335499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.116430 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1047535 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 51877 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11855735000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.110664 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 995658 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs 11545.454545 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 7.997460 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 57 # number of cycles access was blocked +system.cpu.icache.avg_refs 7.985800 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 55 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 637000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 635000 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 9007841 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 14905.597019 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11907.422251 # average overall mshr miss latency -system.cpu.icache.demand_hits 7960337 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15613672500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.116288 # miss rate for demand accesses -system.cpu.icache.demand_misses 1047504 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 51957 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11854398500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.110520 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 995547 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 8997144 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 14906.743449 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11907.437092 # average overall mshr miss latency +system.cpu.icache.demand_hits 7949609 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15615335499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.116430 # miss rate for demand accesses +system.cpu.icache.demand_misses 1047535 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 51877 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11855735000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.110664 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 995658 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 9007841 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 14905.597019 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11907.422251 # average overall mshr miss latency +system.cpu.icache.overall_accesses 8997144 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 14906.743449 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11907.437092 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 7960337 # number of overall hits -system.cpu.icache.overall_miss_latency 15613672500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.116288 # miss rate for overall accesses -system.cpu.icache.overall_misses 1047504 # number of overall misses -system.cpu.icache.overall_mshr_hits 51957 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11854398500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.110520 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 995547 # number of overall MSHR misses +system.cpu.icache.overall_hits 7949609 # number of overall hits +system.cpu.icache.overall_miss_latency 15615335499 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.116430 # miss rate for overall accesses +system.cpu.icache.overall_misses 1047535 # number of overall misses +system.cpu.icache.overall_mshr_hits 51877 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11855735000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.110664 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 995658 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 994847 # number of replacements -system.cpu.icache.sampled_refs 995358 # Sample count of references to valid blocks. +system.cpu.icache.replacements 994957 # number of replacements +system.cpu.icache.sampled_refs 995468 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 509.772456 # Cycle average of tags in use -system.cpu.icache.total_refs 7960336 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 509.772438 # Cycle average of tags in use +system.cpu.icache.total_refs 7949608 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 25306164000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 34729008 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 9164699 # Number of branches executed -system.cpu.iew.EXEC:nop 3680668 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.420415 # Inst execution rate -system.cpu.iew.EXEC:refs 17055609 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 6621040 # Number of stores executed +system.cpu.idleCycles 34725081 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 9164165 # Number of branches executed +system.cpu.iew.EXEC:nop 3679313 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.420337 # Inst execution rate +system.cpu.iew.EXEC:refs 17053432 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 6620337 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 34548488 # num instructions consuming a value -system.cpu.iew.WB:count 57002857 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.763990 # average fanout of values written-back +system.cpu.iew.WB:consumers 34505393 # num instructions consuming a value +system.cpu.iew.WB:count 56992809 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.764525 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 26394693 # num instructions producing a value -system.cpu.iew.WB:rate 0.416089 # insts written-back per cycle -system.cpu.iew.WB:sent 57104330 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 856523 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 9726576 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 11055097 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1799800 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1048637 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 7027136 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 65932751 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 10434569 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 539744 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 57595615 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 50922 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 26380221 # num instructions producing a value +system.cpu.iew.WB:rate 0.416013 # insts written-back per cycle +system.cpu.iew.WB:sent 57095823 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 857525 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 9717535 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 11048107 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1799892 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1045221 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 7018400 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 65886993 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 10433095 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 539578 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 57585192 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 49355 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 6567 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1650418 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 550443 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 6548 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1643233 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 548828 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 311143 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 426303 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 11520 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 307987 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 427807 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 11074 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 46025 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 15352 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1746468 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 634897 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 46025 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 380989 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 475534 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.387532 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.387532 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 58135361 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 45865 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 15487 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1739535 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 626202 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 45865 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 381050 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 476475 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.387526 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.387526 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 58124772 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 7284 0.01% # Type of FU issued - IntAlu 39619390 68.15% # Type of FU issued - IntMult 62115 0.11% # Type of FU issued + IntAlu 39611417 68.15% # Type of FU issued + IntMult 62110 0.11% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 25609 0.04% # Type of FU issued + FloatAdd 25607 0.04% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued FloatDiv 3636 0.01% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 10789898 18.56% # Type of FU issued - MemWrite 6674141 11.48% # Type of FU issued - IprAccess 953288 1.64% # Type of FU issued + MemRead 10788116 18.56% # Type of FU issued + MemWrite 6673339 11.48% # Type of FU issued + IprAccess 953263 1.64% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 434481 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007474 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 433051 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.007450 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 52045 11.98% # attempts to use FU when none available + IntAlu 50716 11.71% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -317,44 +317,44 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 278817 64.17% # attempts to use FU when none available - MemWrite 103619 23.85% # attempts to use FU when none available + MemRead 279321 64.50% # attempts to use FU when none available + MemWrite 103014 23.79% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle::samples 102267931 +system.cpu.iq.ISSUE:issued_per_cycle::samples 102272708 system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::0-1 73151138 71.53% -system.cpu.iq.ISSUE:issued_per_cycle::1-2 14628619 14.30% -system.cpu.iq.ISSUE:issued_per_cycle::2-3 6419666 6.28% -system.cpu.iq.ISSUE:issued_per_cycle::3-4 3934330 3.85% -system.cpu.iq.ISSUE:issued_per_cycle::4-5 2528894 2.47% -system.cpu.iq.ISSUE:issued_per_cycle::5-6 1032607 1.01% -system.cpu.iq.ISSUE:issued_per_cycle::6-7 444582 0.43% -system.cpu.iq.ISSUE:issued_per_cycle::7-8 106443 0.10% -system.cpu.iq.ISSUE:issued_per_cycle::8 21652 0.02% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 73147659 71.52% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 14648372 14.32% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 6417102 6.27% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 3925012 3.84% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 2528533 2.47% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 1035489 1.01% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 441110 0.43% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 106525 0.10% +system.cpu.iq.ISSUE:issued_per_cycle::8 22906 0.02% system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::total 102267931 +system.cpu.iq.ISSUE:issued_per_cycle::total 102272708 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.568461 -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.134174 -system.cpu.iq.ISSUE:rate 0.424355 # Inst issue rate -system.cpu.iq.iqInstsAdded 60200389 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 58135361 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 2051694 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8738375 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 34584 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1383913 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4729371 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.568331 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.133996 +system.cpu.iq.ISSUE:rate 0.424275 # Inst issue rate +system.cpu.iq.iqInstsAdded 60155940 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 58124772 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 2051740 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 8691644 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 34825 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 1383953 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4676225 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1303895 # ITB accesses -system.cpu.itb.fetch_acv 943 # ITB acv -system.cpu.itb.fetch_hits 1264480 # ITB hits -system.cpu.itb.fetch_misses 39415 # ITB misses +system.cpu.itb.fetch_accesses 1303750 # ITB accesses +system.cpu.itb.fetch_acv 951 # ITB acv +system.cpu.itb.fetch_hits 1264322 # ITB hits +system.cpu.itb.fetch_misses 39428 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -363,15 +363,15 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.kern.callpal 192656 # number of callpals executed +system.cpu.kern.callpal 192652 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4177 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal_swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal_swpipl 175684 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal_swpipl 175681 91.19% 93.39% # number of callpals executed system.cpu.kern.callpal_rdps 6794 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed @@ -381,41 +381,41 @@ system.cpu.kern.callpal_rti 5221 2.71% 99.64% # nu system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211815 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6383 # number of quiesce instructions executed -system.cpu.kern.ipl_count 183033 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 74957 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 211811 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6385 # number of quiesce instructions executed +system.cpu.kern.ipl_count 183030 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74956 40.95% 40.95% # number of times we switched to this ipl system.cpu.kern.ipl_count_21 237 0.13% 41.08% # number of times we switched to this ipl system.cpu.kern.ipl_count_22 1890 1.03% 42.11% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 105949 57.89% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149307 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73590 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count_31 105947 57.89% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149305 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73589 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73590 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1867362274000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1824759658500 97.72% 97.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 102563000 0.01% 97.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 392423000 0.02% 97.75% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 42107629500 2.25% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_good_31 73589 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1867362103000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1824761131000 97.72% 97.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 102621000 0.01% 97.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 392338000 0.02% 97.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 42106013000 2.25% 100.00% # number of cycles we spent at this ipl system.cpu.kern.ipl_used_0 0.981763 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.694579 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1911 -system.cpu.kern.mode_good_user 1741 +system.cpu.kern.ipl_used_31 0.694583 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1910 +system.cpu.kern.mode_good_user 1740 system.cpu.kern.mode_good_idle 170 -system.cpu.kern.mode_switch_kernel 5973 # number of protection mode switches -system.cpu.kern.mode_switch_user 1741 # number of protection mode switches +system.cpu.kern.mode_switch_kernel 5972 # number of protection mode switches +system.cpu.kern.mode_switch_user 1740 # number of protection mode switches system.cpu.kern.mode_switch_idle 2095 # number of protection mode switches -system.cpu.kern.mode_switch_good 1.401085 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.319940 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good 1.400971 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.319826 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 31312997500 1.68% 1.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 3190588500 0.17% 1.85% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1832858680000 98.15% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.kern.mode_ticks_kernel 31331138500 1.68% 1.68% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 3191204500 0.17% 1.85% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1832839752000 98.15% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed @@ -447,29 +447,29 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.memDep0.conflictingLoads 3083644 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2877472 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 11055097 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7027136 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 136996939 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14276861 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 38259280 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1099460 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 39573188 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2235524 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 15708 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 83522905 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 68741813 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 46071316 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 12717646 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1650418 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 5220588 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7812034 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 28829228 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 1704991 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 12807732 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 256915 # count of temporary serializing insts renamed -system.cpu.timesIdled 1321478 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.memDep0.conflictingLoads 3077147 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2881540 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 11048107 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7018400 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 136997789 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14285499 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 38258957 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1096982 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 39563718 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2259510 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 15713 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 83436015 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 68679972 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 46025419 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 12707474 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1643233 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 5244444 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7766460 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 28828338 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 1705072 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 12828278 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 257070 # count of temporary serializing insts renamed +system.cpu.timesIdled 1322055 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -483,55 +483,55 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency 115277.445087 # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63277.445087 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19942998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_miss_latency 115260.104046 # average ReadReq miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19939998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.iocache.ReadReq_misses 173 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10946998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10943998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 137802.098720 # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85798.754910 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5725952806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_miss_latency 137794.253129 # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85790.836302 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5725626806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3565109864 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3564780830 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 6162.652539 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles_no_mshrs 6161.136802 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked_no_mshrs 10476 # number of cycles access was blocked +system.iocache.blocked_no_mshrs 10475 # number of cycles access was blocked system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 64559948 # number of cycles access was blocked +system.iocache.blocked_cycles_no_mshrs 64537908 # number of cycles access was blocked system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses 41725 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 137708.707106 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85705.377160 # average overall mshr miss latency +system.iocache.demand_avg_miss_latency 137700.822145 # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 85697.419485 # average overall mshr miss latency system.iocache.demand_hits 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5745895804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5745566804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate 1 # miss rate for demand accesses system.iocache.demand_misses 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3576056862 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3575724828 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.overall_accesses 41725 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 137708.707106 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85705.377160 # average overall mshr miss latency +system.iocache.overall_avg_miss_latency 137700.822145 # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 85697.419485 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.iocache.overall_hits 0 # number of overall hits -system.iocache.overall_miss_latency 5745895804 # number of overall miss cycles +system.iocache.overall_miss_latency 5745566804 # number of overall miss cycles system.iocache.overall_miss_rate 1 # miss rate for overall accesses system.iocache.overall_misses 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3576056862 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3575724828 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -539,88 +539,88 @@ system.iocache.overall_mshr_uncacheable_misses 0 system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.267414 # Cycle average of tags in use +system.iocache.tagsinuse 1.267415 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1716180054000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1716179713000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses 300588 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52362.011561 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40213.127257 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 15739392331 # number of ReadExReq miss cycles +system.l2c.ReadExReq_accesses 300582 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 52361.965557 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40206.978448 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15739064331 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 300588 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12087583496 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses 300582 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12085493996 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 300588 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2097395 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 52065.516476 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40025.575526 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 300582 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2097743 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 52046.745492 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40015.135689 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1786374 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16193469000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.148289 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 311021 # number of ReadReq misses +system.l2c.ReadReq_hits 1786590 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16194501000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.148328 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 311153 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12448754500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.148289 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 311020 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 810514000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 130249 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 52272.455021 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40098.173498 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 6808434994 # number of UpgradeReq miss cycles +system.l2c.ReadReq_mshr_miss_latency 12450789500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.148327 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 311152 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 810515500 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 130274 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 52273.201045 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.567435 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 6809838993 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 130249 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5222747000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses 130274 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5223670500 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 130249 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 130274 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1115855498 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 430428 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 430428 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1116273498 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 430447 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 430447 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 4.596635 # Average number of references to valid blocks. +system.l2c.avg_refs 4.597861 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2397983 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 52211.235170 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40117.751887 # average overall mshr miss latency -system.l2c.demand_hits 1786374 # number of demand (read+write) hits -system.l2c.demand_miss_latency 31932861331 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.255051 # miss rate for demand accesses -system.l2c.demand_misses 611609 # number of demand (read+write) misses +system.l2c.demand_accesses 2398325 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 52201.631966 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40109.399667 # average overall mshr miss latency +system.l2c.demand_hits 1786590 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31933565331 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.255068 # miss rate for demand accesses +system.l2c.demand_misses 611735 # number of demand (read+write) misses system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24536337996 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.255051 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 611608 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 24536283496 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.255067 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 611734 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2397983 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 52211.235170 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40117.751887 # average overall mshr miss latency +system.l2c.overall_accesses 2398325 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 52201.631966 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40109.399667 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1786374 # number of overall hits -system.l2c.overall_miss_latency 31932861331 # number of overall miss cycles -system.l2c.overall_miss_rate 0.255051 # miss rate for overall accesses -system.l2c.overall_misses 611609 # number of overall misses +system.l2c.overall_hits 1786590 # number of overall hits +system.l2c.overall_miss_latency 31933565331 # number of overall miss cycles +system.l2c.overall_miss_rate 0.255068 # miss rate for overall accesses +system.l2c.overall_misses 611735 # number of overall misses system.l2c.overall_mshr_hits 1 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24536337996 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.255051 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 611608 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1926369498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 24536283496 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.255067 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 611734 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1926788998 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 396031 # number of replacements -system.l2c.sampled_refs 427707 # Sample count of references to valid blocks. +system.l2c.replacements 396039 # number of replacements +system.l2c.sampled_refs 427720 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30680.970322 # Cycle average of tags in use -system.l2c.total_refs 1966013 # Total number of references to valid blocks. +system.l2c.tagsinuse 30690.397149 # Cycle average of tags in use +system.l2c.total_refs 1966597 # Total number of references to valid blocks. system.l2c.warmup_cycle 5645091000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119091 # number of writebacks +system.l2c.writebacks 119094 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout index 772ffba43..529f20a79 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:30:33 -M5 executing on maize +M5 compiled Apr 21 2009 18:04:32 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 18:06:05 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index b6a29a98d..ce9766cbc 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3425998 # Simulator instruction rate (inst/s) -host_mem_usage 331732 # Number of bytes of host memory used -host_seconds 71.17 # Real time elapsed on the host -host_tick_rate 1717182841 # Simulator tick rate (ticks/s) +host_inst_rate 2430508 # Simulator instruction rate (inst/s) +host_mem_usage 329972 # Number of bytes of host memory used +host_seconds 100.32 # Real time elapsed on the host +host_tick_rate 1218223693 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243835278 # Number of instructions simulated sim_seconds 0.122216 # Number of seconds simulated diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini index ee3e7a244..676b1ef8d 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -40,11 +40,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -76,11 +75,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -112,11 +110,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout index 3e2f8211c..2fa26b5da 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:30:42 -M5 executing on maize +M5 compiled Apr 21 2009 18:04:32 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 18:10:11 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 1ac5ddac3..aab215cd0 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1860125 # Simulator instruction rate (inst/s) -host_mem_usage 339272 # Number of bytes of host memory used -host_seconds 131.09 # Real time elapsed on the host -host_tick_rate 2795388911 # Simulator tick rate (ticks/s) +host_inst_rate 1286984 # Simulator instruction rate (inst/s) +host_mem_usage 337604 # Number of bytes of host memory used +host_seconds 189.46 # Real time elapsed on the host +host_tick_rate 1934075040 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243835278 # Number of instructions simulated sim_seconds 0.366435 # Number of seconds simulated diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout index 8774a9a45..4d45a89fb 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 12 2009 13:26:17 -M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch -M5 started Apr 12 2009 13:27:47 -M5 executing on tater +M5 compiled Apr 21 2009 19:00:07 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 19:23:20 +M5 executing on zizzer command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt index 7877f9ac7..2349e3c11 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 991817 # Simulator instruction rate (inst/s) -host_mem_usage 331908 # Number of bytes of host memory used -host_seconds 271.91 # Real time elapsed on the host -host_tick_rate 605700319 # Simulator tick rate (ticks/s) +host_inst_rate 1596079 # Simulator instruction rate (inst/s) +host_mem_usage 332596 # Number of bytes of host memory used +host_seconds 168.97 # Real time elapsed on the host +host_tick_rate 974720885 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 269686785 # Number of instructions simulated sim_seconds 0.164697 # Number of seconds simulated diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini index fc66ed40b..6e667cd38 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -40,11 +40,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -76,11 +75,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -112,11 +110,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout index dc48858d5..f69f1702d 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 12 2009 13:26:17 -M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch -M5 started Apr 12 2009 13:27:47 -M5 executing on tater +M5 compiled Apr 21 2009 19:00:07 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 19:25:28 +M5 executing on zizzer command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index 688fa76a5..b30863c58 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 614932 # Simulator instruction rate (inst/s) -host_mem_usage 339532 # Number of bytes of host memory used -host_seconds 438.56 # Real time elapsed on the host -host_tick_rate 870160390 # Simulator tick rate (ticks/s) +host_inst_rate 1561663 # Simulator instruction rate (inst/s) +host_mem_usage 340216 # Number of bytes of host memory used +host_seconds 172.69 # Real time elapsed on the host +host_tick_rate 2209830759 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 269686785 # Number of instructions simulated sim_seconds 0.381621 # Number of seconds simulated diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout index 20050d89e..b9e7f6545 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 12 2009 13:26:17 -M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch -M5 started Apr 12 2009 13:27:47 -M5 executing on tater +M5 compiled Apr 21 2009 19:00:07 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 19:26:09 +M5 executing on zizzer command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt index 95bb2d9ce..cffeaf89a 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1354692 # Simulator instruction rate (inst/s) -host_mem_usage 201092 # Number of bytes of host memory used -host_seconds 1103.93 # Real time elapsed on the host -host_tick_rate 786714284 # Simulator tick rate (ticks/s) +host_inst_rate 2677527 # Simulator instruction rate (inst/s) +host_mem_usage 201788 # Number of bytes of host memory used +host_seconds 558.53 # Real time elapsed on the host +host_tick_rate 1554928126 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1495482368 # Number of instructions simulated sim_seconds 0.868476 # Number of seconds simulated diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini index d9d78b96d..5f5b1b01c 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini @@ -40,11 +40,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -76,11 +75,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -112,11 +110,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout index 2db6852eb..2e4d3d070 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 12 2009 13:26:17 -M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch -M5 started Apr 12 2009 13:27:47 -M5 executing on tater +M5 compiled Apr 21 2009 19:00:07 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 19:28:21 +M5 executing on zizzer command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt index 3f66b5d0c..1dc17b8c3 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 965325 # Simulator instruction rate (inst/s) -host_mem_usage 208960 # Number of bytes of host memory used -host_seconds 1549.20 # Real time elapsed on the host -host_tick_rate 1111767915 # Simulator tick rate (ticks/s) +host_inst_rate 1120182 # Simulator instruction rate (inst/s) +host_mem_usage 209372 # Number of bytes of host memory used +host_seconds 1335.04 # Real time elapsed on the host +host_tick_rate 1290116936 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1495482368 # Number of instructions simulated sim_seconds 1.722353 # Number of seconds simulated diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index 7a03ec602..561928f24 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -104,11 +104,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -277,11 +276,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -313,11 +311,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -356,12 +353,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/eon +executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout index 88f7ed959..856b2af50 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 14 2009 23:40:03 -M5 revision 4208b24ee3ad 6033 default qtip tip new-thread-status-stats-update -M5 started Apr 14 2009 23:48:49 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 17:15:52 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt index a28684bb7..2a30c3ff4 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 195698 # Simulator instruction rate (inst/s) -host_mem_usage 215252 # Number of bytes of host memory used -host_seconds 1919.15 # Real time elapsed on the host -host_tick_rate 70341803 # Simulator tick rate (ticks/s) +host_inst_rate 243057 # Simulator instruction rate (inst/s) +host_mem_usage 211796 # Number of bytes of host memory used +host_seconds 1545.21 # Real time elapsed on the host +host_tick_rate 87364560 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 375574819 # Number of instructions simulated sim_seconds 0.134997 # Number of seconds simulated diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout index 5cd2ed646..ff24c9828 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:41:56 -M5 executing on maize +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:39:12 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt index 09b41faf1..2dd6bb319 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 5193663 # Simulator instruction rate (inst/s) -host_mem_usage 205028 # Number of bytes of host memory used -host_seconds 76.76 # Real time elapsed on the host -host_tick_rate 2596825201 # Simulator tick rate (ticks/s) +host_inst_rate 3427488 # Simulator instruction rate (inst/s) +host_mem_usage 203296 # Number of bytes of host memory used +host_seconds 116.31 # Real time elapsed on the host +host_tick_rate 1713741057 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664595 # Number of instructions simulated sim_seconds 0.199332 # Number of seconds simulated diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini index 6bb84f209..cb9992f60 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -40,11 +40,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -76,11 +75,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -112,11 +110,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout index 15ed4127f..421c424a0 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:44:12 -M5 executing on maize +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:39:04 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 64814b26f..1883943d5 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2545334 # Simulator instruction rate (inst/s) -host_mem_usage 212560 # Number of bytes of host memory used -host_seconds 156.63 # Real time elapsed on the host -host_tick_rate 3622337158 # Simulator tick rate (ticks/s) +host_inst_rate 1575428 # Simulator instruction rate (inst/s) +host_mem_usage 210936 # Number of bytes of host memory used +host_seconds 253.05 # Real time elapsed on the host +host_tick_rate 2242037981 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664609 # Number of instructions simulated sim_seconds 0.567352 # Number of seconds simulated diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index 5c8cc4e1c..451db988f 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -104,11 +104,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -277,11 +276,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -313,11 +311,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -356,12 +353,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 006c533dd..064222d23 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 14 2009 23:40:03 -M5 revision 4208b24ee3ad 6033 default qtip tip new-thread-status-stats-update -M5 started Apr 14 2009 23:46:17 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:44:16 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index ad125d151..6e24feffe 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 193760 # Simulator instruction rate (inst/s) -host_mem_usage 215160 # Number of bytes of host memory used -host_seconds 9408.76 # Real time elapsed on the host -host_tick_rate 74947150 # Simulator tick rate (ticks/s) +host_inst_rate 191030 # Simulator instruction rate (inst/s) +host_mem_usage 211708 # Number of bytes of host memory used +host_seconds 9543.22 # Real time elapsed on the host +host_tick_rate 73891181 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1823043370 # Number of instructions simulated sim_seconds 0.705159 # Number of seconds simulated diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout index c197c46fb..867a8e254 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:38:04 -M5 executing on maize +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:41:45 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index ebae3bb0f..587f67841 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 5314394 # Simulator instruction rate (inst/s) -host_mem_usage 204196 # Number of bytes of host memory used -host_seconds 378.03 # Real time elapsed on the host -host_tick_rate 2657768720 # Simulator tick rate (ticks/s) +host_inst_rate 3366150 # Simulator instruction rate (inst/s) +host_mem_usage 202468 # Number of bytes of host memory used +host_seconds 596.82 # Real time elapsed on the host +host_tick_rate 1683437750 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 1.004711 # Number of seconds simulated diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index 8c5285f82..066cbfff7 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -40,11 +40,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -76,11 +75,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -112,11 +110,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout index cdafa0ab2..816f64d63 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:45:29 -M5 executing on maize +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:39:12 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 4c7aa8469..27fe7637a 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2595694 # Simulator instruction rate (inst/s) -host_mem_usage 211736 # Number of bytes of host memory used -host_seconds 773.97 # Real time elapsed on the host -host_tick_rate 3637030411 # Simulator tick rate (ticks/s) +host_inst_rate 1413347 # Simulator instruction rate (inst/s) +host_mem_usage 210092 # Number of bytes of host memory used +host_seconds 1421.44 # Real time elapsed on the host +host_tick_rate 1980352310 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 2.814951 # Number of seconds simulated diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index e2f1cbbca..33c06f76d 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -104,11 +104,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -277,11 +276,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -313,11 +311,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -356,12 +353,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout index f4ca6413a..689b74dbf 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 14 2009 23:40:03 -M5 revision 4208b24ee3ad 6033 default qtip tip new-thread-status-stats-update -M5 started Apr 14 2009 23:40:05 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:52:32 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index bae501a90..99db99027 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 213847 # Simulator instruction rate (inst/s) -host_mem_usage 218620 # Number of bytes of host memory used -host_seconds 372.19 # Real time elapsed on the host -host_tick_rate 72905538 # Simulator tick rate (ticks/s) +host_inst_rate 274491 # Simulator instruction rate (inst/s) +host_mem_usage 215172 # Number of bytes of host memory used +host_seconds 289.96 # Real time elapsed on the host +host_tick_rate 93580527 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated sim_seconds 0.027135 # Number of seconds simulated diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout index cac080f34..9dd7f1f1a 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:43:53 -M5 executing on maize +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:57:23 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index 25afd1229..aa4c8889a 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 5274353 # Simulator instruction rate (inst/s) -host_mem_usage 207596 # Number of bytes of host memory used -host_seconds 16.75 # Real time elapsed on the host -host_tick_rate 2640164541 # Simulator tick rate (ticks/s) +host_inst_rate 5366735 # Simulator instruction rate (inst/s) +host_mem_usage 205860 # Number of bytes of host memory used +host_seconds 16.46 # Real time elapsed on the host +host_tick_rate 2686413423 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.044221 # Number of seconds simulated diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index bec56725b..f5ae96163 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -40,11 +40,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -76,11 +75,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -112,11 +110,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout index 621e65c84..b076edccd 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:30:03 -M5 executing on maize +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:43:17 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index a690b2e36..cd99a1a3e 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2447162 # Simulator instruction rate (inst/s) -host_mem_usage 215136 # Number of bytes of host memory used -host_seconds 36.10 # Real time elapsed on the host -host_tick_rate 3744340356 # Simulator tick rate (ticks/s) +host_inst_rate 1524580 # Simulator instruction rate (inst/s) +host_mem_usage 213492 # Number of bytes of host memory used +host_seconds 57.94 # Real time elapsed on the host +host_tick_rate 2332726052 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.135169 # Number of seconds simulated diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout index 9f2f0d730..736241b6c 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:31:45 -M5 executing on maize +M5 compiled Apr 21 2009 18:04:32 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 18:05:08 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index 3f55620e8..aa22e4be1 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3453262 # Simulator instruction rate (inst/s) -host_mem_usage 208432 # Number of bytes of host memory used -host_seconds 39.42 # Real time elapsed on the host -host_tick_rate 1728626295 # Simulator tick rate (ticks/s) +host_inst_rate 2400032 # Simulator instruction rate (inst/s) +host_mem_usage 206680 # Number of bytes of host memory used +host_seconds 56.72 # Real time elapsed on the host +host_tick_rate 1201405231 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated sim_seconds 0.068149 # Number of seconds simulated diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini index 05ad8a083..67702eb09 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -40,11 +40,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -76,11 +75,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -112,11 +110,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout index dcc6d4681..95fbb7b97 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:30:34 -M5 executing on maize +M5 compiled Apr 21 2009 18:04:32 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 18:15:57 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 16a33a02d..067472342 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1887759 # Simulator instruction rate (inst/s) -host_mem_usage 215972 # Number of bytes of host memory used -host_seconds 72.12 # Real time elapsed on the host -host_tick_rate 2820090693 # Simulator tick rate (ticks/s) +host_inst_rate 1167251 # Simulator instruction rate (inst/s) +host_mem_usage 214304 # Number of bytes of host memory used +host_seconds 116.63 # Real time elapsed on the host +host_tick_rate 1743737825 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated sim_seconds 0.203377 # Number of seconds simulated diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index e924b3603..f540ab7a3 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -104,11 +104,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -277,11 +276,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -313,11 +311,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -356,12 +353,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/bzip2 +executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout index 2efc71f10..a3fed9503 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 14 2009 23:40:03 -M5 revision 4208b24ee3ad 6033 default qtip tip new-thread-status-stats-update -M5 started Apr 15 2009 00:17:29 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:57:40 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index a08661a40..f9cc5dfc4 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 188573 # Simulator instruction rate (inst/s) -host_mem_usage 207604 # Number of bytes of host memory used -host_seconds 9206.20 # Real time elapsed on the host -host_tick_rate 80631433 # Simulator tick rate (ticks/s) +host_inst_rate 165473 # Simulator instruction rate (inst/s) +host_mem_usage 204148 # Number of bytes of host memory used +host_seconds 10491.39 # Real time elapsed on the host +host_tick_rate 70754150 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated sim_seconds 0.742309 # Number of seconds simulated diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout index 1fd03182d..3b9fb39a4 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:44:24 -M5 executing on maize +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:59:02 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index 7215f3f82..81d14da53 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 5417867 # Simulator instruction rate (inst/s) -host_mem_usage 197364 # Number of bytes of host memory used -host_seconds 335.89 # Real time elapsed on the host -host_tick_rate 2718753958 # Simulator tick rate (ticks/s) +host_inst_rate 3729984 # Simulator instruction rate (inst/s) +host_mem_usage 195632 # Number of bytes of host memory used +host_seconds 487.88 # Real time elapsed on the host +host_tick_rate 1871753572 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 0.913189 # Number of seconds simulated diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index f8a290050..fd5428b3a 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -40,11 +40,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -76,11 +75,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -112,11 +110,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout index a3ccdd7b3..3314840b7 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:43:13 -M5 executing on maize +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:41:08 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 6127ea9b9..5f4f3edad 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2385042 # Simulator instruction rate (inst/s) -host_mem_usage 204904 # Number of bytes of host memory used -host_seconds 763.00 # Real time elapsed on the host -host_tick_rate 3575360927 # Simulator tick rate (ticks/s) +host_inst_rate 1697488 # Simulator instruction rate (inst/s) +host_mem_usage 203260 # Number of bytes of host memory used +host_seconds 1072.04 # Real time elapsed on the host +host_tick_rate 2544665146 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 2.727991 # Number of seconds simulated diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout index f3a9fb5ea..aacd62b2b 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 12 2009 13:26:17 -M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch -M5 started Apr 12 2009 13:27:47 -M5 executing on tater +M5 compiled Apr 21 2009 19:00:07 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 19:35:29 +M5 executing on zizzer command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 47eb00d6b..80e9ba912 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1691472 # Simulator instruction rate (inst/s) -host_mem_usage 197552 # Number of bytes of host memory used -host_seconds 2750.96 # Real time elapsed on the host -host_tick_rate 1028427031 # Simulator tick rate (ticks/s) +host_inst_rate 2097364 # Simulator instruction rate (inst/s) +host_mem_usage 197956 # Number of bytes of host memory used +host_seconds 2218.58 # Real time elapsed on the host +host_tick_rate 1275211959 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4653176270 # Number of instructions simulated sim_seconds 2.829164 # Number of seconds simulated diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini index 8499b0423..2985d5b21 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -40,11 +40,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -76,11 +75,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -112,11 +110,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index bf1d55f3d..aa3bb16f1 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 12 2009 13:26:17 -M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch -M5 started Apr 12 2009 13:27:47 -M5 executing on tater +M5 compiled Apr 21 2009 19:00:07 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 19:50:36 +M5 executing on zizzer command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 32abffbae..f81f1eda7 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1124863 # Simulator instruction rate (inst/s) -host_mem_usage 205172 # Number of bytes of host memory used -host_seconds 4136.66 # Real time elapsed on the host -host_tick_rate 1447560054 # Simulator tick rate (ticks/s) +host_inst_rate 1080301 # Simulator instruction rate (inst/s) +host_mem_usage 205584 # Number of bytes of host memory used +host_seconds 4307.30 # Real time elapsed on the host +host_tick_rate 1390213645 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4653176270 # Number of instructions simulated sim_seconds 5.988064 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 7120f53fd..f62e1fe85 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -104,11 +104,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -277,11 +276,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -313,11 +311,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -356,12 +353,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf +executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index 9b3fabe8e..e5f5aca9e 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 14 2009 23:40:03 -M5 revision 4208b24ee3ad 6033 default qtip tip new-thread-status-stats-update -M5 started Apr 14 2009 23:40:05 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 17:02:55 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index dce6864cd..af7bb24bb 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 160619 # Simulator instruction rate (inst/s) -host_mem_usage 212880 # Number of bytes of host memory used -host_seconds 524.10 # Real time elapsed on the host -host_tick_rate 77883837 # Simulator tick rate (ticks/s) +host_inst_rate 199037 # Simulator instruction rate (inst/s) +host_mem_usage 209432 # Number of bytes of host memory used +host_seconds 422.94 # Real time elapsed on the host +host_tick_rate 96512612 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated sim_seconds 0.040819 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout index 68a75cbd9..76511d754 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:36:46 -M5 executing on maize +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:51:42 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index bf89ff397..b041df4e4 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 5529646 # Simulator instruction rate (inst/s) -host_mem_usage 202292 # Number of bytes of host memory used -host_seconds 16.62 # Real time elapsed on the host -host_tick_rate 2764786682 # Simulator tick rate (ticks/s) +host_inst_rate 5612458 # Simulator instruction rate (inst/s) +host_mem_usage 200556 # Number of bytes of host memory used +host_seconds 16.38 # Real time elapsed on the host +host_tick_rate 2806199168 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.045952 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index 2164626a2..7b97859d0 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -40,11 +40,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -76,11 +75,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -112,11 +110,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout index 24227ac66..977b57eee 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:33:56 -M5 executing on maize +M5 compiled Apr 21 2009 16:38:39 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 16:51:59 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index e5dfef14d..369af5305 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2783619 # Simulator instruction rate (inst/s) -host_mem_usage 209832 # Number of bytes of host memory used -host_seconds 33.02 # Real time elapsed on the host -host_tick_rate 3596666384 # Simulator tick rate (ticks/s) +host_inst_rate 2784324 # Simulator instruction rate (inst/s) +host_mem_usage 208188 # Number of bytes of host memory used +host_seconds 33.01 # Real time elapsed on the host +host_tick_rate 3597581254 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.118747 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout index bcecb77e1..473c9fb4d 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:32:55 -M5 executing on maize +M5 compiled Apr 21 2009 18:04:32 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 18:14:36 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index 2a0d5ef75..a32d620ce 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3173092 # Simulator instruction rate (inst/s) -host_mem_usage 204068 # Number of bytes of host memory used -host_seconds 60.96 # Real time elapsed on the host -host_tick_rate 1586549351 # Simulator tick rate (ticks/s) +host_inst_rate 2403614 # Simulator instruction rate (inst/s) +host_mem_usage 202316 # Number of bytes of host memory used +host_seconds 80.48 # Real time elapsed on the host +host_tick_rate 1201810632 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated sim_seconds 0.096723 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini index 1c4d82608..d52807b10 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -40,11 +40,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -76,11 +75,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -112,11 +110,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout index bc529416a..ac7620094 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:02 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:31:47 -M5 executing on maize +M5 compiled Apr 21 2009 18:04:32 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 18:07:46 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 1993c7752..c019fdbed 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1944755 # Simulator instruction rate (inst/s) -host_mem_usage 211604 # Number of bytes of host memory used -host_seconds 99.47 # Real time elapsed on the host -host_tick_rate 2720193548 # Simulator tick rate (ticks/s) +host_inst_rate 1335116 # Simulator instruction rate (inst/s) +host_mem_usage 209936 # Number of bytes of host memory used +host_seconds 144.89 # Real time elapsed on the host +host_tick_rate 1867472873 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated sim_seconds 0.270578 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout index 839d47ddf..cc9142f47 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout @@ -5,13 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 12 2009 13:26:17 -M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch -M5 started Apr 12 2009 13:27:47 -M5 executing on tater +M5 compiled Apr 21 2009 19:00:07 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 19:52:32 +M5 executing on zizzer command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt index ffa74eb22..0e46be9eb 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1002077 # Simulator instruction rate (inst/s) -host_mem_usage 204648 # Number of bytes of host memory used -host_seconds 218.14 # Real time elapsed on the host -host_tick_rate 595983507 # Simulator tick rate (ticks/s) +host_inst_rate 1749933 # Simulator instruction rate (inst/s) +host_mem_usage 205336 # Number of bytes of host memory used +host_seconds 124.92 # Real time elapsed on the host +host_tick_rate 1040768333 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 218595312 # Number of instructions simulated sim_seconds 0.130009 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini index 8b6664da9..04e429e1e 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -40,11 +40,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -76,11 +75,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -112,11 +110,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=10000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout index 96041e645..c109ece93 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -5,13 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 12 2009 13:26:17 -M5 revision 8c874c02878a 6042 default qtip tip cpuidfixstats.patch -M5 started Apr 12 2009 13:27:47 -M5 executing on tater +M5 compiled Apr 21 2009 19:00:07 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 19:54:37 +M5 executing on zizzer command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index 01ea14551..558f7df88 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 659365 # Simulator instruction rate (inst/s) -host_mem_usage 212548 # Number of bytes of host memory used -host_seconds 331.52 # Real time elapsed on the host -host_tick_rate 756945311 # Simulator tick rate (ticks/s) +host_inst_rate 1114702 # Simulator instruction rate (inst/s) +host_mem_usage 212960 # Number of bytes of host memory used +host_seconds 196.10 # Real time elapsed on the host +host_tick_rate 1279666495 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 218595312 # Number of instructions simulated sim_seconds 0.250946 # Number of seconds simulated diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini index 4b84818cf..b6c350b4c 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini @@ -129,48 +129,30 @@ sys=system [system.iobus] type=Bus -children=responder block_size=64 bus_id=0 clock=2 header_cycles=1 responder_set=false width=64 -default=system.iobus.responder.pio port=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.bridge.side_a system.disk0.pio -[system.iobus.responder] -type=IsaFake -pio_addr=0 -pio_latency=0 -pio_size=8 -platform=system.t1000 -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.default - [system.membus] type=Bus -children=responder +children=badaddr_responder block_size=64 bus_id=1 clock=2 header_cycles=1 responder_set=false width=64 -default=system.membus.responder.pio +default=system.membus.badaddr_responder.pio port=system.t1000.iob.pio system.t1000.htod.pio system.bridge.side_b system.physmem.port[0] system.physmem2.port[0] system.rom.port[0] system.nvram.port[0] system.hypervisor_desc.port[0] system.partition_desc.port[0] system.cpu.icache_port system.cpu.dcache_port -[system.membus.responder] +[system.membus.badaddr_responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=2 pio_size=8 platform=system.t1000 ret_bad_addr=true diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr index d6849b6b0..56e10add5 100755 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr @@ -1,13 +1,5 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 -Warning: rounding error > tolerance - 0.002000 rounded to 0 -Warning: rounding error > tolerance - 0.002000 rounded to 0 warn: Sockets disabled, not accepting terminal connections For more information see: http://www.m5sim.org/warn/8742226b -Warning: rounding error > tolerance - 0.002000 rounded to 0 warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 warn: Don't know what interrupt to clear for console. diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout index 31a7bda45..655c95551 100755 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2009 12:30:03 -M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff -M5 started Apr 8 2009 12:30:19 -M5 executing on maize +M5 compiled Apr 21 2009 18:38:50 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 18:39:20 +M5 executing on zizzer command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic Global frequency set at 2000000000 ticks per second info: No kernel set for full system simulation. Assuming you know what you're doing... diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt index 4fd5a8137..044bdb674 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3204133 # Simulator instruction rate (inst/s) -host_mem_usage 503348 # Number of bytes of host memory used -host_seconds 695.71 # Real time elapsed on the host -host_tick_rate 3210768 # Simulator tick rate (ticks/s) +host_inst_rate 2338829 # Simulator instruction rate (inst/s) +host_mem_usage 501616 # Number of bytes of host memory used +host_seconds 953.11 # Real time elapsed on the host +host_tick_rate 2343672 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks sim_insts 2229160714 # Number of instructions simulated sim_seconds 1.116889 # Number of seconds simulated |