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authorAndreas Sandberg <andreas.sandberg@arm.com>2015-07-07 09:51:05 +0100
committerAndreas Sandberg <andreas.sandberg@arm.com>2015-07-07 09:51:05 +0100
commita0cbf5541133e58968919991635797babaad2a18 (patch)
tree4cf0a0a70ea5835350b2fe7032e637dc3cf4b8b4 /tests/long
parented38e3432c732d71cf29dc3fd739f078be7de6b0 (diff)
downloadgem5-a0cbf5541133e58968919991635797babaad2a18.tar.xz
stats: Update pc-switcheroo stats
The pc-switcheroo test cases has slightly different timing after decoupling draining from the SimObject hierarchy. This is expected since objects aren't drained in the exact same order as before.
Diffstat (limited to 'tests/long')
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini8
-rwxr-xr-xtests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout12
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt10
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini8
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json198
-rwxr-xr-xtests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr24
-rwxr-xr-xtests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout8
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt3216
8 files changed, 1743 insertions, 1741 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
index 5fc8b743b..4b49caa69 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
@@ -20,7 +20,7 @@ eventq_index=0
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
kernel_addr_check=true
load_addr_mask=18446744073709551615
load_offset=0
@@ -29,7 +29,7 @@ mem_ranges=0:134217727
memories=system.physmem
mmap_using_noreserve=false
num_work_ids=16
-readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5/tests/halt.sh
smbios_table=system.smbios_table
symbolfile=
work_begin_ckpt_count=0
@@ -1586,7 +1586,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-x86.img
+image_file=/work/gem5/dist/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
@@ -1609,7 +1609,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
+image_file=/work/gem5/dist/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
index 24624d6a1..9ee84cae3 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
@@ -1,13 +1,13 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Apr 22 2015 08:10:29
-gem5 started Apr 22 2015 10:12:51
-gem5 executing on phenom
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
+gem5 compiled Jul 6 2015 14:29:04
+gem5 started Jul 6 2015 20:46:38
+gem5 executing on e104799-lin
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /work/gem5/outgoing/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5154239928000 because m5_exit instruction encountered
+Exiting @ tick 5130108675000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index 6393b5a08..9f38e11f8 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 5.130109 # Nu
sim_ticks 5130108675000 # Number of ticks simulated
final_tick 5130108675000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 175723 # Simulator instruction rate (inst/s)
-host_op_rate 347336 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2210269457 # Simulator tick rate (ticks/s)
-host_mem_usage 810456 # Number of bytes of host memory used
-host_seconds 2321.03 # Real time elapsed on the host
+host_inst_rate 172691 # Simulator instruction rate (inst/s)
+host_op_rate 341343 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2172133567 # Simulator tick rate (ticks/s)
+host_mem_usage 759908 # Number of bytes of host memory used
+host_seconds 2361.78 # Real time elapsed on the host
sim_insts 407858109 # Number of instructions simulated
sim_ops 806179275 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
index 57635b8c2..bea975397 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
@@ -20,7 +20,7 @@ eventq_index=0
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
kernel_addr_check=true
load_addr_mask=18446744073709551615
load_offset=0
@@ -29,7 +29,7 @@ mem_ranges=0:134217727
memories=system.physmem
mmap_using_noreserve=false
num_work_ids=16
-readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5/tests/halt.sh
smbios_table=system.smbios_table
symbolfile=
work_begin_ckpt_count=0
@@ -1639,7 +1639,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-x86.img
+image_file=/work/gem5/dist/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
@@ -1662,7 +1662,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
+image_file=/work/gem5/dist/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json
index 8d20c23c9..6fe40cc4f 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json
@@ -2,7 +2,7 @@
"name": null,
"sim_quantum": 0,
"system": {
- "kernel": "/home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9",
+ "kernel": "/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9",
"mmap_using_noreserve": false,
"kernel_addr_check": true,
"bridge": {
@@ -103,7 +103,10 @@
},
"symbolfile": "",
"l2c": {
- "is_top_level": false,
+ "cpu_side": {
+ "peer": "system.toL2Bus.master[0]",
+ "role": "SLAVE"
+ },
"prefetcher": null,
"clk_domain": "system.cpu_clk_domain",
"write_buffers": 8,
@@ -138,19 +141,15 @@
"addr_ranges": [
"0:18446744073709551615"
],
- "assoc": 8,
+ "is_read_only": false,
"prefetch_on_access": false,
"path": "system.l2c",
"name": "l2c",
"type": "BaseCache",
"sequential_access": false,
- "cpu_side": {
- "peer": "system.toL2Bus.master[0]",
- "role": "SLAVE"
- },
- "two_queue": false
+ "assoc": 8
},
- "readfile": "/home/stever/hg/m5sim.org/gem5/tests/halt.sh",
+ "readfile": "/work/gem5/outgoing/gem5/tests/halt.sh",
"intel_mp_table": {
"oem_table_addr": 0,
"name": "intel_mp_table",
@@ -631,7 +630,10 @@
"cxx_class": "LinuxX86System",
"load_offset": 0,
"iocache": {
- "is_top_level": true,
+ "cpu_side": {
+ "peer": "system.iobus.master[19]",
+ "role": "SLAVE"
+ },
"prefetcher": null,
"clk_domain": "system.clk_domain",
"write_buffers": 8,
@@ -666,17 +668,13 @@
"addr_ranges": [
"0:134217727"
],
- "assoc": 8,
+ "is_read_only": false,
"prefetch_on_access": false,
"path": "system.iocache",
"name": "iocache",
"type": "BaseCache",
"sequential_access": false,
- "cpu_side": {
- "peer": "system.iobus.master[19]",
- "role": "SLAVE"
- },
- "two_queue": false
+ "assoc": 8
},
"intel_mp_pointer": {
"imcr_present": true,
@@ -1185,7 +1183,7 @@
"eventq_index": 0,
"cxx_class": "RawDiskImage",
"path": "system.pc.south_bridge.ide.disks0.image.child",
- "image_file": "/home/stever/m5/m5_system_2.0b3/disks/linux-x86.img",
+ "image_file": "/work/gem5/dist/disks/linux-x86.img",
"type": "RawDiskImage"
},
"path": "system.pc.south_bridge.ide.disks0.image",
@@ -1213,7 +1211,7 @@
"eventq_index": 0,
"cxx_class": "RawDiskImage",
"path": "system.pc.south_bridge.ide.disks1.image.child",
- "image_file": "/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img",
+ "image_file": "/work/gem5/dist/disks/linux-bigswap2.img",
"type": "RawDiskImage"
},
"path": "system.pc.south_bridge.ide.disks1.image",
@@ -1791,7 +1789,10 @@
"role": "MASTER"
},
"icache": {
- "is_top_level": true,
+ "cpu_side": {
+ "peer": "system.cpu0.icache_port",
+ "role": "SLAVE"
+ },
"prefetcher": null,
"clk_domain": "system.cpu_clk_domain",
"write_buffers": 8,
@@ -1826,17 +1827,13 @@
"addr_ranges": [
"0:18446744073709551615"
],
- "assoc": 1,
+ "is_read_only": true,
"prefetch_on_access": false,
"path": "system.cpu0.icache",
"name": "icache",
"type": "BaseCache",
"sequential_access": false,
- "cpu_side": {
- "peer": "system.cpu0.icache_port",
- "role": "SLAVE"
- },
- "two_queue": false
+ "assoc": 1
},
"interrupts": {
"int_master": {
@@ -1901,7 +1898,10 @@
"progress_interval": 0,
"branchPred": null,
"dcache": {
- "is_top_level": true,
+ "cpu_side": {
+ "peer": "system.cpu0.dcache_port",
+ "role": "SLAVE"
+ },
"prefetcher": null,
"clk_domain": "system.cpu_clk_domain",
"write_buffers": 8,
@@ -1936,17 +1936,13 @@
"addr_ranges": [
"0:18446744073709551615"
],
- "assoc": 4,
+ "is_read_only": false,
"prefetch_on_access": false,
"path": "system.cpu0.dcache",
"name": "dcache",
"type": "BaseCache",
"sequential_access": false,
- "cpu_side": {
- "peer": "system.cpu0.dcache_port",
- "role": "SLAVE"
- },
- "two_queue": false
+ "assoc": 4
},
"isa": [
{
@@ -2109,11 +2105,11 @@
"count": 6,
"opList": [
{
- "issueLat": 1,
+ "opClass": "IntAlu",
"opLat": 1,
"name": "opList",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "IntAlu",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList0.opList",
"type": "OpDesc"
@@ -2129,21 +2125,21 @@
"count": 2,
"opList": [
{
- "issueLat": 1,
+ "opClass": "IntMult",
"opLat": 3,
"name": "opList0",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "IntMult",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList1.opList0",
"type": "OpDesc"
},
{
- "issueLat": 19,
- "opLat": 20,
+ "opClass": "IntDiv",
+ "opLat": 1,
"name": "opList1",
+ "pipelined": false,
"eventq_index": 0,
- "opClass": "IntDiv",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList1.opList1",
"type": "OpDesc"
@@ -2159,31 +2155,31 @@
"count": 4,
"opList": [
{
- "issueLat": 1,
+ "opClass": "FloatAdd",
"opLat": 2,
"name": "opList0",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "FloatAdd",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList2.opList0",
"type": "OpDesc"
},
{
- "issueLat": 1,
+ "opClass": "FloatCmp",
"opLat": 2,
"name": "opList1",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "FloatCmp",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList2.opList1",
"type": "OpDesc"
},
{
- "issueLat": 1,
+ "opClass": "FloatCvt",
"opLat": 2,
"name": "opList2",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "FloatCvt",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList2.opList2",
"type": "OpDesc"
@@ -2199,31 +2195,31 @@
"count": 2,
"opList": [
{
- "issueLat": 1,
+ "opClass": "FloatMult",
"opLat": 4,
"name": "opList0",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "FloatMult",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList3.opList0",
"type": "OpDesc"
},
{
- "issueLat": 12,
+ "opClass": "FloatDiv",
"opLat": 12,
"name": "opList1",
+ "pipelined": false,
"eventq_index": 0,
- "opClass": "FloatDiv",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList3.opList1",
"type": "OpDesc"
},
{
- "issueLat": 24,
+ "opClass": "FloatSqrt",
"opLat": 24,
"name": "opList2",
+ "pipelined": false,
"eventq_index": 0,
- "opClass": "FloatSqrt",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList3.opList2",
"type": "OpDesc"
@@ -2239,11 +2235,11 @@
"count": 0,
"opList": [
{
- "issueLat": 1,
+ "opClass": "MemRead",
"opLat": 1,
"name": "opList",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "MemRead",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList4.opList",
"type": "OpDesc"
@@ -2259,201 +2255,201 @@
"count": 4,
"opList": [
{
- "issueLat": 1,
+ "opClass": "SimdAdd",
"opLat": 1,
"name": "opList00",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "SimdAdd",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList00",
"type": "OpDesc"
},
{
- "issueLat": 1,
+ "opClass": "SimdAddAcc",
"opLat": 1,
"name": "opList01",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "SimdAddAcc",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList01",
"type": "OpDesc"
},
{
- "issueLat": 1,
+ "opClass": "SimdAlu",
"opLat": 1,
"name": "opList02",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "SimdAlu",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList02",
"type": "OpDesc"
},
{
- "issueLat": 1,
+ "opClass": "SimdCmp",
"opLat": 1,
"name": "opList03",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "SimdCmp",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList03",
"type": "OpDesc"
},
{
- "issueLat": 1,
+ "opClass": "SimdCvt",
"opLat": 1,
"name": "opList04",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "SimdCvt",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList04",
"type": "OpDesc"
},
{
- "issueLat": 1,
+ "opClass": "SimdMisc",
"opLat": 1,
"name": "opList05",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "SimdMisc",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList05",
"type": "OpDesc"
},
{
- "issueLat": 1,
+ "opClass": "SimdMult",
"opLat": 1,
"name": "opList06",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "SimdMult",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList06",
"type": "OpDesc"
},
{
- "issueLat": 1,
+ "opClass": "SimdMultAcc",
"opLat": 1,
"name": "opList07",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "SimdMultAcc",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList07",
"type": "OpDesc"
},
{
- "issueLat": 1,
+ "opClass": "SimdShift",
"opLat": 1,
"name": "opList08",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "SimdShift",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList08",
"type": "OpDesc"
},
{
- "issueLat": 1,
+ "opClass": "SimdShiftAcc",
"opLat": 1,
"name": "opList09",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "SimdShiftAcc",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList09",
"type": "OpDesc"
},
{
- "issueLat": 1,
+ "opClass": "SimdSqrt",
"opLat": 1,
"name": "opList10",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "SimdSqrt",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList10",
"type": "OpDesc"
},
{
- "issueLat": 1,
+ "opClass": "SimdFloatAdd",
"opLat": 1,
"name": "opList11",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "SimdFloatAdd",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList11",
"type": "OpDesc"
},
{
- "issueLat": 1,
+ "opClass": "SimdFloatAlu",
"opLat": 1,
"name": "opList12",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "SimdFloatAlu",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList12",
"type": "OpDesc"
},
{
- "issueLat": 1,
+ "opClass": "SimdFloatCmp",
"opLat": 1,
"name": "opList13",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "SimdFloatCmp",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList13",
"type": "OpDesc"
},
{
- "issueLat": 1,
+ "opClass": "SimdFloatCvt",
"opLat": 1,
"name": "opList14",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "SimdFloatCvt",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList14",
"type": "OpDesc"
},
{
- "issueLat": 1,
+ "opClass": "SimdFloatDiv",
"opLat": 1,
"name": "opList15",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "SimdFloatDiv",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList15",
"type": "OpDesc"
},
{
- "issueLat": 1,
+ "opClass": "SimdFloatMisc",
"opLat": 1,
"name": "opList16",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "SimdFloatMisc",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList16",
"type": "OpDesc"
},
{
- "issueLat": 1,
+ "opClass": "SimdFloatMult",
"opLat": 1,
"name": "opList17",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "SimdFloatMult",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList17",
"type": "OpDesc"
},
{
- "issueLat": 1,
+ "opClass": "SimdFloatMultAcc",
"opLat": 1,
"name": "opList18",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "SimdFloatMultAcc",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList18",
"type": "OpDesc"
},
{
- "issueLat": 1,
+ "opClass": "SimdFloatSqrt",
"opLat": 1,
"name": "opList19",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "SimdFloatSqrt",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList5.opList19",
"type": "OpDesc"
@@ -2469,11 +2465,11 @@
"count": 0,
"opList": [
{
- "issueLat": 1,
+ "opClass": "MemWrite",
"opLat": 1,
"name": "opList",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "MemWrite",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList6.opList",
"type": "OpDesc"
@@ -2489,21 +2485,21 @@
"count": 4,
"opList": [
{
- "issueLat": 1,
+ "opClass": "MemRead",
"opLat": 1,
"name": "opList0",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "MemRead",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList7.opList0",
"type": "OpDesc"
},
{
- "issueLat": 1,
+ "opClass": "MemWrite",
"opLat": 1,
"name": "opList1",
+ "pipelined": true,
"eventq_index": 0,
- "opClass": "MemWrite",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList7.opList1",
"type": "OpDesc"
@@ -2519,11 +2515,11 @@
"count": 1,
"opList": [
{
- "issueLat": 3,
+ "opClass": "IprAccess",
"opLat": 3,
"name": "opList",
+ "pipelined": false,
"eventq_index": 0,
- "opClass": "IprAccess",
"cxx_class": "OpDesc",
"path": "system.cpu2.fuPool.FUList8.opList",
"type": "OpDesc"
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr
index d3a4ec20a..69801740a 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr
@@ -30,17 +30,15 @@ Command: 0, Timestamp: 12359, Bank: 3
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is already active!
-Command: 0, Timestamp: 10918, Bank: 5
+Command: 0, Timestamp: 10565, Bank: 5
WARNING: Bank is already active!
-Command: 0, Timestamp: 7932, Bank: 1
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+Command: 0, Timestamp: 7170, Bank: 1
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is already active!
-Command: 0, Timestamp: 6831, Bank: 2
+Command: 0, Timestamp: 6448, Bank: 2
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -54,9 +52,7 @@ Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is already active!
-Command: 0, Timestamp: 6838, Bank: 1
-WARNING: Bank is already active!
-Command: 0, Timestamp: 12183, Bank: 4
+Command: 0, Timestamp: 7090, Bank: 1
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -95,10 +91,12 @@ Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+Command: 0, Timestamp: 10421, Bank: 2
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9326, Bank: 7
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6590, Bank: 6
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout
index d5a88ab7b..88f772da2 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Apr 22 2015 08:10:29
-gem5 started Apr 22 2015 10:40:08
-gem5 executing on phenom
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full
+gem5 compiled Jul 6 2015 14:29:04
+gem5 started Jul 7 2015 09:32:35
+gem5 executing on e104799-lin
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /work/gem5/outgoing/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full
Global frequency set at 1000000000000 ticks per second
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
index 99542453a..9aafe0fe8 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
@@ -1,157 +1,157 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 5.134211 # Number of seconds simulated
-sim_ticks 5134211428000 # Number of ticks simulated
-final_tick 5134211428000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.141168 # Number of seconds simulated
+sim_ticks 5141168437500 # Number of ticks simulated
+final_tick 5141168437500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 263536 # Simulator instruction rate (inst/s)
-host_op_rate 523907 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5540037627 # Simulator tick rate (ticks/s)
-host_mem_usage 1021876 # Number of bytes of host memory used
-host_seconds 926.75 # Real time elapsed on the host
-sim_insts 244230745 # Number of instructions simulated
-sim_ops 485529516 # Number of ops (including micro ops) simulated
+host_inst_rate 561125 # Simulator instruction rate (inst/s)
+host_op_rate 1115525 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 11816760555 # Simulator tick rate (ticks/s)
+host_mem_usage 973408 # Number of bytes of host memory used
+host_seconds 435.07 # Real time elapsed on the host
+sim_insts 244131065 # Number of instructions simulated
+sim_ops 485336254 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 393536 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 5140544 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 149632 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 1859072 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker 2496 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 377472 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4958144 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 201472 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 2034880 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker 2368 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 422208 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 3469952 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 383296 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 3456256 # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11466176 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 393536 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 149632 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 422208 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 965376 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9230336 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9230336 # Number of bytes written to this memory
+system.physmem.bytes_read::total 11442624 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 377472 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 201472 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 383296 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 962240 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9198208 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9198208 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 6149 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 80321 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 2338 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 29048 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker 39 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 5898 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 77471 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 3148 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 31795 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker 37 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 6597 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 54218 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 5989 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 54004 # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 179159 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 144224 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 144224 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 178791 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 143722 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 143722 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 76650 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1001233 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 29144 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 362095 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker 486 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 73421 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 964400 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 39188 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 395801 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker 461 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 82234 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 675849 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide 5522 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2233289 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 76650 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 29144 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 82234 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 188028 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1797810 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1797810 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1797810 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 74554 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 672271 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide 5515 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2225685 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 73421 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 39188 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 74554 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 187164 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1789128 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1789128 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1789128 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 76650 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 1001233 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 29144 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 362095 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker 486 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 73421 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 964400 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 39188 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 395801 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker 461 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 82234 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 675849 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 5522 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4031099 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 92684 # Number of read requests accepted
-system.physmem.writeReqs 79104 # Number of write requests accepted
-system.physmem.readBursts 92684 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 79104 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 5924224 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue
-system.physmem.bytesWritten 5060672 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 5931776 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 5062656 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu2.inst 74554 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 672271 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 5515 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4014813 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 95417 # Number of read requests accepted
+system.physmem.writeReqs 81462 # Number of write requests accepted
+system.physmem.readBursts 95417 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 81462 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 6099840 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue
+system.physmem.bytesWritten 5213440 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 6106688 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 5213568 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 20933 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 6439 # Per bank write bursts
-system.physmem.perBankRdBursts::1 5501 # Per bank write bursts
-system.physmem.perBankRdBursts::2 5319 # Per bank write bursts
-system.physmem.perBankRdBursts::3 5591 # Per bank write bursts
-system.physmem.perBankRdBursts::4 5862 # Per bank write bursts
-system.physmem.perBankRdBursts::5 5383 # Per bank write bursts
-system.physmem.perBankRdBursts::6 5425 # Per bank write bursts
-system.physmem.perBankRdBursts::7 4840 # Per bank write bursts
-system.physmem.perBankRdBursts::8 6025 # Per bank write bursts
-system.physmem.perBankRdBursts::9 5959 # Per bank write bursts
-system.physmem.perBankRdBursts::10 5660 # Per bank write bursts
-system.physmem.perBankRdBursts::11 5754 # Per bank write bursts
-system.physmem.perBankRdBursts::12 5715 # Per bank write bursts
-system.physmem.perBankRdBursts::13 6523 # Per bank write bursts
-system.physmem.perBankRdBursts::14 5966 # Per bank write bursts
-system.physmem.perBankRdBursts::15 6604 # Per bank write bursts
-system.physmem.perBankWrBursts::0 5842 # Per bank write bursts
-system.physmem.perBankWrBursts::1 5111 # Per bank write bursts
-system.physmem.perBankWrBursts::2 4865 # Per bank write bursts
-system.physmem.perBankWrBursts::3 5025 # Per bank write bursts
-system.physmem.perBankWrBursts::4 5489 # Per bank write bursts
-system.physmem.perBankWrBursts::5 4924 # Per bank write bursts
-system.physmem.perBankWrBursts::6 4816 # Per bank write bursts
-system.physmem.perBankWrBursts::7 4154 # Per bank write bursts
-system.physmem.perBankWrBursts::8 4431 # Per bank write bursts
-system.physmem.perBankWrBursts::9 4666 # Per bank write bursts
-system.physmem.perBankWrBursts::10 4446 # Per bank write bursts
-system.physmem.perBankWrBursts::11 4728 # Per bank write bursts
-system.physmem.perBankWrBursts::12 4725 # Per bank write bursts
-system.physmem.perBankWrBursts::13 5504 # Per bank write bursts
-system.physmem.perBankWrBursts::14 4686 # Per bank write bursts
-system.physmem.perBankWrBursts::15 5661 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 21330 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 6364 # Per bank write bursts
+system.physmem.perBankRdBursts::1 5596 # Per bank write bursts
+system.physmem.perBankRdBursts::2 5691 # Per bank write bursts
+system.physmem.perBankRdBursts::3 5690 # Per bank write bursts
+system.physmem.perBankRdBursts::4 6222 # Per bank write bursts
+system.physmem.perBankRdBursts::5 5617 # Per bank write bursts
+system.physmem.perBankRdBursts::6 5512 # Per bank write bursts
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+system.physmem.wrPerTurnAround::16-19 3652 85.85% 87.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 58 1.36% 89.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 99 2.33% 91.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 64 1.50% 93.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 41 0.96% 94.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 93 2.19% 96.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 12 0.28% 96.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 8 0.19% 96.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 11 0.26% 96.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 4 0.09% 97.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 6 0.14% 97.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 2 0.05% 97.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 101 2.37% 99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 2 0.05% 99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 3 0.07% 99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 1 0.02% 99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 1 0.02% 99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 1 0.02% 99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 1 0.02% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 6 0.14% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 1 0.02% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 1 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 4254 # Writes before turning the bus around for reads
+system.physmem.totQLat 1082395298 # Total ticks spent queuing
+system.physmem.totMemAccLat 2869457798 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 476550000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 11356.58 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30152.05 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.15 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.16 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.99 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 30106.58 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.19 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.01 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.01 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 9.29 # Average write queue length when enqueuing
-system.physmem.readRowHits 74063 # Number of row buffer hits during reads
-system.physmem.writeRowHits 56883 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 80.01 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 71.91 # Row buffer hit rate for writes
-system.physmem.avgGap 29881081.46 # Average gap between requests
-system.physmem.pageHitRate 76.28 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 149294880 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 81184125 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 345992400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 260664480 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 250017250080 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 94809930840 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 2241062736000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 2586727052805 # Total energy per rank (pJ)
-system.physmem_0.averagePower 667.763806 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 3682666821734 # Time in different power states
-system.physmem_0.memoryStateTime::REF 127820680000 # Time in different power states
+system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 9.18 # Average write queue length when enqueuing
+system.physmem.readRowHits 76601 # Number of row buffer hits during reads
+system.physmem.writeRowHits 58731 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 80.37 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 72.10 # Row buffer hit rate for writes
+system.physmem.avgGap 29060364.94 # Average gap between requests
+system.physmem.pageHitRate 76.56 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 152477640 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 82953750 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 356538000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 270228960 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 250406807040 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 95253378300 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 2241273732750 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 2587796116440 # Total energy per rank (pJ)
+system.physmem_0.averagePower 667.867379 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 3687953773966 # Time in different power states
+system.physmem_0.memoryStateTime::REF 128019840000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 17822753766 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 18290517534 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 158336640 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 86183625 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 376006800 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 251728560 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 250017250080 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 95265143955 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 2233496235000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 2579650884660 # Total energy per rank (pJ)
-system.physmem_1.averagePower 667.996985 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 3682005807728 # Time in different power states
-system.physmem_1.memoryStateTime::REF 127820680000 # Time in different power states
+system.physmem_1.actEnergy 160786080 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 87503625 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 386872200 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 257631840 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 250406807040 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 95644179990 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 2237947569750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 2584891350525 # Total energy per rank (pJ)
+system.physmem_1.averagePower 667.974891 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 3687410747240 # Time in different power states
+system.physmem_1.memoryStateTime::REF 128019840000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 18463901522 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 18840857760 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu0.numCycles 814812843 # number of cpu cycles simulated
+system.cpu0.numCycles 818622179 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 70855773 # Number of instructions committed
-system.cpu0.committedOps 144639705 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 132581707 # Number of integer alu accesses
+system.cpu0.committedInsts 70465386 # Number of instructions committed
+system.cpu0.committedOps 143948929 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 131896754 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu0.num_func_calls 911803 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 14069363 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 132581707 # number of integer instructions
+system.cpu0.num_func_calls 904463 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 13997547 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 131896754 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
-system.cpu0.num_int_register_reads 242934374 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 114063964 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 241558700 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 113520418 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 82574901 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 55200628 # number of times the CC registers were written
-system.cpu0.num_mem_refs 13389972 # number of memory refs
-system.cpu0.num_load_insts 9966183 # Number of load instructions
-system.cpu0.num_store_insts 3423789 # Number of store instructions
-system.cpu0.num_idle_cycles 774643417.179050 # Number of idle cycles
-system.cpu0.num_busy_cycles 40169425.820950 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.049299 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.950701 # Percentage of idle cycles
-system.cpu0.Branches 15322983 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 87668 0.06% 0.06% # Class of executed instruction
-system.cpu0.op_class::IntAlu 131058913 90.61% 90.67% # Class of executed instruction
-system.cpu0.op_class::IntMult 57724 0.04% 90.71% # Class of executed instruction
-system.cpu0.op_class::IntDiv 47555 0.03% 90.74% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 90.74% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 90.74% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 90.74% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 90.74% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 90.74% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 90.74% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 90.74% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 90.74% # Class of executed instruction
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-system.cpu0.op_class::SimdMisc 0 0.00% 90.74% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 90.74% # Class of executed instruction
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-system.cpu0.op_class::SimdSqrt 0 0.00% 90.74% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.74% # Class of executed instruction
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-system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.74% # Class of executed instruction
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-system.cpu0.op_class::MemRead 9964546 6.89% 97.63% # Class of executed instruction
-system.cpu0.op_class::MemWrite 3423789 2.37% 100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads 82096977 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 54912679 # number of times the CC registers were written
+system.cpu0.num_mem_refs 13231012 # number of memory refs
+system.cpu0.num_load_insts 9870869 # Number of load instructions
+system.cpu0.num_store_insts 3360143 # Number of store instructions
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+system.cpu0.not_idle_fraction 0.050850 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.949150 # Percentage of idle cycles
+system.cpu0.Branches 15238298 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 84207 0.06% 0.06% # Class of executed instruction
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system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 144640195 # Class of executed instruction
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system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements 1639692 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 511.999446 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 19677629 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 1640204 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 11.997062 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements 1638295 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 511.999362 # Cycle average of tags in use
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+system.cpu0.dcache.tags.avg_refs 12.004605 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 231.527826 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data 256.098734 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data 24.372886 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.452203 # Average percentage of cache occupancy
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system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu0.dcache.ReadReq_hits::cpu1.data 2413671 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data 4330956 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 11526744 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 3296356 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data 1699008 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data 3093469 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 8088833 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 19899 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data 9911 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data 30439 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 60249 # number of SoftPFReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 8078473 # number of demand (read+write) hits
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-system.cpu0.dcache.demand_hits::total 19615577 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 8098372 # number of overall hits
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-system.cpu0.dcache.ReadReq_misses::cpu0.data 346307 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data 159141 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data 827752 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 1333200 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 123952 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data 63357 # number of WriteReq misses
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system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 35137560 # Number of instructions committed
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-system.cpu1.num_conditional_control_insts 6463819 # number of instructions that are conditional controls
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system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 35859650 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 26723526 # number of times the CC registers were written
-system.cpu1.num_mem_refs 4592942 # number of memory refs
-system.cpu1.num_load_insts 2829969 # Number of load instructions
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-system.cpu1.num_busy_cycles 122300604.237089 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.046930 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.953070 # Percentage of idle cycles
-system.cpu1.Branches 7109683 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 33619 0.05% 0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu 63651336 93.16% 93.21% # Class of executed instruction
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-system.cpu1.op_class::IntDiv 22176 0.03% 93.28% # Class of executed instruction
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-system.cpu1.op_class::FloatCmp 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.28% # Class of executed instruction
-system.cpu1.op_class::MemRead 2828254 4.14% 97.42% # Class of executed instruction
-system.cpu1.op_class::MemWrite 1762973 2.58% 100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads 36729292 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 27266794 # number of times the CC registers were written
+system.cpu1.num_mem_refs 4880817 # number of memory refs
+system.cpu1.num_load_insts 2999293 # Number of load instructions
+system.cpu1.num_store_insts 1881524 # Number of store instructions
+system.cpu1.num_idle_cycles 2477690884.667310 # Number of idle cycles
+system.cpu1.num_busy_cycles 129469822.332690 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.049659 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.950341 # Percentage of idle cycles
+system.cpu1.Branches 7272679 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 37847 0.05% 0.05% # Class of executed instruction
+system.cpu1.op_class::IntAlu 64724112 92.87% 92.92% # Class of executed instruction
+system.cpu1.op_class::IntMult 30276 0.04% 92.96% # Class of executed instruction
+system.cpu1.op_class::IntDiv 24690 0.04% 93.00% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.00% # Class of executed instruction
+system.cpu1.op_class::MemRead 2997578 4.30% 97.30% # Class of executed instruction
+system.cpu1.op_class::MemWrite 1881524 2.70% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 68325979 # Class of executed instruction
+system.cpu1.op_class::total 69696027 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.branchPred.lookups 29728292 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 29728292 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 354491 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 26875418 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 26145153 # Number of BTB hits
+system.cpu2.branchPred.lookups 29601975 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 29601975 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 343203 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 26791839 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 26086008 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 97.282777 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 627673 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 71339 # Number of incorrect RAS predictions.
-system.cpu2.numCycles 156747191 # number of cpu cycles simulated
+system.cpu2.branchPred.BTBHitPct 97.365500 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 612616 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 69103 # Number of incorrect RAS predictions.
+system.cpu2.numCycles 155854675 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 11575217 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 146531331 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 29728292 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 26772826 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 143455759 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 740896 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles 117693 # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles 8882 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 9184 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 67495 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 36 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 614 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 3714591 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 185121 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes 4402 # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples 155604677 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.852545 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 3.032784 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles 11239571 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 145909604 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 29601975 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 26698624 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 143043306 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 717621 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles 104333 # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles 8734 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 9529 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 59780 # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles 15 # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles 573 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 3640195 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 178300 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes 3755 # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples 154824000 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.854554 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 3.033337 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 99528214 63.96% 63.96% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 894883 0.58% 64.54% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 23827863 15.31% 79.85% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 616054 0.40% 80.25% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 865023 0.56% 80.80% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 874152 0.56% 81.36% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 593045 0.38% 81.75% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 766815 0.49% 82.24% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 27638628 17.76% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 98922679 63.89% 63.89% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 904691 0.58% 64.48% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 23796776 15.37% 79.85% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 606779 0.39% 80.24% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 848220 0.55% 80.79% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 866864 0.56% 81.35% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 584872 0.38% 81.73% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 770506 0.50% 82.22% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 27522613 17.78% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 155604677 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.189658 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 0.934826 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 10653655 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 94438460 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 23846115 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 5077401 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 371099 # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts 285226302 # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles 371099 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 12813669 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 77065666 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 4747202 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 26484696 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 12904465 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 283889044 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 204785 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 5893747 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents 54074 # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents 4792782 # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands 339006774 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 620283621 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 380802622 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 280 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 325933868 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 13072904 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 167839 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 169378 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 24708176 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 6969767 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 3922969 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 416514 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 341941 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 281777756 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 433047 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 279489336 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 112446 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 9646678 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 14520235 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 68066 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 155604677 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.796150 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 2.396491 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 154824000 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.189933 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 0.936190 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 10345116 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 94152744 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 23674011 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 5064791 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 359462 # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts 284127557 # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles 359462 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 12498058 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 76923253 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 4647068 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 26307426 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 12860925 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 282811274 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 202798 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 5895071 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents 49763 # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents 4758021 # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands 337796411 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 617680830 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 379222273 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 178 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 324911571 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 12884840 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 166150 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 167782 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 24657180 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 6871363 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 3845087 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 401055 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 322271 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 280748482 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 429304 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 278478009 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 108269 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 9486121 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 14384380 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 66849 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 154824000 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.798675 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 2.397594 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 92126087 59.21% 59.21% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 5408193 3.48% 62.68% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 3871909 2.49% 65.17% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 3896687 2.50% 67.67% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 22645736 14.55% 82.23% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 2817206 1.81% 84.04% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 24121295 15.50% 99.54% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 489992 0.31% 99.85% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 227572 0.15% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 91620665 59.18% 59.18% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 5352321 3.46% 62.63% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 3836914 2.48% 65.11% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 3858930 2.49% 67.61% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 22596079 14.59% 82.20% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 2789392 1.80% 84.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 24067258 15.54% 99.55% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 479282 0.31% 99.86% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 223159 0.14% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 155604677 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 154824000 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 1782744 86.25% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 2 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 86.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 219490 10.62% 96.87% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 64665 3.13% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 1768977 86.18% 86.18% # attempts to use FU when none available
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+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 86.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 86.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 86.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 86.18% # attempts to use FU when none available
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+system.cpu2.iq.fu_full::SimdMult 0 0.00% 86.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 86.18% # attempts to use FU when none available
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+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 86.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 86.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 86.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 86.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 86.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 86.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 86.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 86.18% # attempts to use FU when none available
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+system.cpu2.iq.fu_full::MemRead 219653 10.70% 96.88% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 63974 3.12% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass 84223 0.03% 0.03% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 268409283 96.04% 96.07% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 60791 0.02% 96.09% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 54867 0.02% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 128 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.11% # Type of FU issued
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-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 7262488 2.60% 98.71% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 3617556 1.29% 100.00% # Type of FU issued
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+system.cpu2.iq.FU_type_0::IntDiv 54123 0.02% 96.15% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.15% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.15% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 92 0.00% 96.15% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.15% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.15% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.15% # Type of FU issued
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+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.15% # Type of FU issued
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+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.15% # Type of FU issued
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+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.15% # Type of FU issued
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+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.15% # Type of FU issued
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+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.15% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.15% # Type of FU issued
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+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.15% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.15% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.15% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.15% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.15% # Type of FU issued
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system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 279489336 # Type of FU issued
-system.cpu2.iq.rate 1.783058 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 2066901 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.007395 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 716762296 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 291861984 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 277802443 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 399 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 402 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 161 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 281471819 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 195 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 741069 # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total 278478009 # Type of FU issued
+system.cpu2.iq.rate 1.786780 # Inst issue rate
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+system.cpu2.iq.fu_busy_rate 0.007371 # FU busy rate (busy events/executed inst)
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+system.cpu2.iq.int_inst_queue_writes 290668152 # Number of integer instruction queue writes
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+system.cpu2.iq.fp_inst_queue_reads 256 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 236 # Number of floating instruction queue writes
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+system.cpu2.iq.fp_alu_accesses 128 # Number of floating point alu accesses
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system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 1314442 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 6549 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 5531 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 685228 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 1286395 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 6167 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 5109 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 663777 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 750208 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 28435 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads 750358 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 29268 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 371099 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 70840326 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 3147966 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 282210803 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 45613 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 6969767 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 3922969 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 254598 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 166407 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 2652713 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 5531 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 201920 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 210112 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 412032 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 278837771 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 7102995 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 592219 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles 359462 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 70735172 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 3134720 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 281177786 # Number of instructions dispatched to IQ
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+system.cpu2.iew.iewIQFullEvents 166997 # Number of times the IQ has become full, causing a stall
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+system.cpu2.iew.memOrderViolationEvents 5109 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 196795 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 202269 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 399064 # Number of branch mispredicts detected at execute
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+system.cpu2.iew.iewExecSquashedInsts 573017 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 0 # number of nop insts executed
-system.cpu2.iew.exec_refs 10623704 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 28332312 # Number of branches executed
-system.cpu2.iew.exec_stores 3520709 # Number of stores executed
-system.cpu2.iew.exec_rate 1.778901 # Inst execution rate
-system.cpu2.iew.wb_sent 278631802 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 277802604 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 216492114 # num instructions producing a value
-system.cpu2.iew.wb_consumers 355079818 # num instructions consuming a value
+system.cpu2.iew.exec_refs 10469775 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 28224309 # Number of branches executed
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+system.cpu2.iew.exec_rate 1.782738 # Inst execution rate
+system.cpu2.iew.wb_sent 277647788 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 276821632 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 215782455 # num instructions producing a value
+system.cpu2.iew.wb_consumers 353891684 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 1.772297 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.609700 # average fanout of values written-back
+system.cpu2.iew.wb_rate 1.776152 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.609742 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 9642578 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 364981 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 357554 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 154160156 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.768058 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 2.650606 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 9482299 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 362455 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 346445 # The number of times a branch was mispredicted
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+system.cpu2.commit.committed_per_cycle::mean 1.771035 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 2.652208 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 95860610 62.18% 62.18% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 4461430 2.89% 65.08% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1337416 0.87% 65.94% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 24820120 16.10% 82.04% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 1009976 0.66% 82.70% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 732580 0.48% 83.17% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 443548 0.29% 83.46% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 23352402 15.15% 98.61% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 2142074 1.39% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 95336138 62.15% 62.15% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 4415580 2.88% 65.02% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1307869 0.85% 65.88% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 24753928 16.14% 82.01% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 995070 0.65% 82.66% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 727248 0.47% 83.13% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 439603 0.29% 83.42% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 23319103 15.20% 98.62% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 2113838 1.38% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 154160156 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 138237412 # Number of instructions committed
-system.cpu2.commit.committedOps 272564120 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 153408377 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 137757751 # Number of instructions committed
+system.cpu2.commit.committedOps 271691665 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 8893065 # Number of memory references committed
-system.cpu2.commit.loads 5655324 # Number of loads committed
-system.cpu2.commit.membars 162767 # Number of memory barriers committed
-system.cpu2.commit.branches 27901240 # Number of branches committed
+system.cpu2.commit.refs 8766278 # Number of memory references committed
+system.cpu2.commit.loads 5584968 # Number of loads committed
+system.cpu2.commit.membars 161958 # Number of memory barriers committed
+system.cpu2.commit.branches 27804222 # Number of branches committed
system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 249166189 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 462772 # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass 50638 0.02% 0.02% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu 263510022 96.68% 96.70% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult 58397 0.02% 96.72% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv 52041 0.02% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.74% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead 5655265 2.07% 98.81% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite 3237741 1.19% 100.00% # Class of committed instruction
+system.cpu2.commit.int_insts 248326046 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 453891 # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass 49969 0.02% 0.02% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu 262767573 96.72% 96.73% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult 56460 0.02% 96.75% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv 51419 0.02% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead 5584918 2.06% 98.83% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite 3181310 1.17% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total 272564120 # Class of committed instruction
-system.cpu2.commit.bw_lim_events 2142074 # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads 434194585 # The number of ROB reads
-system.cpu2.rob.rob_writes 565865422 # The number of ROB writes
-system.cpu2.timesIdled 127222 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 1142514 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 4899644826 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 138237412 # Number of Instructions Simulated
-system.cpu2.committedOps 272564120 # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi 1.133898 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 1.133898 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.881913 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.881913 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 371610814 # number of integer regfile reads
-system.cpu2.int_regfile_writes 222643670 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 73073 # number of floating regfile reads
+system.cpu2.commit.op_class_0::total 271691665 # Class of committed instruction
+system.cpu2.commit.bw_lim_events 2113838 # number cycles where commit BW limit reached
+system.cpu2.rob.rob_reads 432438077 # The number of ROB reads
+system.cpu2.rob.rob_writes 563770770 # The number of ROB writes
+system.cpu2.timesIdled 121162 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 1030675 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 4911308393 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 137757751 # Number of Instructions Simulated
+system.cpu2.committedOps 271691665 # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi 1.131368 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 1.131368 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.883886 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.883886 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 370162227 # number of integer regfile reads
+system.cpu2.int_regfile_writes 221868711 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 73082 # number of floating regfile reads
system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes
-system.cpu2.cc_regfile_reads 141701796 # number of cc regfile reads
-system.cpu2.cc_regfile_writes 108796323 # number of cc regfile writes
-system.cpu2.misc_regfile_reads 90941344 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 144983 # number of misc regfile writes
-system.iobus.trans_dist::ReadReq 3552121 # Transaction distribution
-system.iobus.trans_dist::ReadResp 3552121 # Transaction distribution
-system.iobus.trans_dist::WriteReq 57703 # Transaction distribution
-system.iobus.trans_dist::WriteResp 57703 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1657 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1657 # Transaction distribution
+system.cpu2.cc_regfile_reads 141178662 # number of cc regfile reads
+system.cpu2.cc_regfile_writes 108439379 # number of cc regfile writes
+system.cpu2.misc_regfile_reads 90543264 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 143975 # number of misc regfile writes
+system.iobus.trans_dist::ReadReq 3552152 # Transaction distribution
+system.iobus.trans_dist::ReadResp 3552152 # Transaction distribution
+system.iobus.trans_dist::WriteReq 57748 # Transaction distribution
+system.iobus.trans_dist::WriteResp 57748 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1661 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1661 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
@@ -1161,15 +1163,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 7124404 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3314 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3314 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 7222962 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 7124542 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3322 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3322 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 7223122 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
@@ -1185,19 +1187,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 3568437 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027760 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027760 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6628 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6628 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 6602825 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 2786496 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total 3568515 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6644 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6644 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 6602975 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 2788160 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 5677000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 5737000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
@@ -1215,58 +1217,58 @@ system.iobus.reqLayer10.occupancy 441000 # La
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 11327000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy 11321000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 4000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 104116682 # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy 105499646 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 300127000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 300163000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 23084000 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 23378000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 1172000 # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy 1173000 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 47567 # number of replacements
-system.iocache.tags.tagsinuse 0.081431 # Cycle average of tags in use
+system.iocache.tags.replacements 47574 # number of replacements
+system.iocache.tags.tagsinuse 0.102984 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 47583 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 5000591236509 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.081431 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005089 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.005089 # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.102984 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006437 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.006437 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 428598 # Number of tag accesses
-system.iocache.tags.data_accesses 428598 # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide 902 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 902 # number of ReadReq misses
+system.iocache.tags.tag_accesses 428661 # Number of tag accesses
+system.iocache.tags.data_accesses 428661 # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 909 # number of ReadReq misses
system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 902 # number of demand (read+write) misses
-system.iocache.demand_misses::total 902 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 902 # number of overall misses
-system.iocache.overall_misses::total 902 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 121586746 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 121586746 # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 2354972936 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 2354972936 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 121586746 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 121586746 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 121586746 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 121586746 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 902 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 902 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide 909 # number of demand (read+write) misses
+system.iocache.demand_misses::total 909 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 909 # number of overall misses
+system.iocache.overall_misses::total 909 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 126015772 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 126015772 # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 2387409874 # number of WriteLineReq miss cycles
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@@ -1275,337 +1277,337 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1
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+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 188788.548888 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 178755.489022 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 152286.703667 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 150297.098054 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 151242.472487 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 5067078 # Transaction distribution
-system.membus.trans_dist::ReadResp 5116429 # Transaction distribution
-system.membus.trans_dist::WriteReq 13886 # Transaction distribution
-system.membus.trans_dist::WriteResp 13886 # Transaction distribution
-system.membus.trans_dist::Writeback 144224 # Transaction distribution
-system.membus.trans_dist::CleanEvict 8915 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 1691 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 1691 # Transaction distribution
-system.membus.trans_dist::ReadExReq 130923 # Transaction distribution
-system.membus.trans_dist::ReadExResp 130923 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 49352 # Transaction distribution
-system.membus.trans_dist::MessageReq 1657 # Transaction distribution
-system.membus.trans_dist::MessageResp 1657 # Transaction distribution
-system.membus.trans_dist::BadAddressError 1 # Transaction distribution
+system.membus.trans_dist::ReadReq 5067102 # Transaction distribution
+system.membus.trans_dist::ReadResp 5116344 # Transaction distribution
+system.membus.trans_dist::WriteReq 13938 # Transaction distribution
+system.membus.trans_dist::WriteResp 13938 # Transaction distribution
+system.membus.trans_dist::Writeback 143722 # Transaction distribution
+system.membus.trans_dist::CleanEvict 8694 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 1684 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 1684 # Transaction distribution
+system.membus.trans_dist::ReadExReq 130671 # Transaction distribution
+system.membus.trans_dist::ReadExResp 130671 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 49245 # Transaction distribution
+system.membus.trans_dist::MessageReq 1661 # Transaction distribution
+system.membus.trans_dist::MessageResp 1661 # Transaction distribution
+system.membus.trans_dist::BadAddressError 3 # Transaction distribution
system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3314 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total 3314 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7124404 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3037524 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 467564 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 10629494 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3322 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total 3322 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7124542 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3037538 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 466123 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 6 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 10628209 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142133 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 142133 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 10774941 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6628 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total 6628 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3568437 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6075045 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17691840 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 27335322 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3025024 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 3025024 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 30366974 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 812 # Total snoops (count)
-system.membus.snoop_fanout::samples 5464824 # Request fanout histogram
-system.membus.snoop_fanout::mean 1.000303 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.017410 # Request fanout histogram
+system.membus.pkt_count::total 10773664 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6644 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total 6644 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3568515 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6075073 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17638016 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 27281604 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3024768 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 3024768 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 30313016 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 794 # Total snoops (count)
+system.membus.snoop_fanout::samples 5463823 # Request fanout histogram
+system.membus.snoop_fanout::mean 1.000304 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.017433 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 5463167 99.97% 99.97% # Request fanout histogram
-system.membus.snoop_fanout::2 1657 0.03% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 5462162 99.97% 99.97% # Request fanout histogram
+system.membus.snoop_fanout::2 1661 0.03% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 2 # Request fanout histogram
-system.membus.snoop_fanout::total 5464824 # Request fanout histogram
-system.membus.reqLayer0.occupancy 233042000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 5463823 # Request fanout histogram
+system.membus.reqLayer0.occupancy 233077000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 304115000 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 304111500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 2344000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 2346000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 525464887 # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy 540335137 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy 4500 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer0.occupancy 1172000 # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy 1173000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1340471277 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 1355053149 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer4.occupancy 38659394 # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy 39163714 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
@@ -1839,54 +1847,54 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq 5232649 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 7464311 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 13888 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 13888 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 1628034 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 977588 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 1686 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 1686 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 291075 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 291075 # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq 882303 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 1349887 # Transaction distribution
-system.toL2Bus.trans_dist::MessageReq 1172 # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError 1 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 19960 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2645849 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15085510 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 77708 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 228805 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 18037872 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56466048 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213762586 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 290440 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 837080 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 271356154 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 159100 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 10426288 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.028740 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.167075 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 5228129 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 7456138 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 13940 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 13940 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 1629241 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 974525 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 1670 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 1670 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 290245 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 290245 # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq 879201 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 1349341 # Transaction distribution
+system.toL2Bus.trans_dist::MessageReq 1173 # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError 3 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq 20232 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2636643 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15081470 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 73733 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 221081 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 18012927 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56268224 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213600772 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 270696 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 799584 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 270939276 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 164260 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 10415382 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.028580 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.166622 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 10126637 97.13% 97.13% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 299651 2.87% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 10117713 97.14% 97.14% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 297669 2.86% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 10426288 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 2853173500 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 10415382 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 2866107499 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 340500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 883247245 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 884323704 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 1934319786 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 1946611318 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 28757491 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 27584988 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 101435667 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 99698688 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed