diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
| commit | 10b70d54529f0a44dc088c9271d9ecf3a8ffe68a (patch) | |
| tree | 482dff6407c0b1c8cf1711f33d8ecad6acbf6c7f /tests/long | |
| parent | 9cbe1cb653428a2298644579ddf82c46272683d4 (diff) | |
| download | gem5-10b70d54529f0a44dc088c9271d9ecf3a8ffe68a.tar.xz | |
stats: Update stats for unified cache configuration
This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.
Diffstat (limited to 'tests/long')
43 files changed, 17434 insertions, 17054 deletions
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt index 77611891d..f82052a04 100644 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt @@ -1,24 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.116889 # Number of seconds simulated -sim_ticks 2233777512 # Number of ticks simulated -final_tick 2233777512 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.233778 # Number of seconds simulated +sim_ticks 4467555024 # Number of ticks simulated +final_tick 4467555024 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 2000000000 # Frequency of simulated ticks -host_inst_rate 2751599 # Simulator instruction rate (inst/s) -host_op_rate 2752680 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2758381 # Simulator tick rate (ticks/s) -host_mem_usage 518836 # Number of bytes of host memory used -host_seconds 809.81 # Real time elapsed on the host +host_inst_rate 2515301 # Simulator instruction rate (inst/s) +host_op_rate 2516290 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5043002 # Simulator tick rate (ticks/s) +host_mem_usage 518832 # Number of bytes of host memory used +host_seconds 885.89 # Real time elapsed on the host sim_insts 2228284650 # Number of instructions simulated sim_ops 2229160714 # Number of ops (including micro ops) simulated system.hypervisor_desc.bytes_read::cpu.data 16792 # Number of bytes read from this memory system.hypervisor_desc.bytes_read::total 16792 # Number of bytes read from this memory system.hypervisor_desc.num_reads::cpu.data 9024 # Number of read requests responded to by this memory system.hypervisor_desc.num_reads::total 9024 # Number of read requests responded to by this memory -system.hypervisor_desc.bw_read::cpu.data 15035 # Total read bandwidth from this memory (bytes/s) -system.hypervisor_desc.bw_read::total 15035 # Total read bandwidth from this memory (bytes/s) -system.hypervisor_desc.bw_total::cpu.data 15035 # Total bandwidth to/from this memory (bytes/s) -system.hypervisor_desc.bw_total::total 15035 # Total bandwidth to/from this memory (bytes/s) +system.hypervisor_desc.bw_read::cpu.data 7517 # Total read bandwidth from this memory (bytes/s) +system.hypervisor_desc.bw_read::total 7517 # Total read bandwidth from this memory (bytes/s) +system.hypervisor_desc.bw_total::cpu.data 7517 # Total bandwidth to/from this memory (bytes/s) +system.hypervisor_desc.bw_total::total 7517 # Total bandwidth to/from this memory (bytes/s) +system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory +system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory +system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory +system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory +system.partition_desc.bw_read::cpu.data 2169 # Total read bandwidth from this memory (bytes/s) +system.partition_desc.bw_read::total 2169 # Total read bandwidth from this memory (bytes/s) +system.partition_desc.bw_total::cpu.data 2169 # Total bandwidth to/from this memory (bytes/s) +system.partition_desc.bw_total::total 2169 # Total bandwidth to/from this memory (bytes/s) +system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory +system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory +system.rom.bytes_read::total 1128688 # Number of bytes read from this memory +system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory +system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory +system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory +system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory +system.rom.num_reads::total 195123 # Number of read requests responded to by this memory +system.rom.bw_read::cpu.inst 193527 # Total read bandwidth from this memory (bytes/s) +system.rom.bw_read::cpu.data 311755 # Total read bandwidth from this memory (bytes/s) +system.rom.bw_read::total 505282 # Total read bandwidth from this memory (bytes/s) +system.rom.bw_inst_read::cpu.inst 193527 # Instruction read bandwidth from this memory (bytes/s) +system.rom.bw_inst_read::total 193527 # Instruction read bandwidth from this memory (bytes/s) +system.rom.bw_total::cpu.inst 193527 # Total bandwidth to/from this memory (bytes/s) +system.rom.bw_total::cpu.data 311755 # Total bandwidth to/from this memory (bytes/s) +system.rom.bw_total::total 505282 # Total bandwidth to/from this memory (bytes/s) +system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory +system.nvram.bytes_read::total 284 # Number of bytes read from this memory +system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory +system.nvram.bytes_written::total 92 # Number of bytes written to this memory +system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory +system.nvram.num_reads::total 284 # Number of read requests responded to by this memory +system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory +system.nvram.num_writes::total 92 # Number of write requests responded to by this memory +system.nvram.bw_read::cpu.data 127 # Total read bandwidth from this memory (bytes/s) +system.nvram.bw_read::total 127 # Total read bandwidth from this memory (bytes/s) +system.nvram.bw_write::cpu.data 41 # Write bandwidth from this memory (bytes/s) +system.nvram.bw_write::total 41 # Write bandwidth from this memory (bytes/s) +system.nvram.bw_total::cpu.data 168 # Total bandwidth to/from this memory (bytes/s) +system.nvram.bw_total::total 168 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 97534024 # Number of bytes read from this memory system.physmem.bytes_read::total 709825348 # Number of bytes read from this memory @@ -33,24 +71,174 @@ system.physmem.num_writes::cpu.data 1927067 # Nu system.physmem.num_writes::total 1927067 # Number of write requests responded to by this memory system.physmem.num_other::cpu.data 14 # Number of other requests responded to by this memory system.physmem.num_other::total 14 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 548211557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 87326534 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 635538091 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 548211557 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 548211557 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 13788502 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13788502 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 548211557 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 101115036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 649326593 # Total bandwidth to/from this memory (bytes/s) -system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory -system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory -system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory -system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory -system.partition_desc.bw_read::cpu.data 4339 # Total read bandwidth from this memory (bytes/s) -system.partition_desc.bw_read::total 4339 # Total read bandwidth from this memory (bytes/s) -system.partition_desc.bw_total::cpu.data 4339 # Total bandwidth to/from this memory (bytes/s) -system.partition_desc.bw_total::total 4339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 274105779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 43663267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 317769046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 274105779 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 274105779 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6894251 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6894251 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 274105779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 50557518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 324663297 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 0 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 0 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 0 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 0 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 0 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 0 # Sum of mem lat for all requests +system.physmem.totBusLat 0 # Total cycles spent in databus access +system.physmem.totBankLat 0 # Total cycles spent in bank access +system.physmem.avgQLat nan # Average queueing delay per request +system.physmem.avgBankLat nan # Average bank access latency per request +system.physmem.avgBusLat nan # Average bus latency per request +system.physmem.avgMemAccLat nan # Average memory access latency +system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.00 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 0 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate nan # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap nan # Average gap between requests system.physmem2.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory system.physmem2.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory system.physmem2.bytes_read::total 9813991967 # Number of bytes read from this memory @@ -65,46 +253,174 @@ system.physmem2.num_writes::cpu.data 187387796 # Nu system.physmem2.num_writes::total 187387796 # Number of write requests responded to by this memory system.physmem2.num_other::cpu.data 5403067 # Number of other requests responded to by this memory system.physmem2.num_other::total 5403067 # Number of other requests responded to by this memory -system.physmem2.bw_read::cpu.inst 7447569684 # Total read bandwidth from this memory (bytes/s) -system.physmem2.bw_read::cpu.data 1339332247 # Total read bandwidth from this memory (bytes/s) -system.physmem2.bw_read::total 8786901931 # Total read bandwidth from this memory (bytes/s) -system.physmem2.bw_inst_read::cpu.inst 7447569684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem2.bw_inst_read::total 7447569684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem2.bw_write::cpu.data 803364182 # Write bandwidth from this memory (bytes/s) -system.physmem2.bw_write::total 803364182 # Write bandwidth from this memory (bytes/s) -system.physmem2.bw_total::cpu.inst 7447569684 # Total bandwidth to/from this memory (bytes/s) -system.physmem2.bw_total::cpu.data 2142696429 # Total bandwidth to/from this memory (bytes/s) -system.physmem2.bw_total::total 9590266113 # Total bandwidth to/from this memory (bytes/s) -system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory -system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory -system.rom.bytes_read::total 1128688 # Number of bytes read from this memory -system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory -system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory -system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory -system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory -system.rom.num_reads::total 195123 # Number of read requests responded to by this memory -system.rom.bw_read::cpu.inst 387054 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_read::cpu.data 623511 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_read::total 1010564 # Total read bandwidth from this memory (bytes/s) -system.rom.bw_inst_read::cpu.inst 387054 # Instruction read bandwidth from this memory (bytes/s) -system.rom.bw_inst_read::total 387054 # Instruction read bandwidth from this memory (bytes/s) -system.rom.bw_total::cpu.inst 387054 # Total bandwidth to/from this memory (bytes/s) -system.rom.bw_total::cpu.data 623511 # Total bandwidth to/from this memory (bytes/s) -system.rom.bw_total::total 1010564 # Total bandwidth to/from this memory (bytes/s) -system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory -system.nvram.bytes_read::total 284 # Number of bytes read from this memory -system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory -system.nvram.bytes_written::total 92 # Number of bytes written to this memory -system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory -system.nvram.num_reads::total 284 # Number of read requests responded to by this memory -system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory -system.nvram.num_writes::total 92 # Number of write requests responded to by this memory -system.nvram.bw_read::cpu.data 254 # Total read bandwidth from this memory (bytes/s) -system.nvram.bw_read::total 254 # Total read bandwidth from this memory (bytes/s) -system.nvram.bw_write::cpu.data 82 # Write bandwidth from this memory (bytes/s) -system.nvram.bw_write::total 82 # Write bandwidth from this memory (bytes/s) -system.nvram.bw_total::cpu.data 337 # Total bandwidth to/from this memory (bytes/s) -system.nvram.bw_total::total 337 # Total bandwidth to/from this memory (bytes/s) +system.physmem2.bw_read::cpu.inst 3723784842 # Total read bandwidth from this memory (bytes/s) +system.physmem2.bw_read::cpu.data 669666123 # Total read bandwidth from this memory (bytes/s) +system.physmem2.bw_read::total 4393450966 # Total read bandwidth from this memory (bytes/s) +system.physmem2.bw_inst_read::cpu.inst 3723784842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem2.bw_inst_read::total 3723784842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem2.bw_write::cpu.data 401682091 # Write bandwidth from this memory (bytes/s) +system.physmem2.bw_write::total 401682091 # Write bandwidth from this memory (bytes/s) +system.physmem2.bw_total::cpu.inst 3723784842 # Total bandwidth to/from this memory (bytes/s) +system.physmem2.bw_total::cpu.data 1071348214 # Total bandwidth to/from this memory (bytes/s) +system.physmem2.bw_total::total 4795133057 # Total bandwidth to/from this memory (bytes/s) +system.physmem2.readReqs 0 # Total number of read requests seen +system.physmem2.writeReqs 0 # Total number of write requests seen +system.physmem2.cpureqs 0 # Reqs generatd by CPU via cache - shady +system.physmem2.bytesRead 0 # Total number of bytes read from memory +system.physmem2.bytesWritten 0 # Total number of bytes written to memory +system.physmem2.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() +system.physmem2.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem2.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem2.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem2.perBankRdReqs::0 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::1 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::2 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::3 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::4 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::5 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::6 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::7 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::8 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::9 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::10 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::11 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::12 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::13 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::14 0 # Track reads on a per bank basis +system.physmem2.perBankRdReqs::15 0 # Track reads on a per bank basis +system.physmem2.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem2.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem2.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem2.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem2.totGap 0 # Total gap between requests +system.physmem2.readPktSize::0 0 # Categorize read packet sizes +system.physmem2.readPktSize::1 0 # Categorize read packet sizes +system.physmem2.readPktSize::2 0 # Categorize read packet sizes +system.physmem2.readPktSize::3 0 # Categorize read packet sizes +system.physmem2.readPktSize::4 0 # Categorize read packet sizes +system.physmem2.readPktSize::5 0 # Categorize read packet sizes +system.physmem2.readPktSize::6 0 # Categorize read packet sizes +system.physmem2.readPktSize::7 0 # Categorize read packet sizes +system.physmem2.readPktSize::8 0 # Categorize read packet sizes +system.physmem2.writePktSize::0 0 # categorize write packet sizes +system.physmem2.writePktSize::1 0 # categorize write packet sizes +system.physmem2.writePktSize::2 0 # categorize write packet sizes +system.physmem2.writePktSize::3 0 # categorize write packet sizes +system.physmem2.writePktSize::4 0 # categorize write packet sizes +system.physmem2.writePktSize::5 0 # categorize write packet sizes +system.physmem2.writePktSize::6 0 # categorize write packet sizes +system.physmem2.writePktSize::7 0 # categorize write packet sizes +system.physmem2.writePktSize::8 0 # categorize write packet sizes +system.physmem2.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem2.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem2.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem2.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem2.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem2.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem2.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem2.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem2.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem2.rdQLenPdf::0 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem2.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem2.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem2.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem2.totQLat 0 # Total cycles spent in queuing delays +system.physmem2.totMemAccLat 0 # Sum of mem lat for all requests +system.physmem2.totBusLat 0 # Total cycles spent in databus access +system.physmem2.totBankLat 0 # Total cycles spent in bank access +system.physmem2.avgQLat nan # Average queueing delay per request +system.physmem2.avgBankLat nan # Average bank access latency per request +system.physmem2.avgBusLat nan # Average bus latency per request +system.physmem2.avgMemAccLat nan # Average memory access latency +system.physmem2.avgRdBW 0.00 # Average achieved read bandwidth in MB/s +system.physmem2.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem2.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s +system.physmem2.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem2.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem2.busUtil 0.00 # Data bus utilization in percentage +system.physmem2.avgRdQLen 0.00 # Average read queue length over time +system.physmem2.avgWrQLen 0.00 # Average write queue length over time +system.physmem2.readRowHits 0 # Number of row buffer hits during reads +system.physmem2.writeRowHits 0 # Number of row buffer hits during writes +system.physmem2.readRowHitRate nan # Row buffer hit rate for reads +system.physmem2.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem2.avgGap nan # Average gap between requests system.cpu.numCycles 2233777513 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index eaa40425f..01d17fd64 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.271565 # Number of seconds simulated -sim_ticks 271565222500 # Number of ticks simulated -final_tick 271565222500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.269731 # Number of seconds simulated +sim_ticks 269730745500 # Number of ticks simulated +final_tick 269730745500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118122 # Simulator instruction rate (inst/s) -host_op_rate 118122 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53298093 # Simulator tick rate (ticks/s) -host_mem_usage 217868 # Number of bytes of host memory used -host_seconds 5095.21 # Real time elapsed on the host +host_inst_rate 168515 # Simulator instruction rate (inst/s) +host_op_rate 168515 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 75522303 # Simulator tick rate (ticks/s) +host_mem_usage 218132 # Number of bytes of host memory used +host_seconds 3571.54 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1620224 # Number of bytes read from this memory -system.physmem.bytes_read::total 1674048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1628992 # Number of bytes read from this memory +system.physmem.bytes_read::total 1682816 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 53824 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 53824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 57024 # Number of bytes written to this memory -system.physmem.bytes_written::total 57024 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 64896 # Number of bytes written to this memory +system.physmem.bytes_written::total 64896 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 841 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25316 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26157 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory -system.physmem.num_writes::total 891 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 198199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5966243 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6164442 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 198199 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 198199 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 209983 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 209983 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 209983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 198199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5966243 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6374424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 26157 # Total number of read requests seen -system.physmem.writeReqs 891 # Total number of write requests seen -system.physmem.cpureqs 27048 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1674048 # Total number of bytes read from memory -system.physmem.bytesWritten 57024 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1674048 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 57024 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 5 # Number of read reqs serviced by write Q +system.physmem.num_reads::cpu.data 25453 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 199547 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6039326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6238873 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199547 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199547 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 240595 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 240595 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 240595 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199547 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6039326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6479469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 26294 # Total number of read requests seen +system.physmem.writeReqs 1014 # Total number of write requests seen +system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1682816 # Total number of bytes read from memory +system.physmem.bytesWritten 64896 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1682816 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 64896 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1710 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1560 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1574 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1699 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1625 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1662 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1653 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1553 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1614 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1596 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1543 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1643 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1645 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1666 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 58 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 65 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 46 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 65 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 53 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 67 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 71 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 48 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 52 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 41 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 49 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 54 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 60 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 60 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1718 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1732 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1568 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1581 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1632 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1673 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1665 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1558 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1618 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1600 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1550 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1652 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1697 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1675 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 66 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 76 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 52 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 74 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 60 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 79 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 81 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 53 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 56 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 55 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 48 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 58 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 62 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 74 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 271565170500 # Total gap between requests +system.physmem.totGap 269730693500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 26157 # Categorize read packet sizes +system.physmem.readPktSize::6 26294 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 891 # categorize write packet sizes +system.physmem.writePktSize::6 1014 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 22499 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 383 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 800 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 782 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 17613 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 868 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -138,31 +138,31 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,47 +171,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 129156577 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 809724577 # Sum of mem lat for all requests -system.physmem.totBusLat 104608000 # Total cycles spent in databus access -system.physmem.totBankLat 575960000 # Total cycles spent in bank access -system.physmem.avgQLat 4938.69 # Average queueing delay per request -system.physmem.avgBankLat 22023.55 # Average bank access latency per request +system.physmem.totQLat 360576187 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1020404187 # Sum of mem lat for all requests +system.physmem.totBusLat 105120000 # Total cycles spent in databus access +system.physmem.totBankLat 554708000 # Total cycles spent in bank access +system.physmem.avgQLat 13720.56 # Average queueing delay per request +system.physmem.avgBankLat 21107.61 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30962.24 # Average memory access latency -system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.21 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.21 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 38828.17 # Average memory access latency +system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.24 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 7.68 # Average write queue length over time -system.physmem.readRowHits 17269 # Number of row buffer hits during reads -system.physmem.writeRowHits 120 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.03 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 13.47 # Row buffer hit rate for writes -system.physmem.avgGap 10040120.18 # Average gap between requests +system.physmem.avgWrQLen 12.19 # Average write queue length over time +system.physmem.readRowHits 17405 # Number of row buffer hits during reads +system.physmem.writeRowHits 51 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.23 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 5.03 # Row buffer hit rate for writes +system.physmem.avgGap 9877350.72 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517787 # DTB read hits +system.cpu.dtb.read_hits 114517567 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114520418 # DTB read accesses -system.cpu.dtb.write_hits 39661841 # DTB write hits +system.cpu.dtb.read_accesses 114520198 # DTB read accesses +system.cpu.dtb.write_hits 39453373 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39664143 # DTB write accesses -system.cpu.dtb.data_hits 154179628 # DTB hits +system.cpu.dtb.write_accesses 39455675 # DTB write accesses +system.cpu.dtb.data_hits 153970940 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 154184561 # DTB accesses -system.cpu.itb.fetch_hits 25070821 # ITB hits +system.cpu.dtb.data_accesses 153975873 # DTB accesses +system.cpu.itb.fetch_hits 25065868 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25070843 # ITB accesses +system.cpu.itb.fetch_accesses 25065890 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 543130446 # number of cpu cycles simulated +system.cpu.numCycles 539461492 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 86310002 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 81365597 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 36354316 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 52694902 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 34317638 # Number of BTB hits +system.cpu.branch_predictor.lookups 86297721 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 81352852 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 36357676 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 52914836 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 34319624 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 65.125158 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 36895088 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 49414914 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541552418 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 64.858226 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 36896934 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 49400787 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541636673 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1005407264 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 1005491519 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 255071398 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 155051796 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 33757784 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 2591545 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 36349329 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 26198578 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 58.114381 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 412334991 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 254989713 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 155053642 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 33759621 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 2593068 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 36352689 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 26195221 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 58.119750 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 412334808 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 538350006 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 535900413 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 387710 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 54025519 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 489104927 # Number of cycles cpu stages are processed. -system.cpu.activity 90.052939 # Percentage of cycles cpu is active +system.cpu.timesIdled 295985 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 50743768 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 488717724 # Number of cycles cpu stages are processed. +system.cpu.activity 90.593626 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -272,144 +272,144 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.902424 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.896328 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.902424 # CPI: Total CPI of All Threads -system.cpu.ipc 1.108126 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.896328 # CPI: Total CPI of All Threads +system.cpu.ipc 1.115663 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.108126 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 204275308 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338855138 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 62.389273 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 232303926 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310826520 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 57.228705 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 201351117 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341779329 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.927669 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 431560271 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111570175 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.542059 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 196153041 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 346977405 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 63.884727 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.115663 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 200698192 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338763300 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 62.796568 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 228822575 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310638917 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 57.583149 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 197865765 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341595727 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.321615 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 428073840 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111387652 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.647934 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 192651610 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 346809882 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.288163 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 729.013382 # Cycle average of tags in use -system.cpu.icache.total_refs 25069798 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 729.083311 # Cycle average of tags in use +system.cpu.icache.total_refs 25064833 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29321.401170 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29315.594152 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 729.013382 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.355964 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.355964 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25069798 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25069798 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25069798 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25069798 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25069798 # number of overall hits -system.cpu.icache.overall_hits::total 25069798 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1021 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1021 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1021 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1021 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1021 # number of overall misses -system.cpu.icache.overall_misses::total 1021 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 53787000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 53787000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 53787000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 53787000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 53787000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 53787000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25070819 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25070819 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25070819 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25070819 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25070819 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25070819 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 729.083311 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.355998 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.355998 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25064833 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25064833 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25064833 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25064833 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25064833 # number of overall hits +system.cpu.icache.overall_hits::total 25064833 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1035 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1035 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1035 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1035 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1035 # number of overall misses +system.cpu.icache.overall_misses::total 1035 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 52854000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 52854000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 52854000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 52854000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 52854000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 52854000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25065868 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25065868 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25065868 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25065868 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25065868 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25065868 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52680.705191 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52680.705191 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52680.705191 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52680.705191 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52680.705191 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52680.705191 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 109 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 36.333333 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51066.666667 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51066.666667 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 51066.666667 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51066.666667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 51066.666667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51066.666667 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 187 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 93.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 180 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 180 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 180 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 180 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 180 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 180 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43651000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 43651000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43651000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 43651000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43651000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 43651000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43286500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 43286500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43286500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 43286500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43286500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 43286500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51053.801170 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51053.801170 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51053.801170 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51053.801170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51053.801170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51053.801170 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50627.485380 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50627.485380 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50627.485380 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50627.485380 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50627.485380 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50627.485380 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4093.593977 # Cycle average of tags in use -system.cpu.dcache.total_refs 152406549 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4093.419858 # Cycle average of tags in use +system.cpu.dcache.total_refs 151786041 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 334.668912 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 342752000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.593977 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999413 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999413 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 114120505 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114120505 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 38286044 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38286044 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 152406549 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 152406549 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 152406549 # number of overall hits -system.cpu.dcache.overall_hits::total 152406549 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 393537 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 393537 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1165277 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1165277 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1558814 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1558814 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1558814 # number of overall misses -system.cpu.dcache.overall_misses::total 1558814 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5631779500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5631779500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16513706000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16513706000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22145485500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22145485500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22145485500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22145485500 # number of overall miss cycles +system.cpu.dcache.avg_refs 333.306341 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 334129000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.419858 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999370 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999370 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 114120628 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114120628 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37665413 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37665413 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 151786041 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 151786041 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 151786041 # number of overall hits +system.cpu.dcache.overall_hits::total 151786041 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 393414 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 393414 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1785908 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1785908 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2179322 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2179322 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2179322 # number of overall misses +system.cpu.dcache.overall_misses::total 2179322 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5991589500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5991589500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22875440000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22875440000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28867029500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28867029500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28867029500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28867029500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -418,40 +418,40 @@ system.cpu.dcache.demand_accesses::cpu.data 153965363 # system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029537 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029537 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010124 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010124 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010124 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010124 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14310.673456 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14310.673456 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14171.485406 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14171.485406 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14206.624716 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14206.624716 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14206.624716 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14206.624716 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 44530 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3993200 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3165 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 211455 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.069510 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18.884396 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003436 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003436 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045269 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014155 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014155 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014155 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014155 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15229.731275 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15229.731275 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12808.856895 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 12808.856895 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13245.876240 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13245.876240 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13245.876240 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13245.876240 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 165761 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 544 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5600 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.600179 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 60.444444 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks -system.cpu.dcache.writebacks::total 436902 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192305 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 192305 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911114 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 911114 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1103419 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1103419 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1103419 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1103419 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks +system.cpu.dcache.writebacks::total 436887 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192182 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 192182 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531745 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1531745 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1723927 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1723927 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1723927 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1723927 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -460,14 +460,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2467175500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2467175500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3742658000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3742658000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6209833500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6209833500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6209833500 # 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mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -476,68 +476,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12260.353721 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12260.353721 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14725.424236 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14725.424236 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13636.147740 # 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Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.021918 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.014514 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.698198 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 197087 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 197101 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 436902 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 436902 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 232992 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 232992 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 197082 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 197096 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 436887 # 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miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083387 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020501 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.024577 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083906 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083906 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983626 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.055591 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.057330 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.055892 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.057631 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.055591 # 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number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 234985616 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 267012470 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 891005143 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 891005143 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32026854 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1125990759 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1158017613 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32026854 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1125990759 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1158017613 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31666859 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 419253922 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 450920781 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 877062534 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 877062534 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31666859 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1296316456 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1327983315 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31666859 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1296316456 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1327983315 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020476 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024552 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083387 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083387 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083906 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083906 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.057330 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38081.871581 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57035.343689 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53822.308002 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42036.475892 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42036.475892 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38081.871581 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44477.435574 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44271.805368 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38081.871581 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44477.435574 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44271.805368 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37653.815696 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101637.314424 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 90801.607128 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41122.586928 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41122.586928 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37653.815696 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50929.810081 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50505.184263 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37653.815696 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50929.810081 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50505.184263 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 28d2d6014..82eaca8c6 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133501 # Number of seconds simulated -sim_ticks 133501490500 # Number of ticks simulated -final_tick 133501490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.135739 # Number of seconds simulated +sim_ticks 135738546500 # Number of ticks simulated +final_tick 135738546500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 263578 # Simulator instruction rate (inst/s) -host_op_rate 263578 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62218941 # Simulator tick rate (ticks/s) -host_mem_usage 217856 # Number of bytes of host memory used -host_seconds 2145.67 # Real time elapsed on the host +host_inst_rate 149707 # Simulator instruction rate (inst/s) +host_op_rate 149707 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35931284 # Simulator tick rate (ticks/s) +host_mem_usage 219152 # Number of bytes of host memory used +host_seconds 3777.73 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1627136 # Number of bytes read from this memory -system.physmem.bytes_read::total 1688448 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 58752 # Number of bytes written to this memory -system.physmem.bytes_written::total 58752 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 958 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25424 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26382 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 918 # Number of write requests responded to by this memory -system.physmem.num_writes::total 918 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 459261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12188149 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12647409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 459261 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 459261 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 440085 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 440085 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 440085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 459261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12188149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13087494 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 26382 # Total number of read requests seen -system.physmem.writeReqs 918 # Total number of write requests seen -system.physmem.cpureqs 27300 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1688448 # Total number of bytes read from memory -system.physmem.bytesWritten 58752 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1688448 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 58752 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1636160 # Number of bytes read from this memory +system.physmem.bytes_read::total 1697792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67072 # Number of bytes written to this memory +system.physmem.bytes_written::total 67072 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25565 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26528 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1048 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1048 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 454049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12053761 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12507810 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 454049 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 454049 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 494126 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 494126 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 494126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 454049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12053761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13001937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 26528 # Total number of read requests seen +system.physmem.writeReqs 1048 # Total number of write requests seen +system.physmem.cpureqs 27576 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1697792 # Total number of bytes read from memory +system.physmem.bytesWritten 67072 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1697792 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 67072 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1716 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1728 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1605 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1629 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1633 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1672 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1669 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1563 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1626 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1614 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1549 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1659 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1643 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1668 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 58 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 67 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 52 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 55 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 66 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 53 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 67 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 72 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 49 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 52 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 55 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 42 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 53 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 54 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 63 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 60 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1724 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1737 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1613 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1636 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1721 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1640 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1683 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1681 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1569 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1630 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1617 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1555 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1665 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1711 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1678 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 66 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 78 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 55 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 60 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 75 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 62 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 78 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 83 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 54 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 56 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 59 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 48 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 63 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 62 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 80 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 133501465500 # Total gap between requests +system.physmem.totGap 135738512500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 26382 # Categorize read packet sizes +system.physmem.readPktSize::6 26528 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 918 # categorize write packet sizes +system.physmem.writePktSize::6 1048 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 5916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 716 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 422 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 393 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 382 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 10104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 10480 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 4915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1000 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -138,31 +138,31 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,47 +171,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 842096821 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1422758821 # Sum of mem lat for all requests -system.physmem.totBusLat 105516000 # Total cycles spent in databus access -system.physmem.totBankLat 475146000 # Total cycles spent in bank access -system.physmem.avgQLat 31923.00 # Average queueing delay per request -system.physmem.avgBankLat 18012.28 # Average bank access latency per request +system.physmem.totQLat 656768415 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1272742415 # Sum of mem lat for all requests +system.physmem.totBusLat 106052000 # Total cycles spent in databus access +system.physmem.totBankLat 509922000 # Total cycles spent in bank access +system.physmem.avgQLat 24771.56 # Average queueing delay per request +system.physmem.avgBankLat 19232.90 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 53935.28 # Average memory access latency -system.physmem.avgRdBW 12.65 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.44 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 12.65 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.44 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 48004.47 # Average memory access latency +system.physmem.avgRdBW 12.51 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.49 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 12.51 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.49 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.08 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.07 # Average write queue length over time -system.physmem.readRowHits 17947 # Number of row buffer hits during reads -system.physmem.writeRowHits 124 # Number of row buffer hits during writes -system.physmem.readRowHitRate 68.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 13.51 # Row buffer hit rate for writes -system.physmem.avgGap 4890163.57 # Average gap between requests +system.physmem.avgWrQLen 10.03 # Average write queue length over time +system.physmem.readRowHits 18053 # Number of row buffer hits during reads +system.physmem.writeRowHits 56 # Number of row buffer hits during writes +system.physmem.readRowHitRate 68.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 5.34 # Row buffer hit rate for writes +system.physmem.avgGap 4922342.34 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 123834550 # DTB read hits -system.cpu.dtb.read_misses 17810 # DTB read misses +system.cpu.dtb.read_hits 123922794 # DTB read hits +system.cpu.dtb.read_misses 28366 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 123852360 # DTB read accesses -system.cpu.dtb.write_hits 40838763 # DTB write hits -system.cpu.dtb.write_misses 27151 # DTB write misses +system.cpu.dtb.read_accesses 123951160 # DTB read accesses +system.cpu.dtb.write_hits 40833980 # DTB write hits +system.cpu.dtb.write_misses 25612 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40865914 # DTB write accesses -system.cpu.dtb.data_hits 164673313 # DTB hits -system.cpu.dtb.data_misses 44961 # DTB misses +system.cpu.dtb.write_accesses 40859592 # DTB write accesses +system.cpu.dtb.data_hits 164756774 # DTB hits +system.cpu.dtb.data_misses 53978 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 164718274 # DTB accesses -system.cpu.itb.fetch_hits 66485884 # ITB hits -system.cpu.itb.fetch_misses 38 # ITB misses +system.cpu.dtb.data_accesses 164810752 # DTB accesses +system.cpu.itb.fetch_hits 66580671 # ITB hits +system.cpu.itb.fetch_misses 40 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 66485922 # ITB accesses +system.cpu.itb.fetch_accesses 66580711 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,245 +225,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 267002982 # number of cpu cycles simulated +system.cpu.numCycles 271477094 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 78490289 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 72847815 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3050228 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 42945683 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 41640479 # Number of BTB hits +system.cpu.BPredUnit.lookups 78553522 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 72909571 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3050106 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 42863354 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 41672348 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1629196 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68428860 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 710798920 # Number of instructions fetch has processed -system.cpu.fetch.Branches 78490289 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43269675 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 119192583 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12919622 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 69466328 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1179 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 66485884 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 944600 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 266949725 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.662670 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.464655 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1629524 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 245 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68542455 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 711581178 # Number of instructions fetch has processed +system.cpu.fetch.Branches 78553522 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43301872 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 119313775 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13045820 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 73380337 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 247 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1305 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 7 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66580671 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 946763 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 271202747 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.623798 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454049 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 147757142 55.35% 55.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10366639 3.88% 59.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11845375 4.44% 63.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10612007 3.98% 67.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6988496 2.62% 70.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2666505 1.00% 71.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3491309 1.31% 72.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3106869 1.16% 73.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 70115383 26.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 151888972 56.01% 56.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10373570 3.83% 59.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11841110 4.37% 64.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10622549 3.92% 68.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7004922 2.58% 70.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2671761 0.99% 71.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3503178 1.29% 72.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3113300 1.15% 74.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 70183385 25.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 266949725 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.293968 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.662139 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 85457793 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 53956348 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 104522021 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13153880 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9859683 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3909548 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1132 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 702023291 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 5115 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9859683 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 93690944 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11427696 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1077 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 104202524 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 47767801 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 690131281 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 37133482 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4417196 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 527277904 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 906836279 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 906833414 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2865 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 271202747 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.289356 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.621146 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 86023061 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 57429003 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 104152322 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13634796 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9963565 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3909126 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1128 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 702760367 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 4141 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9963565 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 94304341 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12784998 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1531 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104174044 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 49974268 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 690768624 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 416 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 38037873 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5669894 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 527681051 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 907529781 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 907526811 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2970 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 63423015 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 63826162 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 100 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 107 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 106239657 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 128990605 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42428237 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14728779 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9525532 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 626440684 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 91 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608386027 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 332535 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60195764 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33399973 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 74 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 266949725 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.279028 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.823675 # Number of insts issued each cycle +system.cpu.rename.skidInsts 112138467 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 129142032 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42466663 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14842304 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10368291 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 626932339 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 92 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608621790 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 344229 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60678365 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33855512 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 75 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 271202747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.244158 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.828491 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52346454 19.61% 19.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 53679990 20.11% 39.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 53956371 20.21% 59.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 37644200 14.10% 74.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31434632 11.78% 85.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23774675 8.91% 94.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10171294 3.81% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3315844 1.24% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 626265 0.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55518105 20.47% 20.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55264401 20.38% 40.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53914091 19.88% 60.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 37013789 13.65% 74.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31720099 11.70% 86.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23689667 8.74% 94.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10003906 3.69% 98.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3493839 1.29% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 584850 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 266949725 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 271202747 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2688356 76.19% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 516717 14.64% 90.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 323442 9.17% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2803923 71.85% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 36 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 717323 18.38% 90.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 381401 9.77% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 441007420 72.49% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7412 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 126109044 20.73% 93.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41262108 6.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 441148473 72.48% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7331 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 126212456 20.74% 93.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41253487 6.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608386027 # Type of FU issued -system.cpu.iq.rate 2.278574 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3528520 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005800 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1487578943 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 686639010 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 598810761 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3891 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2383 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1718 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 611912593 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1954 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12176241 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 608621790 # Type of FU issued +system.cpu.iq.rate 2.241890 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3902683 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006412 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1492689315 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 687613743 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 598990581 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3924 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2505 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1722 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 612522503 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1970 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12211500 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14476563 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33526 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4894 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2976916 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14627990 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 32965 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 5519 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3015342 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6758 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 144 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6777 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 53391 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9859683 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 765668 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 16511 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 670353065 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1690084 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 128990605 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42428237 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 91 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6929 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3539 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4894 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1348243 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2207087 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3555330 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 602565477 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 123852464 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5820550 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 9963565 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1456092 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 187737 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 670933978 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1716868 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 129142032 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42466663 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 92 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 140012 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7404 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 5519 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1345446 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2210203 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3555649 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 602801961 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 123951309 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5819829 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 43912290 # number of nop insts executed -system.cpu.iew.exec_refs 164735376 # number of memory reference insts executed -system.cpu.iew.exec_branches 67003758 # Number of branches executed -system.cpu.iew.exec_stores 40882912 # Number of stores executed -system.cpu.iew.exec_rate 2.256774 # Inst execution rate -system.cpu.iew.wb_sent 600054937 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 598812479 # cumulative count of insts written-back -system.cpu.iew.wb_producers 417702193 # num instructions producing a value -system.cpu.iew.wb_consumers 531441219 # num instructions consuming a value +system.cpu.iew.exec_nop 44001547 # number of nop insts executed +system.cpu.iew.exec_refs 164826908 # number of memory reference insts executed +system.cpu.iew.exec_branches 67037045 # Number of branches executed +system.cpu.iew.exec_stores 40875599 # Number of stores executed +system.cpu.iew.exec_rate 2.220452 # Inst execution rate +system.cpu.iew.wb_sent 600240253 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 598992303 # cumulative count of insts written-back +system.cpu.iew.wb_producers 417488059 # num instructions producing a value +system.cpu.iew.wb_consumers 532706701 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.242718 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.785980 # average fanout of values written-back +system.cpu.iew.wb_rate 2.206419 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.783711 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 68328005 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 68955725 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3049164 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 257090042 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.341036 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.706336 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3049050 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 261239182 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.303854 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.691353 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 78450782 30.51% 30.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72765387 28.30% 58.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 26309862 10.23% 69.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7783958 3.03% 72.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10791645 4.20% 76.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20794996 8.09% 84.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6257040 2.43% 86.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3054798 1.19% 87.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 30881574 12.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 82351408 31.52% 31.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72672063 27.82% 59.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 25867656 9.90% 69.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8932880 3.42% 72.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10297113 3.94% 76.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20861196 7.99% 84.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6530231 2.50% 87.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3837950 1.47% 88.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29888685 11.44% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 257090042 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 261239182 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -474,358 +475,368 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 30881574 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29888685 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 896329047 # The number of ROB reads -system.cpu.rob.rob_writes 1350251983 # The number of ROB writes -system.cpu.timesIdled 964 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 53257 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 902098796 # The number of ROB reads +system.cpu.rob.rob_writes 1351611788 # The number of ROB writes +system.cpu.timesIdled 34221 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 274347 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.472110 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.472110 # CPI: Total CPI of All Threads -system.cpu.ipc 2.118150 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.118150 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 848643813 # number of integer regfile reads -system.cpu.int_regfile_writes 492723889 # number of integer regfile writes -system.cpu.fp_regfile_reads 378 # number of floating regfile reads +system.cpu.cpi 0.480021 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.480021 # CPI: Total CPI of All Threads +system.cpu.ipc 2.083242 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.083242 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 848885274 # number of integer regfile reads +system.cpu.int_regfile_writes 492863541 # number of integer regfile writes +system.cpu.fp_regfile_reads 396 # number of floating regfile reads system.cpu.fp_regfile_writes 49 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 45 # number of replacements -system.cpu.icache.tagsinuse 826.583116 # Cycle average of tags in use -system.cpu.icache.total_refs 66484511 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 979 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 67910.634321 # Average number of references to valid blocks. +system.cpu.icache.replacements 43 # number of replacements +system.cpu.icache.tagsinuse 832.109405 # Cycle average of tags in use +system.cpu.icache.total_refs 66579220 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 984 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 67661.808943 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 826.583116 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.403605 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.403605 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 66484511 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 66484511 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 66484511 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 66484511 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 66484511 # number of overall hits -system.cpu.icache.overall_hits::total 66484511 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1373 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1373 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1373 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1373 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1373 # number of overall misses -system.cpu.icache.overall_misses::total 1373 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 50434500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 50434500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 50434500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 50434500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 50434500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 50434500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66485884 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66485884 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66485884 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66485884 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66485884 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66485884 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36733.066278 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36733.066278 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36733.066278 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36733.066278 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36733.066278 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36733.066278 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 832.109405 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.406303 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.406303 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 66579220 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 66579220 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 66579220 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 66579220 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 66579220 # number of overall hits +system.cpu.icache.overall_hits::total 66579220 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1449 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1449 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1449 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1449 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1449 # number of overall misses +system.cpu.icache.overall_misses::total 1449 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 74643000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 74643000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 74643000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 74643000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 74643000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 74643000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66580669 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66580669 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66580669 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66580669 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66580669 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66580669 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51513.457557 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51513.457557 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 51513.457557 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51513.457557 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 51513.457557 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51513.457557 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 293 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 73.250000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 394 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 394 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 394 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 394 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 394 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 394 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 979 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 979 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 979 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 979 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 979 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 979 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36994000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36994000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36994000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36994000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36994000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36994000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 465 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 465 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 465 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 465 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 465 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 465 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 984 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 984 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 984 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 984 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 984 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 984 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52158000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 52158000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52158000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 52158000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52158000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 52158000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37787.538304 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37787.538304 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37787.538304 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37787.538304 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37787.538304 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37787.538304 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53006.097561 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53006.097561 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53006.097561 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53006.097561 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53006.097561 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53006.097561 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 460592 # number of replacements -system.cpu.dcache.tagsinuse 4091.681579 # Cycle average of tags in use -system.cpu.dcache.total_refs 149616636 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 464688 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 321.972239 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 272105000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4091.681579 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998946 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998946 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 111082260 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 111082260 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 38534319 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38534319 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 149616579 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 149616579 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 149616579 # number of overall hits -system.cpu.dcache.overall_hits::total 149616579 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 569184 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 569184 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 917002 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 917002 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1486186 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1486186 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1486186 # number of overall misses -system.cpu.dcache.overall_misses::total 1486186 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5325915500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5325915500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10007471913 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10007471913 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15333387413 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15333387413 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15333387413 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15333387413 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 111651444 # 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number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37649215 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37649215 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 49 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 49 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 148282380 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 148282380 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 148282380 # number of overall hits +system.cpu.dcache.overall_hits::total 148282380 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1026018 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1026018 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1802106 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1802106 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2828124 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2828124 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2828124 # number of overall misses +system.cpu.dcache.overall_misses::total 2828124 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15421055000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15421055000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25889922656 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25889922656 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 28500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 28500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41310977656 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41310977656 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41310977656 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41310977656 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 111659183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 111659183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 57 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 57 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 151102765 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 151102765 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 151102765 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 151102765 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005098 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.005098 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.023244 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.023244 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009836 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009836 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009836 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009836 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9357.106841 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9357.106841 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10913.249822 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10913.249822 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10317.273486 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10317.273486 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10317.273486 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10317.273486 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1070 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 182 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 91 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.758242 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.750000 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 52 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 52 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 151110504 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 151110504 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 151110504 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 151110504 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009189 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009189 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045679 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045679 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057692 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057692 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018716 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018716 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018716 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018716 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.004347 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.004347 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14366.481581 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14366.481581 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14607.201684 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14607.201684 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14607.201684 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14607.201684 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 279576 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 531 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 17250 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.207304 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 44.250000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 444845 # number of writebacks -system.cpu.dcache.writebacks::total 444845 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 359021 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 359021 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 662477 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 662477 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1021498 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1021498 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1021498 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1021498 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210163 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 210163 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254525 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254525 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 464688 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 464688 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 464688 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 464688 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 841779000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 841779000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1751356497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1751356497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2593135497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 2593135497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2593135497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 2593135497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001882 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001882 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003075 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003075 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003075 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003075 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 4005.362504 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4005.362504 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 6880.882023 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 6880.882023 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 5580.379732 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 5580.379732 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 5580.379732 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 5580.379732 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 445038 # number of writebacks +system.cpu.dcache.writebacks::total 445038 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 815637 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 815637 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1547591 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1547591 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2363228 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2363228 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2363228 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2363228 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210381 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210381 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254515 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254515 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 464896 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 464896 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 464896 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 464896 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2700521500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2700521500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4051961986 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4051961986 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6752483486 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6752483486 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6752483486 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6752483486 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001884 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001884 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006451 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006451 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003077 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003077 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003077 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003077 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12836.337407 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12836.337407 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15920.326841 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15920.326841 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14524.718402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14524.718402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14524.718402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14524.718402 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 947 # number of replacements -system.cpu.l2cache.tagsinuse 22923.825111 # Cycle average of tags in use -system.cpu.l2cache.total_refs 555284 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23374 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.756482 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1080 # number of replacements +system.cpu.l2cache.tagsinuse 22929.630995 # Cycle average of tags in use +system.cpu.l2cache.total_refs 547178 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23523 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 23.261404 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21489.572206 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 820.765317 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 613.487588 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.655810 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.025048 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.018722 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.699580 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21483.752454 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 824.475298 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 621.403243 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.655632 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.025161 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.018964 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.699757 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 205882 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 205903 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 444845 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 444845 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 233382 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 233382 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 206090 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 206111 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 445038 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 445038 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 233241 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 233241 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 21 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 439264 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 439285 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 439331 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 439352 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 21 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 439264 # number of overall hits -system.cpu.l2cache.overall_hits::total 439285 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 958 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4281 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5239 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21143 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21143 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 958 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 25424 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 26382 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 958 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 25424 # number of overall misses -system.cpu.l2cache.overall_misses::total 26382 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35966000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 406243000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 442209000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1225336000 # 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number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 444845 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 254525 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 254525 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 979 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 464688 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 465667 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 979 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 464688 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 465667 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.978550 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020370 # 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number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.978550 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020370 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024813 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083068 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083068 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.978550 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054712 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.056654 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.978550 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054712 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.056654 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33982.712944 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 91011.255081 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 80583.054400 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54567.536300 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54567.536300 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33982.712944 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60704.082874 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59733.759457 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33982.712944 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60704.082874 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59733.759457 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 1049 # number of writebacks +system.cpu.l2cache.writebacks::total 1049 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 963 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4290 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5253 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21275 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21275 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 25565 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 26528 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 25565 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26528 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38838509 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 367821283 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 406659792 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1190995676 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1190995676 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38838509 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1558816959 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1597655468 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38838509 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1558816959 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1597655468 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.978659 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020392 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024853 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083590 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083590 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.978659 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.056942 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.978659 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.056942 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40330.746625 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 85739.226807 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77414.770988 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55980.995347 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55980.995347 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40330.746625 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60974.651242 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60225.251357 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40330.746625 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60974.651242 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60225.251357 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index cd0e43aa8..f1f52256e 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.762398 # Number of seconds simulated -sim_ticks 762397656000 # Number of ticks simulated -final_tick 762397656000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.762403 # Number of seconds simulated +sim_ticks 762403375000 # Number of ticks simulated +final_tick 762403375000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1514073 # Simulator instruction rate (inst/s) -host_op_rate 1514073 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1917939864 # Simulator tick rate (ticks/s) -host_mem_usage 219440 # Number of bytes of host memory used -host_seconds 397.51 # Real time elapsed on the host +host_inst_rate 2059312 # Simulator instruction rate (inst/s) +host_op_rate 2059312 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2608636387 # Simulator tick rate (ticks/s) +host_mem_usage 217100 # Number of bytes of host memory used +host_seconds 292.26 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1620160 # Number of bytes read from this memory -system.physmem.bytes_read::total 1670272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1628864 # Number of bytes read from this memory +system.physmem.bytes_read::total 1678976 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 56512 # Number of bytes written to this memory -system.physmem.bytes_written::total 56512 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 64384 # Number of bytes written to this memory +system.physmem.bytes_written::total 64384 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25315 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26098 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 883 # Number of write requests responded to by this memory -system.physmem.num_writes::total 883 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.data 25451 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26234 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1006 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1006 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 65729 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2125085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2190815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2136486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2202215 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 65729 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 65729 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 74124 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 74124 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 74124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 84449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 84449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 84449 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 65729 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2125085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2264939 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2136486 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2286664 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 1524795312 # number of cpu cycles simulated +system.cpu.numCycles 1524806750 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 601856964 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 153970296 # nu system.cpu.num_load_insts 114516673 # Number of load instructions system.cpu.num_store_insts 39453623 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1524795312 # Number of busy cycles +system.cpu.num_busy_cycles 1524806750 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 673.382950 # Cycle average of tags in use +system.cpu.icache.tagsinuse 673.381157 # Cycle average of tags in use system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 673.382950 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.328800 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.328800 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 673.381157 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.328799 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.328799 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 601861103 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 795 # n system.cpu.icache.demand_misses::total 795 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 795 # number of overall misses system.cpu.icache.overall_misses::total 795 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 43221000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 43221000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 43221000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 43221000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 43221000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 43221000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 43222000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 43222000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 43222000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 43222000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 43222000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 43222000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 601861898 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54366.037736 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54366.037736 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54366.037736 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54366.037736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54366.037736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54366.037736 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54367.295597 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54367.295597 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54367.295597 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54367.295597 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54367.295597 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54367.295597 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,32 +148,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 795 system.cpu.icache.demand_mshr_misses::total 795 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 795 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41631000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 41631000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41631000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 41631000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41631000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 41631000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41632000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 41632000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41632000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 41632000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41632000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 41632000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52366.037736 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52366.037736 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52367.295597 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52367.295597 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52367.295597 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52367.295597 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52367.295597 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52367.295597 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.202421 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.203488 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 563489000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.202421 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 563363000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.203488 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999561 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999561 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 455395 # n system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses system.cpu.dcache.overall_misses::total 455395 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2789140000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2789140000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4194225000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4194225000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6983365000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6983365000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6983365000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6983365000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2789356000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2789356000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4199727000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4199727000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6989083000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6989083000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6989083000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6989083000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13860.320426 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13860.320426 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16502.106916 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16502.106916 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15334.742367 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15334.742367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15334.742367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15334.742367 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13861.393814 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13861.393814 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16523.754441 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16523.754441 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15347.298499 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15347.298499 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15347.298499 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15347.298499 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks -system.cpu.dcache.writebacks::total 436902 # number of writebacks +system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks +system.cpu.dcache.writebacks::total 436887 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386676000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386676000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3685899000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3685899000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6072575000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6072575000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6072575000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6072575000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386892000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386892000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3691401000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3691401000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6078293000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6078293000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6078293000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6078293000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -258,68 +258,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11860.320426 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11860.320426 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14502.106916 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14502.106916 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11861.393814 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11861.393814 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14523.754441 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14523.754441 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 903 # number of replacements -system.cpu.l2cache.tagsinuse 22842.908958 # Cycle average of tags in use -system.cpu.l2cache.total_refs 538870 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23085 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.342863 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1028 # number of replacements +system.cpu.l2cache.tagsinuse 22854.086849 # Cycle average of tags in use +system.cpu.l2cache.total_refs 531883 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23221 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.905258 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21649.670438 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 668.334752 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 524.903769 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.660696 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.020396 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016019 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.697110 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21662.155591 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 666.530347 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 525.400911 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.661077 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.020341 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.016034 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.697451 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 12 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 197110 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 197122 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 436902 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 436902 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 232970 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 232970 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 197105 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 197117 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 436887 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 436887 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 232839 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 232839 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 12 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 430080 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 430092 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 429944 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 429956 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 12 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 430080 # number of overall hits -system.cpu.l2cache.overall_hits::total 430092 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 429944 # number of overall hits +system.cpu.l2cache.overall_hits::total 429956 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 783 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4122 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4905 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21193 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21193 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 4127 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4910 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 21324 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 21324 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 783 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 25315 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 26098 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 25451 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 26234 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 783 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 25315 # number of overall misses -system.cpu.l2cache.overall_misses::total 26098 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 40716000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214344000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 255060000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1102036000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1102036000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 40716000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1316380000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1357096000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 40716000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1316380000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1357096000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 25451 # number of overall misses +system.cpu.l2cache.overall_misses::total 26234 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 40717000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214610000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 255327000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1108848000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1108848000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 40717000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1323458000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1364175000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 40717000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1323458000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1364175000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 795 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 201232 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 202027 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 436902 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 436902 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 436887 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 436887 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 254163 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 254163 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 795 # number of demand (read+write) accesses @@ -329,27 +329,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 795 system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 456190 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.984906 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020484 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.024279 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083383 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083383 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020509 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.024304 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083899 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083899 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984906 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.055589 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.057209 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.055888 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.057507 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984906 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.055589 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.057209 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.055888 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.057507 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52001.277139 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52001.453841 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52001.425662 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52001.277139 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.235747 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.266829 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52001.277139 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.235747 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.266829 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -358,52 +358,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 883 # number of writebacks -system.cpu.l2cache.writebacks::total 883 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1006 # number of writebacks +system.cpu.l2cache.writebacks::total 1006 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 783 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4122 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4905 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21193 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21193 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4127 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4910 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21324 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21324 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 783 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 25315 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 26098 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 25451 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 26234 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 783 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 25315 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 26098 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 164880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 196200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 847720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 847720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31320000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1012600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1043920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31320000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1012600000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1043920000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 25451 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26234 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31321000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 165086000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 196407000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 852960000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 852960000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31321000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1018046000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1049367000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31321000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1018046000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1049367000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984906 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020484 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024279 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083383 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083383 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020509 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024304 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083899 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083899 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984906 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055589 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.057209 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055888 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.057507 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984906 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055589 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.057209 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055888 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.057507 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.277139 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40001.453841 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.425662 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.277139 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.235747 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.266829 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.277139 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.235747 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.266829 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 6dfebbc39..ec201586b 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.163308 # Number of seconds simulated -sim_ticks 163308075000 # Number of ticks simulated -final_tick 163308075000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.165181 # Number of seconds simulated +sim_ticks 165180822000 # Number of ticks simulated +final_tick 165180822000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134720 # Simulator instruction rate (inst/s) -host_op_rate 142356 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38594530 # Simulator tick rate (ticks/s) -host_mem_usage 233164 # Number of bytes of host memory used -host_seconds 4231.38 # Real time elapsed on the host -sim_insts 570052710 # Number of instructions simulated -sim_ops 602360916 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1771456 # Number of bytes read from this memory -system.physmem.bytes_read::total 1819968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 204864 # Number of bytes written to this memory -system.physmem.bytes_written::total 204864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 758 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 27679 # Number of read requests responded to by this memory -system.physmem.num_reads::total 28437 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 3201 # Number of write requests responded to by this memory -system.physmem.num_writes::total 3201 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 297058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10847326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11144385 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 297058 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 297058 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1254463 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1254463 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1254463 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 297058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10847326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12398848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 28438 # Total number of read requests seen -system.physmem.writeReqs 3201 # Total number of write requests seen -system.physmem.cpureqs 31639 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1819968 # Total number of bytes read from memory -system.physmem.bytesWritten 204864 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1819968 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 204864 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 110 # Number of read reqs serviced by write Q +host_inst_rate 196230 # Simulator instruction rate (inst/s) +host_op_rate 207352 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56860513 # Simulator tick rate (ticks/s) +host_mem_usage 233444 # Number of bytes of host memory used +host_seconds 2905.02 # Real time elapsed on the host +sim_insts 570052720 # Number of instructions simulated +sim_ops 602360926 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 46976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1702592 # Number of bytes read from this memory +system.physmem.bytes_read::total 1749568 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 46976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 46976 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162368 # Number of bytes written to this memory +system.physmem.bytes_written::total 162368 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 734 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26603 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27337 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2537 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2537 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 284391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10307444 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10591835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 284391 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 284391 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 982971 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 982971 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 982971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 284391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10307444 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11574806 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27339 # Total number of read requests seen +system.physmem.writeReqs 2537 # Total number of write requests seen +system.physmem.cpureqs 29876 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1749568 # Total number of bytes read from memory +system.physmem.bytesWritten 162368 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1749568 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162368 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1839 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1814 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1805 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1784 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1796 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1898 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1731 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1725 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1752 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1846 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1666 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1720 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1702 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1705 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1738 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1698 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1679 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1720 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1741 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1736 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1724 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1670 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1743 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1664 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1665 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1719 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 1759 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1677 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 255 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 220 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 240 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 223 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 185 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 230 # Track writes on a per bank basis +system.physmem.perBankRdReqs::15 1676 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 162 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 204 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 229 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 177 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 166 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 173 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 153 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 164 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 157 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 163308062000 # Total gap between requests +system.physmem.totGap 165180805000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 28438 # Categorize read packet sizes +system.physmem.readPktSize::6 27339 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 3201 # categorize write packet sizes +system.physmem.writePktSize::6 2537 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 10296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6854 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 743 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 66 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 14846 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8786 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -138,60 +138,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1146806136 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1807266136 # Sum of mem lat for all requests -system.physmem.totBusLat 113312000 # Total cycles spent in databus access -system.physmem.totBankLat 547148000 # Total cycles spent in bank access -system.physmem.avgQLat 40483.13 # Average queueing delay per request -system.physmem.avgBankLat 19314.74 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 63797.87 # Average memory access latency -system.physmem.avgRdBW 11.14 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.25 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 11.14 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.25 # Average consumed write bandwidth in MB/s +system.physmem.totQLat 952476989 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1656324989 # Sum of mem lat for all requests +system.physmem.totBusLat 109352000 # Total cycles spent in databus access +system.physmem.totBankLat 594496000 # Total cycles spent in bank access +system.physmem.avgQLat 34839.50 # Average queueing delay per request +system.physmem.avgBankLat 21745.35 # Average bank access latency per request +system.physmem.avgBusLat 3999.85 # Average bus latency per request +system.physmem.avgMemAccLat 60584.70 # Average memory access latency +system.physmem.avgRdBW 10.59 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.98 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 10.59 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.98 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.08 # Data bus utilization in percentage +system.physmem.busUtil 0.07 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 8.45 # Average write queue length over time -system.physmem.readRowHits 18527 # Number of row buffer hits during reads -system.physmem.writeRowHits 1851 # Number of row buffer hits during writes -system.physmem.readRowHitRate 65.40 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.83 # Row buffer hit rate for writes -system.physmem.avgGap 5161606.31 # Average gap between requests +system.physmem.avgWrQLen 5.90 # Average write queue length over time +system.physmem.readRowHits 17775 # Number of row buffer hits during reads +system.physmem.writeRowHits 1102 # Number of row buffer hits during writes +system.physmem.readRowHitRate 65.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 43.44 # Row buffer hit rate for writes +system.physmem.avgGap 5528879.54 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,141 +235,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 326616151 # number of cpu cycles simulated +system.cpu.numCycles 330361645 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 85529383 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80327419 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2411594 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 47239817 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 46868068 # Number of BTB hits +system.cpu.BPredUnit.lookups 85614942 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80408346 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2411110 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47313103 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46933261 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1438897 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 976 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68850265 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 669456795 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85529383 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48306965 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 130031029 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13412588 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 115987741 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1438558 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1082 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68875257 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 669940715 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85614942 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48371819 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 130120406 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13468606 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 119373897 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 596 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 67404301 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 787271 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 325854018 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.189155 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.204154 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 577 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 67426910 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 785892 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 329401870 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.167030 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.195227 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 195823205 60.10% 60.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20926796 6.42% 66.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4974411 1.53% 68.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14401150 4.42% 72.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8914958 2.74% 75.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9439818 2.90% 78.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4393851 1.35% 79.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5794662 1.78% 81.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 61185167 18.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 199281685 60.50% 60.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20931796 6.35% 66.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4976114 1.51% 68.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14405737 4.37% 72.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8916437 2.71% 75.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9491769 2.88% 78.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4395407 1.33% 79.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5797990 1.76% 81.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 61204935 18.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 325854018 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.261865 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.049674 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 92909986 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 93274931 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108737205 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 19949035 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10982861 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4721514 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 329401870 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.259155 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.027901 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 93386530 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96217512 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108381185 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20386445 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 11030198 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4725688 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 1634 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 705778363 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 5683 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10982861 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107200735 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12803432 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 41316 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114329497 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 80496177 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 697076108 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 75 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59278982 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 18940548 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 607 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 723768936 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3240980671 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3240980543 # Number of integer rename lookups +system.cpu.decode.DecodedInsts 706212594 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6047 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 11030198 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107646383 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14427218 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 44142 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114436491 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 81817438 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 697478243 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59322145 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20349848 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 693 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 724191424 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3242851069 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3242850941 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627419173 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 96349763 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2017 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1967 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 169248841 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172890049 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80617622 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21466789 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 27949042 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 681898631 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3279 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 646738917 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1408601 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 79369513 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 197745870 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 350 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 325854018 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.984750 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.743125 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627419189 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 96772235 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2137 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2090 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 170767366 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172981751 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80655031 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21643688 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28602277 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 682247714 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3351 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 646916263 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1413678 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 79713119 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 198676272 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 420 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 329401870 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.963912 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.726446 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 67303060 20.65% 20.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 84497277 25.93% 46.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 74959252 23.00% 69.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40290304 12.36% 81.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28820123 8.84% 90.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15118844 4.64% 95.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5732215 1.76% 97.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6879322 2.11% 99.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2253621 0.69% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 68982651 20.94% 20.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85413517 25.93% 46.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 75907397 23.04% 69.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40996794 12.45% 82.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28857883 8.76% 91.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14995240 4.55% 95.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5624116 1.71% 97.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6449034 1.96% 99.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2175238 0.66% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 325854018 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 329401870 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 205105 5.40% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2822579 74.31% 79.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 770924 20.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 209715 5.57% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2699537 71.67% 77.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 857291 22.76% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403867506 62.45% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6566 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403968416 62.45% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6570 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued @@ -397,468 +397,468 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 166069409 25.68% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76795433 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 166149452 25.68% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76791822 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 646738917 # Type of FU issued -system.cpu.iq.rate 1.980119 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3798608 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005873 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1624539025 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 761282766 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 638466372 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 646916263 # Type of FU issued +system.cpu.iq.rate 1.958206 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3766543 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005822 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1628414581 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 761976266 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 638610282 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 650537505 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 650682786 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30381283 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30415737 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23937231 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 124667 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11589 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10396384 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 24028931 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 122816 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12363 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10433791 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12749 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 16530 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12786 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 32242 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10982861 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 283658 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 42314 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 681905072 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 702708 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172890049 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80617622 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1929 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 10939 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4841 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11589 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1389637 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1521620 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2911257 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 642548978 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163933240 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4189939 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 11030198 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 797335 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 96405 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 682254196 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 711562 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172981751 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80655031 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2002 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 33535 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 20290 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12363 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1389918 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1519621 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2909539 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 642699172 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163997886 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4217091 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3162 # number of nop insts executed -system.cpu.iew.exec_refs 239931847 # number of memory reference insts executed -system.cpu.iew.exec_branches 74717690 # Number of branches executed -system.cpu.iew.exec_stores 75998607 # Number of stores executed -system.cpu.iew.exec_rate 1.967291 # Inst execution rate -system.cpu.iew.wb_sent 639936452 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 638466388 # cumulative count of insts written-back -system.cpu.iew.wb_producers 420738662 # num instructions producing a value -system.cpu.iew.wb_consumers 656063471 # num instructions consuming a value +system.cpu.iew.exec_nop 3131 # number of nop insts executed +system.cpu.iew.exec_refs 239992833 # number of memory reference insts executed +system.cpu.iew.exec_branches 74738268 # Number of branches executed +system.cpu.iew.exec_stores 75994947 # Number of stores executed +system.cpu.iew.exec_rate 1.945441 # Inst execution rate +system.cpu.iew.wb_sent 640075541 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 638610298 # cumulative count of insts written-back +system.cpu.iew.wb_producers 419218635 # num instructions producing a value +system.cpu.iew.wb_consumers 650818648 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.954791 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.641308 # average fanout of values written-back +system.cpu.iew.wb_rate 1.933064 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.644140 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 79553511 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 2929 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2410069 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 314871158 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.913040 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.240132 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 79903729 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 2931 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2409576 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 318371673 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.892006 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.234894 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 91119458 28.94% 28.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 103740730 32.95% 61.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42921464 13.63% 75.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8973909 2.85% 78.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25553482 8.12% 86.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13492783 4.29% 90.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7636973 2.43% 93.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1102971 0.35% 93.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20329388 6.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 93985379 29.52% 29.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104446341 32.81% 62.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43081844 13.53% 75.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8825548 2.77% 78.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25971107 8.16% 86.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12926353 4.06% 90.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7575563 2.38% 93.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1171571 0.37% 93.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20387967 6.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 314871158 # Number of insts commited each cycle -system.cpu.commit.committedInsts 570052761 # Number of instructions committed -system.cpu.commit.committedOps 602360967 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 318371673 # Number of insts commited each cycle +system.cpu.commit.committedInsts 570052771 # Number of instructions committed +system.cpu.commit.committedOps 602360977 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219174056 # Number of memory references committed -system.cpu.commit.loads 148952818 # Number of loads committed +system.cpu.commit.refs 219174060 # Number of memory references committed +system.cpu.commit.loads 148952820 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70892749 # Number of branches committed +system.cpu.commit.branches 70892751 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533523531 # Number of committed integer instructions. +system.cpu.commit.int_insts 533523539 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20329388 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20387967 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 976455636 # The number of ROB reads -system.cpu.rob.rob_writes 1374843243 # The number of ROB writes -system.cpu.timesIdled 13781 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 762133 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 570052710 # Number of Instructions Simulated -system.cpu.committedOps 602360916 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 570052710 # Number of Instructions Simulated -system.cpu.cpi 0.572958 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.572958 # CPI: Total CPI of All Threads -system.cpu.ipc 1.745329 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.745329 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3209817028 # number of integer regfile reads -system.cpu.int_regfile_writes 664078534 # number of integer regfile writes +system.cpu.rob.rob_reads 980247800 # The number of ROB reads +system.cpu.rob.rob_writes 1375591081 # The number of ROB writes +system.cpu.timesIdled 40973 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 959775 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 570052720 # Number of Instructions Simulated +system.cpu.committedOps 602360926 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 570052720 # Number of Instructions Simulated +system.cpu.cpi 0.579528 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.579528 # CPI: Total CPI of All Threads +system.cpu.ipc 1.725541 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.725541 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3210576810 # number of integer regfile reads +system.cpu.int_regfile_writes 664235164 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 904771120 # number of misc regfile reads -system.cpu.misc_regfile_writes 3106 # number of misc regfile writes -system.cpu.icache.replacements 68 # number of replacements -system.cpu.icache.tagsinuse 692.511005 # Cycle average of tags in use -system.cpu.icache.total_refs 67403190 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 831 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 81110.938628 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 905305467 # number of misc regfile reads +system.cpu.misc_regfile_writes 3110 # number of misc regfile writes +system.cpu.icache.replacements 62 # number of replacements +system.cpu.icache.tagsinuse 692.874511 # Cycle average of tags in use +system.cpu.icache.total_refs 67425756 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 825 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 81728.189091 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 692.511005 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.338140 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.338140 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67403190 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67403190 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67403190 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67403190 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67403190 # number of overall hits -system.cpu.icache.overall_hits::total 67403190 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1111 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1111 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1111 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1111 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1111 # number of overall misses -system.cpu.icache.overall_misses::total 1111 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39508000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39508000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39508000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39508000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39508000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39508000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67404301 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67404301 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67404301 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67404301 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67404301 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67404301 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35560.756076 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35560.756076 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35560.756076 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35560.756076 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35560.756076 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35560.756076 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 692.874511 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.338318 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.338318 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67425756 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67425756 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67425756 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67425756 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67425756 # number of overall hits +system.cpu.icache.overall_hits::total 67425756 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses +system.cpu.icache.overall_misses::total 1154 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 50922500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 50922500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 50922500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 50922500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 50922500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 50922500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67426910 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67426910 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67426910 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67426910 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67426910 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67426910 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44126.949740 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44126.949740 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44126.949740 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44126.949740 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44126.949740 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44126.949740 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 247 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 49.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 280 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 280 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 280 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 280 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 280 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 831 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 831 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 831 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 831 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 831 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 831 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29618500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 29618500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29618500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 29618500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29618500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 29618500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 328 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 328 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 328 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 328 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 328 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 826 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 826 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 826 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 826 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 826 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 826 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38439500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 38439500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38439500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 38439500 # 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miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001636 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018599 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.018599 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012813 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012813 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007473 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007473 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007473 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007473 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10507.999483 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 10507.999483 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10174.921337 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10174.921337 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9863.636364 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9863.636364 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10222.756075 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10222.756075 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10222.756075 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10222.756075 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 57181 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3033 # 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number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002583 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002583 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048140 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.048140 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.013357 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.013357 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018259 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018259 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018259 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018259 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15068.031490 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15068.031490 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12011.493011 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 12011.493011 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17630.434783 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17630.434783 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12295.132513 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12295.132513 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12295.132513 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12295.132513 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 131789 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4871 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.055841 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 421155 # number of writebacks -system.cpu.dcache.writebacks::total 421155 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 18984 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 18984 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1043965 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1043965 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # 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number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 28438 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 758 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 27680 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 28438 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25719146 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 701873552 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 727592698 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1275833198 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1275833198 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25719146 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1977706750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2003425896 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25719146 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1977706750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2003425896 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.912154 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.027844 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031549 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089750 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089750 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.912154 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.062250 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063835 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.912154 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.062250 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063835 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33930.271768 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 127613.373091 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 116266.011186 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57521.785302 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57521.785302 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33930.271768 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71448.943280 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70448.902736 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33930.271768 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71448.943280 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70448.902736 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::total 13 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 734 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4814 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5548 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21791 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21791 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 734 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26605 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27339 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 734 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26605 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27339 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27102664 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 668415074 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 695517738 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1272078673 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1272078673 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27102664 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1940493747 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1967596411 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27102664 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1940493747 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1967596411 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.888620 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024382 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027983 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088182 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088182 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.888620 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059847 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.061384 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.888620 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059847 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.061384 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36924.610354 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 138848.166597 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125363.687455 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58376.333027 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58376.333027 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36924.610354 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72937.182748 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71970.313874 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36924.610354 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72937.182748 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71970.313874 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt index e1fc6c299..3042021d4 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.793710 # Number of seconds simulated -sim_ticks 793709507000 # Number of ticks simulated -final_tick 793709507000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.793670 # Number of seconds simulated +sim_ticks 793670137000 # Number of ticks simulated +final_tick 793670137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1083083 # Simulator instruction rate (inst/s) -host_op_rate 1143775 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1512037928 # Simulator tick rate (ticks/s) -host_mem_usage 233820 # Number of bytes of host memory used -host_seconds 524.93 # Real time elapsed on the host +host_inst_rate 897110 # Simulator instruction rate (inst/s) +host_op_rate 947381 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1252348386 # Simulator tick rate (ticks/s) +host_mem_usage 231392 # Number of bytes of host memory used +host_seconds 633.75 # Real time elapsed on the host sim_insts 568539335 # Number of instructions simulated sim_ops 600398272 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 39104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1735040 # Number of bytes read from this memory -system.physmem.bytes_read::total 1774144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 39104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 39104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 194752 # Number of bytes written to this memory -system.physmem.bytes_written::total 194752 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 611 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 27110 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27721 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 3043 # Number of write requests responded to by this memory -system.physmem.num_writes::total 3043 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 49267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2185989 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2235256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 49267 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 49267 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 245369 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 245369 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 245369 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 49267 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2185989 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2480625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 38592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1675072 # Number of bytes read from this memory +system.physmem.bytes_read::total 1713664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 38592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 38592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 159552 # Number of bytes written to this memory +system.physmem.bytes_written::total 159552 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 603 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26173 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26776 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2493 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2493 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 48625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2110539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2159164 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 48625 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 48625 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 201031 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 201031 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 201031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 48625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2110539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2360195 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1587419014 # number of cpu cycles simulated +system.cpu.numCycles 1587340274 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 568539335 # Number of instructions committed @@ -96,16 +96,16 @@ system.cpu.num_mem_refs 219173606 # nu system.cpu.num_load_insts 148952593 # Number of load instructions system.cpu.num_store_insts 70221013 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1587419014 # Number of busy cycles +system.cpu.num_busy_cycles 1587340274 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 12 # number of replacements -system.cpu.icache.tagsinuse 577.773227 # Cycle average of tags in use +system.cpu.icache.tagsinuse 577.773656 # Cycle average of tags in use system.cpu.icache.total_refs 570073883 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 886584.576983 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 577.773227 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 577.773656 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.282116 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.282116 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 570073883 # number of ReadReq hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 643 # n system.cpu.icache.demand_misses::total 643 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 643 # number of overall misses system.cpu.icache.overall_misses::total 643 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34021000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34021000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34021000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34021000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34021000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34021000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 33685000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 33685000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 33685000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 33685000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 33685000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 33685000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 570074526 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 570074526 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 570074526 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52909.797823 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52909.797823 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52909.797823 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52909.797823 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52909.797823 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52909.797823 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52387.247278 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52387.247278 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52387.247278 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52387.247278 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52387.247278 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52387.247278 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,32 +158,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 643 system.cpu.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 643 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 643 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32735000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 32735000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32735000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 32735000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32735000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 32735000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32399000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 32399000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32399000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 32399000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32399000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 32399000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50909.797823 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50909.797823 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50387.247278 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50387.247278 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50387.247278 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50387.247278 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50387.247278 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50387.247278 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 433468 # number of replacements -system.cpu.dcache.tagsinuse 4094.242161 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.241219 # Cycle average of tags in use system.cpu.dcache.total_refs 216774472 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 495.412036 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 529482000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.242161 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 529622000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.241219 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999571 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999571 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 147602035 # number of ReadReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 437564 # n system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses system.cpu.dcache.overall_misses::total 437564 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2675478000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2675478000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4151654000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4151654000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6827132000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6827132000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6827132000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6827132000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2650304000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2650304000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4137794000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4137794000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6788098000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6788098000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6788098000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6788098000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 147791851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 147791851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14095.113162 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14095.113162 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16757.568174 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16757.568174 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15602.590707 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15602.590707 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15602.590707 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15602.590707 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13962.489990 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13962.489990 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16701.624231 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16701.624231 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15513.383185 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15513.383185 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 418219 # number of writebacks -system.cpu.dcache.writebacks::total 418219 # number of writebacks +system.cpu.dcache.writebacks::writebacks 418626 # number of writebacks +system.cpu.dcache.writebacks::total 418626 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 189816 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 189816 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247748 # number of WriteReq MSHR misses @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 437564 system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2295846000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2295846000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3656158000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3656158000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5952004000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5952004000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5952004000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5952004000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2270672000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2270672000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3642298000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3642298000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5912970000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5912970000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5912970000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5912970000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses @@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12095.113162 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12095.113162 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14757.568174 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14757.568174 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13602.590707 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13602.590707 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13602.590707 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13602.590707 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11962.489990 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11962.489990 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14701.624231 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14701.624231 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 3963 # number of replacements -system.cpu.l2cache.tagsinuse 21582.814171 # Cycle average of tags in use -system.cpu.l2cache.total_refs 495400 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24559 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 20.171831 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2512 # number of replacements +system.cpu.l2cache.tagsinuse 22024.775302 # Cycle average of tags in use +system.cpu.l2cache.total_refs 506990 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23599 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 21.483537 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20943.692003 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 130.073000 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 509.049168 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.639151 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.015535 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.658655 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 32 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 184871 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 184903 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 418219 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 418219 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 225583 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 225583 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 410454 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 410486 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 410454 # number of overall hits -system.cpu.l2cache.overall_hits::total 410486 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 611 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4945 # 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number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1152580000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 31772000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1409900000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1441672000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 31772000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1409900000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1441672000 # number of overall miss cycles +system.cpu.l2cache.occ_blocks::writebacks 20978.651717 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 539.196236 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 506.927350 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.640218 # 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number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 40 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 411391 # number of overall hits +system.cpu.l2cache.overall_hits::total 411431 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 603 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 4338 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4941 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 21835 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 21835 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 603 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 26173 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 26776 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 603 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 26173 # number of overall misses +system.cpu.l2cache.overall_misses::total 26776 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31356000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 226076000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 257432000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1135420000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1135420000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 31356000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1361496000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1392852000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 31356000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1361496000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1392852000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 643 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 189816 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 190459 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 418219 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 418219 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 418626 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 418626 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 247748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 247748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 643 # number of demand (read+write) accesses @@ -346,28 +346,28 @@ system.cpu.l2cache.demand_accesses::total 438207 # n system.cpu.l2cache.overall_accesses::cpu.inst 643 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 437564 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 438207 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.950233 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026052 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.029172 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089466 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.089466 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.950233 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.061957 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.063260 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.950233 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.061957 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.063260 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.937792 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022854 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.025943 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.088134 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.088134 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.937792 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.059815 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.061104 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.937792 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.059815 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.061104 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52036.400404 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52032.397408 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52115.260489 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52101.194090 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52006.639616 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52006.493272 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52019.103656 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52018.673439 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52006.639616 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52006.493272 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52019.103656 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52018.673439 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -376,52 +376,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 3043 # number of writebacks -system.cpu.l2cache.writebacks::total 3043 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 611 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4945 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5556 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 22165 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 22165 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 611 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 27110 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27721 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 611 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 27110 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27721 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24440000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 197980000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 222420000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 886600000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 886600000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24440000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1084580000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1109020000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24440000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1084580000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1109020000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026052 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.029172 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089466 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089466 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.061957 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063260 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.061957 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063260 # mshr miss rate for overall accesses +system.cpu.l2cache.writebacks::writebacks 2493 # number of writebacks +system.cpu.l2cache.writebacks::total 2493 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 603 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4338 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4941 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21835 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21835 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 603 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26173 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 26776 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 603 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26173 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26776 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24120000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 174020000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198140000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 873400000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 873400000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1047420000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1071540000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1047420000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1071540000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.937792 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022854 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.025943 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088134 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088134 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.937792 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059815 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.061104 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.937792 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059815 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.061104 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40036.400404 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40032.397408 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40115.260489 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40101.194090 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40006.639616 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40006.493272 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40019.103656 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40018.673439 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40006.639616 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40006.493272 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40019.103656 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40018.673439 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 532c2f1d1..ef06efc76 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.387215 # Number of seconds simulated -sim_ticks 387214915500 # Number of ticks simulated -final_tick 387214915500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.389228 # Number of seconds simulated +sim_ticks 389227542000 # Number of ticks simulated +final_tick 389227542000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118034 # Simulator instruction rate (inst/s) -host_op_rate 118406 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32618299 # Simulator tick rate (ticks/s) -host_mem_usage 226848 # Number of bytes of host memory used -host_seconds 11871.09 # Real time elapsed on the host +host_inst_rate 219415 # Simulator instruction rate (inst/s) +host_op_rate 220107 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60950012 # Simulator tick rate (ticks/s) +host_mem_usage 227096 # Number of bytes of host memory used +host_seconds 6386.01 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 78656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1678976 # Number of bytes read from this memory -system.physmem.bytes_read::total 1757632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 78656 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 78656 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 163392 # Number of bytes written to this memory -system.physmem.bytes_written::total 163392 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1229 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26234 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27463 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2553 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2553 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 203133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4336031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4539164 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 203133 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 203133 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 421967 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 421967 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 421967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 203133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4336031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4961131 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27464 # Total number of read requests seen -system.physmem.writeReqs 2553 # Total number of write requests seen -system.physmem.cpureqs 30017 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1757632 # Total number of bytes read from memory -system.physmem.bytesWritten 163392 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1757632 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 163392 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 4 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 76992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1678464 # Number of bytes read from this memory +system.physmem.bytes_read::total 1755456 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 76992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 76992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory +system.physmem.bytes_written::total 162112 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1203 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26226 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27429 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 197807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4312295 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4510102 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 416497 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 416497 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 416497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4312295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4926599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27430 # Total number of read requests seen +system.physmem.writeReqs 2533 # Total number of write requests seen +system.physmem.cpureqs 29963 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1755456 # Total number of bytes read from memory +system.physmem.bytesWritten 162112 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1755456 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1703 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1746 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1716 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1734 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1804 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1724 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1715 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1733 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1803 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 1768 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1696 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1697 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1668 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1679 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1746 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1678 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1745 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1695 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1685 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1728 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1758 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1711 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1754 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1713 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1623 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 172 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 161 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 165 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 166 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 161 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 153 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 157 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 160 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 153 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 152 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 387214887500 # Total gap between requests +system.physmem.totGap 389227514000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27464 # Categorize read packet sizes +system.physmem.readPktSize::6 27430 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 2553 # categorize write packet sizes +system.physmem.writePktSize::6 2533 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 6398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12553 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6348 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 625 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 371 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 8259 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13045 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -138,32 +138,32 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see @@ -171,161 +171,162 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 916617704 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1530569704 # Sum of mem lat for all requests -system.physmem.totBusLat 109840000 # Total cycles spent in databus access -system.physmem.totBankLat 504112000 # Total cycles spent in bank access -system.physmem.avgQLat 33380.11 # Average queueing delay per request -system.physmem.avgBankLat 18358.05 # Average bank access latency per request +system.physmem.totQLat 723930803 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1405746803 # Sum of mem lat for all requests +system.physmem.totBusLat 109720000 # Total cycles spent in databus access +system.physmem.totBankLat 572096000 # Total cycles spent in bank access +system.physmem.avgQLat 26391.94 # Average queueing delay per request +system.physmem.avgBankLat 20856.58 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 55738.15 # Average memory access latency -system.physmem.avgRdBW 4.54 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 51248.52 # Average memory access latency +system.physmem.avgRdBW 4.51 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 4.54 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 4.51 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.42 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 12.78 # Average write queue length over time -system.physmem.readRowHits 18350 # Number of row buffer hits during reads -system.physmem.writeRowHits 1423 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 55.74 # Row buffer hit rate for writes -system.physmem.avgGap 12899853.00 # Average gap between requests +system.physmem.avgWrQLen 17.21 # Average write queue length over time +system.physmem.readRowHits 18327 # Number of row buffer hits during reads +system.physmem.writeRowHits 1092 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 43.11 # Row buffer hit rate for writes +system.physmem.avgGap 12990271.80 # Average gap between requests system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 774429832 # number of cpu cycles simulated +system.cpu.numCycles 778455085 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 98185573 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 88408048 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3782090 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 66047653 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 65662573 # Number of BTB hits +system.cpu.BPredUnit.lookups 98229199 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 88445613 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3785118 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 66042302 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 65687206 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1362 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 165872466 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1648691883 # Number of instructions fetch has processed -system.cpu.fetch.Branches 98185573 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65663935 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 330391084 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 21655373 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 260441698 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 121 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2775 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 162813824 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 754521 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 774378524 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.134915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.150373 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1416 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 222 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 165941423 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1649243289 # Number of instructions fetch has processed +system.cpu.fetch.Branches 98229199 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65688622 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 330524246 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 21752869 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 264030512 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 127 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 3232 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 162872893 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 756309 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 778243541 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.125156 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.146469 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 443987440 57.33% 57.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74371964 9.60% 66.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37979457 4.90% 71.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9083058 1.17% 73.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28156651 3.64% 76.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18823006 2.43% 79.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11516280 1.49% 80.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3872547 0.50% 81.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146588121 18.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 447719295 57.53% 57.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74411347 9.56% 67.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37980792 4.88% 71.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9095898 1.17% 73.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28164996 3.62% 76.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18829907 2.42% 79.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11517848 1.48% 80.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3875799 0.50% 81.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146647659 18.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 774378524 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126784 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.128911 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 216878479 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 211680769 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 285325834 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 42823062 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 17670380 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1642440106 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 17670380 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 240852826 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 34201656 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 51873963 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 303043152 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 126736547 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1631096404 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 30920192 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 73688032 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3125584 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1360785655 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2755532793 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2721694232 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 33838561 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 778243541 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126185 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.118611 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 217164629 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 215069073 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 285415505 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42850333 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 17744001 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1642995255 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 17744001 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 241214952 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36881220 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52262769 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 303103685 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 127036914 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1631617640 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 159 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 30927214 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 74044181 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3148431 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1361239803 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2756565281 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2722455578 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34109703 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 116015216 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2681563 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2696177 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 272664149 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 438656145 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 180228164 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 255185830 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 83164069 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1516867754 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2636658 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1460784709 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 45870 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 113563441 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 136393501 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 392987 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 774378524 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.886396 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.429689 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 116469364 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2680762 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2695576 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 273321719 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 438834936 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 180276836 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 255914047 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 82184887 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1517277053 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2635551 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1461048176 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 49743 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 113961410 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 136888972 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 391880 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 778243541 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.877366 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.430181 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 144522601 18.66% 18.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 185174960 23.91% 42.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 210422651 27.17% 69.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131027562 16.92% 86.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70858421 9.15% 95.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20344015 2.63% 98.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7836220 1.01% 99.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4026070 0.52% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 166024 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 147640445 18.97% 18.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 185782276 23.87% 42.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 210767336 27.08% 69.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131005887 16.83% 86.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70732163 9.09% 95.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20418483 2.62% 98.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7758324 1.00% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3966460 0.51% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 172167 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 774378524 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 778243541 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112088 6.69% 6.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 98938 5.90% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1079860 64.44% 77.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 384872 22.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 96825 5.83% 5.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 95727 5.76% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1146892 69.00% 80.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 322714 19.42% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 867100758 59.36% 59.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 867232738 59.36% 59.36% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2647457 0.18% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2645576 0.18% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued @@ -351,84 +352,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419766221 28.74% 88.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171270273 11.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419895345 28.74% 88.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171274517 11.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1460784709 # Type of FU issued -system.cpu.iq.rate 1.886271 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1675758 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001147 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3679920663 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1624205262 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1444366362 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17748907 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9099237 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8557399 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1453373806 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9086661 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215387676 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1461048176 # Type of FU issued +system.cpu.iq.rate 1.876856 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1662158 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001138 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3684211603 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1624908064 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1444562282 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17840191 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9203552 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8548837 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1453579294 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9131040 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215356561 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 36143302 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 55137 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 245231 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 13380022 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 36322093 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 55076 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 245947 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 13428694 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3602 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3648 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 92141 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 17670380 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1032740 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 13152 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1613687741 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4121479 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 438656145 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 180228164 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2550792 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8203 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 255 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 245231 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2357183 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1559022 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3916205 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1455236393 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 417044165 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5548316 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 17744001 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3080372 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 245510 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1614123458 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4140274 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 438834936 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 180276836 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2549819 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 147701 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1738 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 245947 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2356068 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1563417 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3919485 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1455490088 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 417172237 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5558088 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 94183329 # number of nop insts executed -system.cpu.iew.exec_refs 587622922 # number of memory reference insts executed -system.cpu.iew.exec_branches 89108958 # Number of branches executed -system.cpu.iew.exec_stores 170578757 # Number of stores executed -system.cpu.iew.exec_rate 1.879107 # Inst execution rate -system.cpu.iew.wb_sent 1453841644 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1452923761 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1154329978 # num instructions producing a value -system.cpu.iew.wb_consumers 1205560357 # num instructions consuming a value +system.cpu.iew.exec_nop 94210854 # number of nop insts executed +system.cpu.iew.exec_refs 587755640 # number of memory reference insts executed +system.cpu.iew.exec_branches 89119477 # Number of branches executed +system.cpu.iew.exec_stores 170583403 # Number of stores executed +system.cpu.iew.exec_rate 1.869716 # Inst execution rate +system.cpu.iew.wb_sent 1454027442 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1453111119 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1154511485 # num instructions producing a value +system.cpu.iew.wb_consumers 1205709259 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.876121 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.957505 # average fanout of values written-back +system.cpu.iew.wb_rate 1.866660 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957537 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 124055997 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 124505734 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3782090 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 756708755 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.968423 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.506505 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3785118 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 760500151 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.958610 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.504084 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 238213555 31.48% 31.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 276540536 36.55% 68.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43021375 5.69% 73.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54822808 7.24% 80.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19645378 2.60% 83.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13385764 1.77% 85.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30553973 4.04% 89.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10565526 1.40% 90.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69959840 9.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 241986025 31.82% 31.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 276568961 36.37% 68.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42982436 5.65% 73.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54874417 7.22% 81.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19672131 2.59% 83.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13330795 1.75% 85.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30549094 4.02% 89.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10561201 1.39% 90.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69975091 9.20% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 756708755 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 760500151 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108088 # Number of instructions committed system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -439,374 +440,374 @@ system.cpu.commit.branches 86248928 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69959840 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69975091 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2300263324 # The number of ROB reads -system.cpu.rob.rob_writes 3244852707 # The number of ROB writes -system.cpu.timesIdled 1017 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 51308 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2304489206 # The number of ROB reads +system.cpu.rob.rob_writes 3245826636 # The number of ROB writes +system.cpu.timesIdled 25902 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 211544 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188945 # Number of Instructions Simulated system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated -system.cpu.cpi 0.552695 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.552695 # CPI: Total CPI of All Threads -system.cpu.ipc 1.809317 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.809317 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1980527314 # number of integer regfile reads -system.cpu.int_regfile_writes 1276211568 # number of integer regfile writes -system.cpu.fp_regfile_reads 16969770 # number of floating regfile reads -system.cpu.fp_regfile_writes 10498210 # number of floating regfile writes -system.cpu.misc_regfile_reads 593297660 # number of misc regfile reads +system.cpu.cpi 0.555568 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.555568 # CPI: Total CPI of All Threads +system.cpu.ipc 1.799961 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.799961 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1980833855 # number of integer regfile reads +system.cpu.int_regfile_writes 1276392600 # number of integer regfile writes +system.cpu.fp_regfile_reads 16967472 # number of floating regfile reads +system.cpu.fp_regfile_writes 10493116 # number of floating regfile writes +system.cpu.misc_regfile_reads 593429000 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 217 # number of replacements -system.cpu.icache.tagsinuse 1045.896866 # Cycle average of tags in use -system.cpu.icache.total_refs 162811965 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1366 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 119188.846999 # Average number of references to valid blocks. +system.cpu.icache.replacements 221 # number of replacements +system.cpu.icache.tagsinuse 1044.865694 # Cycle average of tags in use +system.cpu.icache.total_refs 162870916 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1368 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 119057.687135 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1045.896866 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.510692 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.510692 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 162811965 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 162811965 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 162811965 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 162811965 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 162811965 # number of overall hits -system.cpu.icache.overall_hits::total 162811965 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1859 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1859 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1859 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1859 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1859 # number of overall misses -system.cpu.icache.overall_misses::total 1859 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 53339000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 53339000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 53339000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 53339000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 53339000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 53339000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162813824 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162813824 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162813824 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162813824 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162813824 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162813824 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000011 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000011 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000011 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000011 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000011 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000011 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28692.307692 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28692.307692 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28692.307692 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28692.307692 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28692.307692 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28692.307692 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1044.865694 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.510188 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.510188 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 162870916 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 162870916 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 162870916 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 162870916 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 162870916 # number of overall hits +system.cpu.icache.overall_hits::total 162870916 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1977 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1977 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1977 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1977 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1977 # number of overall misses +system.cpu.icache.overall_misses::total 1977 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 82311500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 82311500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 82311500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 82311500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 82311500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 82311500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162872893 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162872893 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162872893 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162872893 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162872893 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162872893 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41634.547294 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41634.547294 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41634.547294 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41634.547294 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41634.547294 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41634.547294 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 38 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 492 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 40091000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 40091000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 40091000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 40091000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 40091000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 608 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 608 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 608 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 608 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 608 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 608 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1369 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1369 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1369 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1369 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1369 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1369 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60349500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 60349500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60349500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 60349500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60349500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 60349500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29327.724945 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29327.724945 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29327.724945 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29327.724945 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29327.724945 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29327.724945 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44082.907232 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44082.907232 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44082.907232 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 44082.907232 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44082.907232 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 44082.907232 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 458245 # number of replacements -system.cpu.dcache.tagsinuse 4094.164833 # Cycle average of tags in use -system.cpu.dcache.total_refs 365848378 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 462341 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 791.295555 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 304049000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.164833 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999552 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999552 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 200718396 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 200718396 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 165128663 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 165128663 # number of WriteReq hits +system.cpu.dcache.replacements 458014 # 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number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 365847059 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 365847059 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 365847059 # number of overall hits -system.cpu.dcache.overall_hits::total 365847059 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 893632 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 893632 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1718153 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1718153 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 365739456 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 365739456 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 365739456 # number of overall hits +system.cpu.dcache.overall_hits::total 365739456 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 929575 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 929575 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1888210 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1888210 # number of WriteReq misses system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 2611785 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2611785 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2611785 # number of overall misses -system.cpu.dcache.overall_misses::total 2611785 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6936484000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6936484000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15815722499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15815722499 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 50000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 50000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22752206499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22752206499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22752206499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22752206499 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 201612028 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 201612028 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2817785 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2817785 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2817785 # number of overall misses +system.cpu.dcache.overall_misses::total 2817785 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14994299000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14994299000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31871156950 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31871156950 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 122000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 122000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 46865455950 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46865455950 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46865455950 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46865455950 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201710425 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201710425 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 368458844 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 368458844 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 368458844 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 368458844 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004432 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004432 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010298 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010298 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 368557241 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 368557241 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 368557241 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 368557241 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004608 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004608 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011317 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011317 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007088 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007088 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007088 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007088 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7762.125797 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 7762.125797 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9205.072249 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9205.072249 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 7142.857143 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 7142.857143 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 8711.362727 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 8711.362727 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 8711.362727 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 8711.362727 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 36 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.007645 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007645 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007645 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007645 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16130.273512 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16130.273512 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16879.031967 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16879.031967 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 17428.571429 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 17428.571429 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16632.019813 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16632.019813 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16632.019813 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16632.019813 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 577430 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 18 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 35655 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.194924 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 18 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 443162 # number of writebacks -system.cpu.dcache.writebacks::total 443162 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 693399 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 693399 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1456052 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1456052 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2149451 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2149451 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2149451 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2149451 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200233 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200233 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262101 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 262101 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 442964 # number of writebacks +system.cpu.dcache.writebacks::total 442964 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 729519 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 729519 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1626163 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1626163 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2355682 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2355682 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2355682 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2355682 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200056 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 200056 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262047 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 262047 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 462334 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 462334 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 462334 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 462334 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 847043500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 847043500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1875854500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1875854500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 36000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 36000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2722898000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 2722898000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2722898000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 2722898000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000993 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000993 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 462103 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 462103 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 462103 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 462103 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2627957000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2627957000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4314187000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4314187000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 108000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 108000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6942144000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6942144000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6942144000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6942144000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000992 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001571 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001571 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001255 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001255 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001255 # 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average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 5889.460866 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001254 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001254 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13136.106890 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13136.106890 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16463.409236 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16463.409236 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 15428.571429 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 15428.571429 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15022.936445 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15022.936445 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15022.936445 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15022.936445 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2679 # number of replacements -system.cpu.l2cache.tagsinuse 22378.512464 # Cycle average of tags in use -system.cpu.l2cache.total_refs 542084 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24310 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.298807 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2556 # number of replacements +system.cpu.l2cache.tagsinuse 22458.024259 # Cycle average of tags in use +system.cpu.l2cache.total_refs 548899 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24278 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.608905 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20735.512523 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 999.090351 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 643.909590 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.632798 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.030490 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019651 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.682938 # 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number of cycles access was blocked +system.cpu.l2cache.occ_blocks::writebacks 20744.377954 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1070.274135 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 643.372169 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.633068 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.032662 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019634 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.685365 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 165 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 195629 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 195794 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 442964 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 442964 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 240255 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 240255 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 165 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 435884 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 436049 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 165 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 435884 # number of overall hits +system.cpu.l2cache.overall_hits::total 436049 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1204 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 4426 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 5630 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 21800 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 21800 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2018566500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2075878500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 57312000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2018566500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2075878500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1369 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 200055 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 201424 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 442964 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 442964 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 262055 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 262055 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1369 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 462110 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 463479 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1369 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 462110 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 463479 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.879474 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022124 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.027951 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083189 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083189 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.879474 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.056753 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.059183 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.879474 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.056753 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.059183 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47601.328904 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 106028.129236 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 93533.303730 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71068.165138 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71068.165138 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47601.328904 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76968.142302 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75679.128691 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47601.328904 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76968.142302 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75679.128691 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 28 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2553 # number of writebacks -system.cpu.l2cache.writebacks::total 2553 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1230 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4433 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5663 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21801 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21801 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1230 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26234 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27464 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1230 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26234 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27464 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34143480 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 430451654 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 464595134 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1217504185 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1217504185 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34143480 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1647955839 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1682099319 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34143480 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1647955839 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1682099319 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.899781 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022140 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.028091 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083174 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083174 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899781 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056742 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.059227 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899781 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056742 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.059227 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 27758.926829 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 97101.658922 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 82040.461593 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55846.254071 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55846.254071 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 27758.926829 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62817.558855 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61247.426413 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 27758.926829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62817.558855 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61247.426413 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 2533 # number of writebacks +system.cpu.l2cache.writebacks::total 2533 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1204 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4426 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5630 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21800 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21800 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1204 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26226 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27430 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1204 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26226 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27430 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 42159963 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 413894207 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 456054170 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1275808135 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1275808135 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42159963 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1689702342 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1731862305 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42159963 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1689702342 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1731862305 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.879474 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022124 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027951 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083189 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083189 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.879474 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056753 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059183 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.879474 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056753 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059183 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35016.580565 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 93514.280840 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 81004.293073 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58523.308945 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58523.308945 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35016.580565 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64428.519103 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63137.524790 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35016.580565 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64428.519103 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63137.524790 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt index c111732e8..d4dde6ec1 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.061067 # Number of seconds simulated -sim_ticks 2061066683000 # Number of ticks simulated -final_tick 2061066683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.061066 # Number of seconds simulated +sim_ticks 2061066313000 # Number of ticks simulated +final_tick 2061066313000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1352034 # Simulator instruction rate (inst/s) -host_op_rate 1356054 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1876383782 # Simulator tick rate (ticks/s) -host_mem_usage 222536 # Number of bytes of host memory used -host_seconds 1098.43 # Real time elapsed on the host +host_inst_rate 632829 # Simulator instruction rate (inst/s) +host_op_rate 634711 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 878254717 # Simulator tick rate (ticks/s) +host_mem_usage 225052 # Number of bytes of host memory used +host_seconds 2346.78 # Real time elapsed on the host sim_insts 1485108088 # Number of instructions simulated sim_ops 1489523282 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 65728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1672576 # Number of bytes read from this memory -system.physmem.bytes_read::total 1738304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 161472 # Number of bytes written to this memory -system.physmem.bytes_written::total 161472 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1027 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26134 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27161 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2523 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2523 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 31890 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 811510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 843400 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 31890 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 31890 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 78344 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 78344 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 78344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 31890 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 811510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 921744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1672512 # Number of bytes read from this memory +system.physmem.bytes_read::total 1737728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 161152 # Number of bytes written to this memory +system.physmem.bytes_written::total 161152 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1019 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26133 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27152 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2518 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2518 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 31642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 811479 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 843121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 31642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 31642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 78189 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 78189 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 78189 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 31642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 811479 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 921310 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 4122133366 # number of cpu cycles simulated +system.cpu.numCycles 4122132626 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1485108088 # Number of instructions committed @@ -54,16 +54,16 @@ system.cpu.num_mem_refs 569365766 # nu system.cpu.num_load_insts 402515345 # Number of load instructions system.cpu.num_store_insts 166850421 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4122133366 # Number of busy cycles +system.cpu.num_busy_cycles 4122132626 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 118 # number of replacements -system.cpu.icache.tagsinuse 906.468708 # Cycle average of tags in use +system.cpu.icache.tagsinuse 906.468716 # Cycle average of tags in use system.cpu.icache.total_refs 1485111892 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1341564.491418 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 906.468708 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 906.468716 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.442612 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.442612 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1485111892 # number of ReadReq hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 1107 # n system.cpu.icache.demand_misses::total 1107 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1107 # number of overall misses system.cpu.icache.overall_misses::total 1107 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 57527000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 57527000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 57527000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 57527000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 57527000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 57527000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 57199000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 57199000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 57199000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 57199000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 57199000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 57199000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1485112999 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1485112999 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1485112999 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51966.576332 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 51966.576332 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 51966.576332 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 51966.576332 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 51966.576332 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 51966.576332 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51670.280036 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51670.280036 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 51670.280036 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51670.280036 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 51670.280036 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51670.280036 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,32 +116,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1107 system.cpu.icache.demand_mshr_misses::total 1107 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1107 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1107 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55313000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 55313000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55313000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 55313000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55313000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 55313000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54985000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 54985000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54985000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 54985000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54985000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 54985000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49966.576332 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49966.576332 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49966.576332 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49966.576332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49966.576332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49966.576332 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49670.280036 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49670.280036 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49670.280036 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49670.280036 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49670.280036 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49670.280036 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 449125 # number of replacements -system.cpu.dcache.tagsinuse 4095.236029 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.236014 # Cycle average of tags in use system.cpu.dcache.total_refs 568907764 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 1255.254642 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 559332000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.236029 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 559340000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.236014 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999813 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999813 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 402319357 # number of ReadReq hits @@ -166,14 +166,14 @@ system.cpu.dcache.overall_misses::cpu.data 453214 # system.cpu.dcache.overall_misses::total 453214 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 2694826000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 2694826000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4294542000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4294542000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4294500000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4294500000 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 133000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 133000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6989368000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6989368000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6989368000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6989368000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6989326000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6989326000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6989326000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6989326000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 402512843 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 402512843 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) @@ -196,14 +196,14 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13927.757047 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 13927.757047 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16534.767141 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16534.767141 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16534.605433 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16534.605433 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 19000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 19000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15421.783087 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15421.783087 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15421.783087 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15421.783087 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15421.690416 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15421.690416 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15421.690416 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15421.690416 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -226,14 +226,14 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 453214 system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2307854000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2307854000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775086000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775086000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775044000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775044000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 119000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 119000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082940000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6082940000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6082940000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6082940000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082898000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6082898000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6082898000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6082898000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses @@ -246,63 +246,63 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11927.757047 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11927.757047 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.767141 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14534.767141 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.605433 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14534.605433 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 17000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 17000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2614 # number of replacements -system.cpu.l2cache.tagsinuse 22187.209427 # Cycle average of tags in use -system.cpu.l2cache.total_refs 527657 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23998 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.987541 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2539 # number of replacements +system.cpu.l2cache.tagsinuse 22253.549915 # Cycle average of tags in use +system.cpu.l2cache.total_refs 534785 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23989 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.292926 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20830.496331 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 857.499465 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 499.213631 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.635696 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.026169 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.015235 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.677100 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 80 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 20839.325928 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 913.017348 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 501.206640 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.635966 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.027863 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.015296 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.679124 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 88 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 189212 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 189292 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 189300 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 435341 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 435341 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 237875 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 237875 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 80 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 427087 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 427167 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 80 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 427087 # number of overall hits -system.cpu.l2cache.overall_hits::total 427167 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1027 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 237876 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 237876 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 88 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 427088 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 427176 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 88 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 427088 # number of overall hits +system.cpu.l2cache.overall_hits::total 427176 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1019 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 4274 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5301 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21860 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21860 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1027 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 26134 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 27161 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1027 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 26134 # number of overall misses -system.cpu.l2cache.overall_misses::total 27161 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 53406000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_misses::total 5293 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 21859 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 21859 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1019 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 26133 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 27152 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1019 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 26133 # number of overall misses +system.cpu.l2cache.overall_misses::total 27152 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 52998000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 222248000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 275654000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1136720000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1136720000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 53406000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1358968000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1412374000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 53406000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1358968000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1412374000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 275246000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1136668000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1136668000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 52998000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1358916000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1411914000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 52998000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1358916000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1411914000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 1107 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 193486 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 194593 # number of ReadReq accesses(hits+misses) @@ -316,28 +316,28 @@ system.cpu.l2cache.demand_accesses::total 454328 # n system.cpu.l2cache.overall_accesses::cpu.inst 1107 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 453221 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 454328 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.927733 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.920506 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022089 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.027241 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.084163 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.084163 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.927733 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.057663 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.059783 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.927733 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.057663 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.059783 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52001.947420 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_miss_rate::total 0.027200 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.084159 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.084159 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.920506 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.057661 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.059763 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.920506 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.057661 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.059763 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52009.813543 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.377287 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52001.889288 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52001.947420 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52009.813543 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.073635 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52001.947420 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.368297 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52009.813543 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.073635 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.368297 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -346,52 +346,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2523 # number of writebacks -system.cpu.l2cache.writebacks::total 2523 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1027 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 2518 # number of writebacks +system.cpu.l2cache.writebacks::total 2518 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1019 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4274 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5301 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21860 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21860 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1027 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26134 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27161 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1027 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26134 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27161 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41082000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_misses::total 5293 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21859 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21859 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1019 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26133 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27152 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26133 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27152 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40770000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 170960000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212042000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 874400000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 874400000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41082000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1045360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1086442000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41082000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1045360000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1086442000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 211730000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 874360000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 874360000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40770000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1045320000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1086090000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40770000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1045320000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1086090000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.920506 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022089 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027241 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.084163 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.084163 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.057663 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.059783 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.057663 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.059783 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.947420 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027200 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.084159 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.084159 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.920506 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.057661 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059763 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.920506 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.057661 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059763 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40009.813543 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.377287 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.889288 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.947420 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40009.813543 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.073635 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.947420 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.368297 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40009.813543 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.073635 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.368297 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 24127a6e1..43ee6670c 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.609434 # Number of seconds simulated -sim_ticks 609433847500 # Number of ticks simulated -final_tick 609433847500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.610645 # Number of seconds simulated +sim_ticks 610645123000 # Number of ticks simulated +final_tick 610645123000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61609 # Simulator instruction rate (inst/s) -host_op_rate 113518 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42665232 # Simulator tick rate (ticks/s) -host_mem_usage 229588 # Number of bytes of host memory used -host_seconds 14284.09 # Real time elapsed on the host +host_inst_rate 90668 # Simulator instruction rate (inst/s) +host_op_rate 167061 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62914134 # Simulator tick rate (ticks/s) +host_mem_usage 229848 # Number of bytes of host memory used +host_seconds 9706.01 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493925 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 58176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1694272 # Number of bytes read from this memory -system.physmem.bytes_read::total 1752448 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 58176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 58176 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162816 # Number of bytes written to this memory -system.physmem.bytes_written::total 162816 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 909 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26473 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27382 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2544 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2544 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 95459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2780075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2875534 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 95459 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 95459 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 267159 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 267159 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 267159 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 95459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2780075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3142694 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27384 # Total number of read requests seen -system.physmem.writeReqs 2544 # Total number of write requests seen -system.physmem.cpureqs 29928 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1752448 # Total number of bytes read from memory -system.physmem.bytesWritten 162816 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1752448 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 162816 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 13 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 58048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1693312 # Number of bytes read from this memory +system.physmem.bytes_read::total 1751360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 58048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 58048 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162176 # Number of bytes written to this memory +system.physmem.bytes_written::total 162176 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 907 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26458 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27365 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2534 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2534 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 95060 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2772989 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2868049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 95060 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 95060 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 265581 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 265581 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 265581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 95060 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2772989 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3133630 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27367 # Total number of read requests seen +system.physmem.writeReqs 2534 # Total number of write requests seen +system.physmem.cpureqs 29901 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1751360 # Total number of bytes read from memory +system.physmem.bytesWritten 162176 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1751360 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162176 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1753 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1689 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1673 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1748 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1674 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1754 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1755 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1781 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1776 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1809 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1711 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1756 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1780 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1777 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1811 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1712 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 1665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1638 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1637 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1661 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1666 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1670 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1694 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1692 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1676 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 165 # Track writes on a per bank basis +system.physmem.perBankWrReqs::0 162 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 155 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 163 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 162 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 166 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 167 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 158 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 154 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 153 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 153 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 156 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 609433834000 # Total gap between requests +system.physmem.totGap 610645109000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27384 # Categorize read packet sizes +system.physmem.readPktSize::6 27367 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 2544 # categorize write packet sizes +system.physmem.writePktSize::6 2534 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,13 +105,13 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 26904 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 26902 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 95 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -142,16 +142,16 @@ system.physmem.wrQLenPdf::0 111 # Wh system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 110 # What write queue length does an incoming req see @@ -171,264 +171,264 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 56299249 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 811057249 # Sum of mem lat for all requests -system.physmem.totBusLat 109484000 # Total cycles spent in databus access -system.physmem.totBankLat 645274000 # Total cycles spent in bank access -system.physmem.avgQLat 2056.89 # Average queueing delay per request -system.physmem.avgBankLat 23575.10 # Average bank access latency per request +system.physmem.totQLat 68648669 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 822368669 # Sum of mem lat for all requests +system.physmem.totBusLat 109468000 # Total cycles spent in databus access +system.physmem.totBankLat 644252000 # Total cycles spent in bank access +system.physmem.avgQLat 2508.45 # Average queueing delay per request +system.physmem.avgBankLat 23541.20 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29631.99 # Average memory access latency -system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 30049.65 # Average memory access latency +system.physmem.avgRdBW 2.87 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.87 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.27 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 8.89 # Average write queue length over time -system.physmem.readRowHits 17700 # Number of row buffer hits during reads -system.physmem.writeRowHits 1376 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 54.09 # Row buffer hit rate for writes -system.physmem.avgGap 20363333.13 # Average gap between requests +system.physmem.avgWrQLen 9.42 # Average write queue length over time +system.physmem.readRowHits 17709 # Number of row buffer hits during reads +system.physmem.writeRowHits 1083 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 42.74 # Row buffer hit rate for writes +system.physmem.avgGap 20422230.33 # Average gap between requests system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1218867696 # number of cpu cycles simulated +system.cpu.numCycles 1221290247 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 154233173 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 154233173 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 26682976 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 75825299 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 75424108 # Number of BTB hits +system.cpu.BPredUnit.lookups 153796448 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 153796448 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 26699295 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 76444965 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 76044325 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 180166559 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1483545531 # Number of instructions fetch has processed -system.cpu.fetch.Branches 154233173 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 75424108 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 400496189 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 91879143 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 573121383 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 424 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 185204471 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8524885 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1218826768 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.080610 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.274340 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180218290 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1484873312 # Number of instructions fetch has processed +system.cpu.fetch.Branches 153796448 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 76044325 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 400561886 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 92153015 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 574855756 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 55 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 434 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 186235545 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 9536973 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1220934154 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.078258 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.273787 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 825549489 67.73% 67.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24308401 1.99% 69.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15365270 1.26% 70.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 17994568 1.48% 72.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26708645 2.19% 74.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18181975 1.49% 76.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 28608277 2.35% 78.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 39394925 3.23% 81.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 222715218 18.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 827594377 67.78% 67.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24117068 1.98% 69.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15648261 1.28% 71.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 17796387 1.46% 72.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26716755 2.19% 74.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18183763 1.49% 76.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 28386980 2.33% 78.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39418545 3.23% 81.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 223072018 18.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1218826768 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126538 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.217151 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 289191573 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 496681660 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 275162301 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 92749072 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 65042162 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2356227760 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 65042162 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 337598744 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 122716382 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1927 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 305616336 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 387851217 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2259951612 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 313 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 242131587 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 121014894 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2627036833 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5767802630 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5767798158 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4472 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1220934154 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.125929 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.215823 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 289407961 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 498246191 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 275145699 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 92836570 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 65297733 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2356719721 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 65297733 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 337924282 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 123917110 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2381 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 305534064 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 388258584 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2260509367 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 337 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 242606329 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 120880984 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2627145665 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5770220684 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5770216108 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4576 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1886895257 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 740141576 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 82 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 82 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 730432949 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 541717387 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220348120 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 348120905 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 144711749 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2012299347 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 522 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1784417764 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 261262 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 390397150 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 813518141 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 472 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1218826768 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.464045 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.419425 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 740250408 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 92 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 92 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 731279841 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542420235 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220423040 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 348990798 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 145234295 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2013682993 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 521 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1784560921 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 286575 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 391758246 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 817229320 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 471 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1220934154 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.461636 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.419528 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 363571086 29.83% 29.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 365294377 29.97% 59.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234631055 19.25% 79.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 141184624 11.58% 90.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 60758407 4.98% 95.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 40069639 3.29% 98.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10832423 0.89% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1950212 0.16% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 534945 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 365719162 29.95% 29.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 365027224 29.90% 59.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234751927 19.23% 79.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 141361627 11.58% 90.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 60962306 4.99% 95.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39637127 3.25% 98.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10977510 0.90% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1933125 0.16% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 564146 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1218826768 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1220934154 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 467444 16.32% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2152766 75.14% 91.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 244877 8.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 457693 15.95% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2209699 77.01% 92.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 202113 7.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46817146 2.62% 2.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1065882672 59.73% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 479009051 26.84% 89.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192708895 10.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46812464 2.62% 2.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1065891237 59.73% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 479189352 26.85% 89.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192667868 10.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1784417764 # Type of FU issued -system.cpu.iq.rate 1.463996 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2865087 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001606 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4790788107 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2402871988 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1725236233 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 538 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1508 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 108 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1740465474 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 231 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 209679766 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1784560921 # Type of FU issued +system.cpu.iq.rate 1.461210 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2869505 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001608 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4793211641 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2405618854 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1725377736 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 435 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1480 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 90 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1740617772 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 190 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 209954463 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 122675266 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 38585 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 181440 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 32162063 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 123378114 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 38587 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 183844 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 32236983 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2083 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2078 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 49 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 65042162 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 152720 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 14367 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2012299869 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63596984 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 541717387 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220348120 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6821 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 181440 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2121622 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24710303 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 26831925 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1766440348 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 474226114 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 17977416 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 65297733 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1143885 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 111744 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2013683514 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63490304 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 542420235 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220423040 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 86 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 55193 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2862 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 183844 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2121921 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24727534 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 26849455 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1766386720 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 474113432 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 18174201 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 666063645 # number of memory reference insts executed -system.cpu.iew.exec_branches 110217721 # Number of branches executed -system.cpu.iew.exec_stores 191837531 # Number of stores executed -system.cpu.iew.exec_rate 1.449247 # Inst execution rate -system.cpu.iew.wb_sent 1726559885 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1725236341 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1267696731 # num instructions producing a value -system.cpu.iew.wb_consumers 1828647298 # num instructions consuming a value +system.cpu.iew.exec_refs 665931472 # number of memory reference insts executed +system.cpu.iew.exec_branches 110216269 # Number of branches executed +system.cpu.iew.exec_stores 191818040 # Number of stores executed +system.cpu.iew.exec_rate 1.446328 # Inst execution rate +system.cpu.iew.wb_sent 1726595079 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1725377826 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1268018973 # num instructions producing a value +system.cpu.iew.wb_consumers 1829950696 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.415442 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.693243 # average fanout of values written-back +system.cpu.iew.wb_rate 1.412750 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692925 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 390808265 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 392192006 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 26683034 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1153784606 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.405370 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.832544 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 26699352 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1155636421 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.403118 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.832114 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 420543726 36.45% 36.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 413309390 35.82% 72.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 87337007 7.57% 79.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 122231111 10.59% 90.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24478385 2.12% 92.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22989251 1.99% 94.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18567232 1.61% 96.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12074031 1.05% 97.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 32254473 2.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 422545803 36.56% 36.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 413097230 35.75% 72.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 87361742 7.56% 79.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 122290747 10.58% 90.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24514270 2.12% 92.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22708378 1.97% 94.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 18848985 1.63% 96.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12046038 1.04% 97.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 32223228 2.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1153784606 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1155636421 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025277 # Number of instructions committed system.cpu.commit.committedOps 1621493925 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -439,298 +439,302 @@ system.cpu.commit.branches 107161574 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354435 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 32254473 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 32223228 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3133832323 # The number of ROB reads -system.cpu.rob.rob_writes 4089684452 # The number of ROB writes -system.cpu.timesIdled 614 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 40928 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3137099124 # The number of ROB reads +system.cpu.rob.rob_writes 4092706915 # The number of ROB writes +system.cpu.timesIdled 59218 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 356093 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025277 # Number of Instructions Simulated system.cpu.committedOps 1621493925 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated -system.cpu.cpi 1.385037 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.385037 # CPI: Total CPI of All Threads -system.cpu.ipc 0.722002 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.722002 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3541814029 # number of integer regfile reads -system.cpu.int_regfile_writes 1975313076 # number of integer regfile writes -system.cpu.fp_regfile_reads 108 # number of floating regfile reads -system.cpu.misc_regfile_reads 910517303 # number of misc regfile reads -system.cpu.icache.replacements 21 # number of replacements -system.cpu.icache.tagsinuse 817.668717 # Cycle average of tags in use -system.cpu.icache.total_refs 185203176 # Total number of references to valid blocks. +system.cpu.cpi 1.387790 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.387790 # CPI: Total CPI of All Threads +system.cpu.ipc 0.720570 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.720570 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3541569732 # number of integer regfile reads +system.cpu.int_regfile_writes 1975385267 # number of integer regfile writes +system.cpu.fp_regfile_reads 90 # number of floating regfile reads +system.cpu.misc_regfile_reads 910403293 # number of misc regfile reads +system.cpu.icache.replacements 20 # number of replacements +system.cpu.icache.tagsinuse 822.205718 # Cycle average of tags in use +system.cpu.icache.total_refs 186234150 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 919 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 201526.850925 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 202648.694233 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 817.668717 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.399252 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.399252 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 185203176 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 185203176 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 185203176 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 185203176 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 185203176 # number of overall hits -system.cpu.icache.overall_hits::total 185203176 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1295 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1295 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1295 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1295 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1295 # number of overall misses -system.cpu.icache.overall_misses::total 1295 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39388000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39388000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39388000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39388000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39388000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39388000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 185204471 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 185204471 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 185204471 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 185204471 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 185204471 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 185204471 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 822.205718 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.401468 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.401468 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 186234151 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 186234151 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 186234151 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 186234151 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 186234151 # number of overall hits +system.cpu.icache.overall_hits::total 186234151 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1394 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1394 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1394 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1394 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1394 # number of overall misses +system.cpu.icache.overall_misses::total 1394 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 63295000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 63295000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 63295000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 63295000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 63295000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 63295000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 186235545 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 186235545 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 186235545 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 186235545 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 186235545 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 186235545 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30415.444015 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30415.444015 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30415.444015 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30415.444015 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30415.444015 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30415.444015 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45405.308465 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 45405.308465 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 45405.308465 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 45405.308465 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 45405.308465 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 45405.308465 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 42.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 376 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 376 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 376 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 376 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 376 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 919 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 919 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 919 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 919 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 919 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 919 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30110000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 30110000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30110000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 30110000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30110000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 30110000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 472 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 472 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 472 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 472 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 472 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 472 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 922 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 922 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 922 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 922 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 922 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 922 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46053000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46053000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46053000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46053000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46053000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46053000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32763.873776 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32763.873776 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32763.873776 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 32763.873776 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32763.873776 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 32763.873776 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49949.023861 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49949.023861 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49949.023861 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49949.023861 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49949.023861 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49949.023861 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 445574 # number of replacements -system.cpu.dcache.tagsinuse 4093.370170 # Cycle average of tags in use -system.cpu.dcache.total_refs 452274995 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 449670 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1005.793126 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 737045000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.370170 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999358 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999358 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 264335239 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 264335239 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 187939756 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 187939756 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 452274995 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 452274995 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 452274995 # number of overall hits -system.cpu.dcache.overall_hits::total 452274995 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 208073 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 208073 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 246301 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 246301 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 454374 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 454374 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 454374 # number of overall misses -system.cpu.dcache.overall_misses::total 454374 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1068376500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1068376500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1644748000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1644748000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 2713124500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 2713124500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 2713124500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 2713124500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 264543312 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 264543312 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 445401 # number of replacements +system.cpu.dcache.tagsinuse 4092.926016 # Cycle average of tags in use +system.cpu.dcache.total_refs 451884939 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 449497 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1005.312469 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 828056000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4092.926016 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999250 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999250 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 263945150 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 263945150 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187939786 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187939786 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 451884936 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 451884936 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 451884936 # number of overall hits +system.cpu.dcache.overall_hits::total 451884936 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 210668 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 210668 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 246271 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 246271 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 456939 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 456939 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 456939 # number of overall misses +system.cpu.dcache.overall_misses::total 456939 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3009925000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3009925000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4061663000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4061663000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7071588000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7071588000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7071588000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7071588000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264155818 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264155818 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 452729369 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 452729369 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 452729369 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 452729369 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000787 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000787 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 452341875 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 452341875 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 452341875 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 452341875 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000798 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000798 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001309 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001309 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.001004 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.001004 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.001004 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.001004 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5134.623425 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 5134.623425 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 6677.796680 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 6677.796680 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 5971.126209 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 5971.126209 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 5971.126209 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 5971.126209 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.001010 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.001010 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.001010 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.001010 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14287.528243 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14287.528243 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16492.656464 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16492.656464 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15476.000079 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15476.000079 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15476.000079 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15476.000079 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 339 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 37 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.162162 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 428583 # number of writebacks -system.cpu.dcache.writebacks::total 428583 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4687 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4687 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4702 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4702 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4702 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4702 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203386 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 203386 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246286 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 246286 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 449672 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 449672 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 449672 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 449672 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 641587500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 641587500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1151947500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1151947500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1793535000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 1793535000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1793535000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 1793535000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000769 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000769 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001309 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000993 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000993 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000993 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000993 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 3154.531285 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 3154.531285 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 4677.275606 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 4677.275606 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3988.540536 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 3988.540536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3988.540536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 3988.540536 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 428512 # number of writebacks +system.cpu.dcache.writebacks::total 428512 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7369 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7369 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 67 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 67 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7436 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7436 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7436 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7436 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203299 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 203299 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246204 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 246204 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 449503 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 449503 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 449503 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 449503 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2518009500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2518009500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3568493000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3568493000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6086502500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6086502500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6086502500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6086502500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001308 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001308 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000994 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12385.744642 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12385.744642 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14494.049650 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14494.049650 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13540.515859 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13540.515859 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13540.515859 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13540.515859 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2659 # number of replacements -system.cpu.l2cache.tagsinuse 22184.156099 # Cycle average of tags in use -system.cpu.l2cache.total_refs 517708 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24213 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.381407 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2556 # number of replacements +system.cpu.l2cache.tagsinuse 22261.498307 # Cycle average of tags in use +system.cpu.l2cache.total_refs 530423 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24197 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 21.921023 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20787.169449 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 726.088351 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 670.898299 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.634374 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.022158 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020474 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.677007 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 10 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 198821 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 198831 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 428583 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 428583 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 224376 # 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number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44997500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 325370000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 370367500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1079389000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1079389000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 44997500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1404759000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1449756500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 44997500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1404759000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1449756500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 919 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 203375 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 204294 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 428583 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 428583 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246297 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246297 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 203289 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 204208 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 428512 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 428512 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246211 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246211 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 919 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 449672 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 450591 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 449500 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 450419 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 919 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 449672 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 450591 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.989119 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022392 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.026741 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089002 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.089002 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.989119 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.058876 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.060774 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.989119 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.058876 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.060774 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 32086.358636 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52217.940272 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 48868.204283 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 31072.761279 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 31072.761279 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 32086.358636 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34709.971671 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34622.881975 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 32086.358636 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34709.971671 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34622.881975 # average overall miss latency +system.cpu.l2cache.overall_accesses::cpu.data 449500 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 450419 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.986942 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022347 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.026688 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089017 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.089017 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.986942 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.058865 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.060759 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.986942 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.058865 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.060759 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49611.356119 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71620.074840 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67957.339450 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49248.939180 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49248.939180 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49611.356119 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53089.909297 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52974.622721 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49611.356119 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53089.909297 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52974.622721 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -739,52 +743,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2544 # number of writebacks -system.cpu.l2cache.writebacks::total 2544 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 909 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4554 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5463 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21921 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21921 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 909 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26475 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27384 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 909 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26475 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27384 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25917391 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 220807955 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 246725346 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 596009194 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 596009194 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25917391 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 816817149 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 842734540 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25917391 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 816817149 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 842734540 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.989119 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022392 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026741 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089002 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089002 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.989119 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058876 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060774 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.989119 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058876 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060774 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28511.981298 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48486.595301 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45162.977485 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 27188.960084 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 27188.960084 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28511.981298 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 30852.394674 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30774.705668 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28511.981298 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 30852.394674 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30774.705668 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 2534 # number of writebacks +system.cpu.l2cache.writebacks::total 2534 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 907 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4543 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5450 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21917 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21917 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 907 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26460 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27367 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 907 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26460 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27367 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33582421 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 267466906 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301049327 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 797222639 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 797222639 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33582421 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1064689545 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1098271966 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33582421 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1064689545 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1098271966 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.986942 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022347 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026688 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089017 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089017 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.986942 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058865 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060759 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.986942 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058865 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060759 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37025.822492 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58874.511556 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55238.408624 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36374.624219 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36374.624219 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37025.822492 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40237.700113 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40131.251727 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37025.822492 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40237.700113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40131.251727 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt index e35ba34dd..ea680ba75 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.800193 # Number of seconds simulated -sim_ticks 1800193072000 # Number of ticks simulated -final_tick 1800193072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1800193396000 # Number of ticks simulated +final_tick 1800193396000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 480678 # Simulator instruction rate (inst/s) -host_op_rate 885676 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 983283018 # Simulator tick rate (ticks/s) -host_mem_usage 228792 # Number of bytes of host memory used -host_seconds 1830.80 # Real time elapsed on the host +host_inst_rate 332254 # Simulator instruction rate (inst/s) +host_op_rate 612196 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 679663607 # Simulator tick rate (ticks/s) +host_mem_usage 227800 # Number of bytes of host memory used +host_seconds 2648.65 # Real time elapsed on the host sim_insts 880025278 # Number of instructions simulated sim_ops 1621493926 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory @@ -16,26 +16,26 @@ system.physmem.bytes_read::cpu.data 1682368 # Nu system.physmem.bytes_read::total 1728576 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 46208 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 46208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 160640 # Number of bytes written to this memory -system.physmem.bytes_written::total 160640 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 160704 # Number of bytes written to this memory +system.physmem.bytes_written::total 160704 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 722 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 26287 # Number of read requests responded to by this memory system.physmem.num_reads::total 27009 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2510 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2510 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 2511 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2511 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 25668 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 934549 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 934548 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 960217 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 25668 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 25668 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 89235 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 89235 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 89235 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 89270 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 89270 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 89270 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 25668 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 934549 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1049452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 934548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1049487 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 3600386144 # number of cpu cycles simulated +system.cpu.numCycles 3600386792 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 880025278 # Number of instructions committed @@ -54,16 +54,16 @@ system.cpu.num_mem_refs 607228178 # nu system.cpu.num_load_insts 419042121 # Number of load instructions system.cpu.num_store_insts 188186057 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3600386144 # Number of busy cycles +system.cpu.num_busy_cycles 3600386792 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 660.197374 # Cycle average of tags in use +system.cpu.icache.tagsinuse 660.197306 # Cycle average of tags in use system.cpu.icache.total_refs 1186515974 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1643373.925208 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 660.197374 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 660.197306 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.322362 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.322362 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1186515974 # number of ReadReq hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 722 # n system.cpu.icache.demand_misses::total 722 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 722 # number of overall misses system.cpu.icache.overall_misses::total 722 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39710000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39710000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39710000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39710000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39710000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39710000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 39712000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 39712000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39712000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39712000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39712000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39712000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1186516696 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1186516696 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1186516696 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55002.770083 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55002.770083 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55002.770083 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55002.770083 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55002.770083 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55002.770083 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,32 +116,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 722 system.cpu.icache.demand_mshr_misses::total 722 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 722 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38266000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 38266000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38266000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 38266000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38266000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 38266000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38268000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 38268000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38268000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 38268000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38268000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 38268000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53002.770083 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53002.770083 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53002.770083 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53002.770083 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53002.770083 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53002.770083 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 437952 # number of replacements -system.cpu.dcache.tagsinuse 4094.905905 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.905744 # Cycle average of tags in use system.cpu.dcache.total_refs 606786130 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 1372.670230 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 771462000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.905905 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 771786000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.905744 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 418844795 # number of ReadReq hits @@ -162,12 +162,12 @@ system.cpu.dcache.overall_misses::cpu.data 442048 # system.cpu.dcache.overall_misses::total 442048 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 2746552000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 2746552000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4104707000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4104707000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6851259000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6851259000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6851259000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6851259000 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4105029000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4105029000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6851581000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6851581000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6851581000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6851581000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 419042121 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 419042121 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) @@ -186,12 +186,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13918.855093 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 13918.855093 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16772.938273 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16772.938273 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15498.902834 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15498.902834 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15498.902834 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15498.902834 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16774.254052 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16774.254052 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15499.631262 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15499.631262 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,12 +212,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 442048 system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2351900000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2351900000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3615263000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3615263000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5967163000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5967163000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5967163000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5967163000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3615585000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3615585000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5967485000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5967485000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5967485000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5967485000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses @@ -228,26 +228,26 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14772.938273 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14772.938273 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13498.902834 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13498.902834 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13498.902834 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13498.902834 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14774.254052 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14774.254052 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2581 # number of replacements -system.cpu.l2cache.tagsinuse 22163.399604 # Cycle average of tags in use -system.cpu.l2cache.total_refs 506758 # Total number of references to valid blocks. +system.cpu.l2cache.replacements 2532 # number of replacements +system.cpu.l2cache.tagsinuse 22211.029339 # Cycle average of tags in use +system.cpu.l2cache.total_refs 519268 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.263763 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 21.788687 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21020.012941 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 596.858262 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 546.528401 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.641480 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.018215 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21021.301366 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 643.199216 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 546.528757 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.641519 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.019629 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.016679 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.676373 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.677827 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 193009 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 193009 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 422980 # number of Writeback hits @@ -269,17 +269,17 @@ system.cpu.l2cache.demand_misses::total 27009 # nu system.cpu.l2cache.overall_misses::cpu.inst 722 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 26287 # number of overall misses system.cpu.l2cache.overall_misses::total 27009 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37544000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37546000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 224484000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 262028000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1143021000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1143021000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 37544000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1367505000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1405049000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 37544000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1367505000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1405049000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 262030000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1143343000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1143343000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 37546000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1367827000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1405373000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 37546000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1367827000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1405373000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 722 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 197326 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 198048 # number of ReadReq accesses(hits+misses) @@ -304,17 +304,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.061000 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.059466 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.061000 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.770083 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52026.445152 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52026.445152 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52022.102180 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52021.511348 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52022.102180 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52021.511348 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.396904 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52041.101502 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52041.101502 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52002.770083 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52034.351581 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52033.507349 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52002.770083 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52034.351581 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52033.507349 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -323,8 +323,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2510 # number of writebacks -system.cpu.l2cache.writebacks::total 2510 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 2511 # number of writebacks +system.cpu.l2cache.writebacks::total 2511 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4317 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 5039 # number of ReadReq MSHR misses @@ -336,17 +336,17 @@ system.cpu.l2cache.demand_mshr_misses::total 27009 system.cpu.l2cache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 26287 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 27009 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28882000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 172680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201560000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 879381000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 879381000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1052061000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1080941000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1052061000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1080941000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201562000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 879703000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 879703000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28882000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1052383000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1081265000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28882000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1052383000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1081265000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021878 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.025443 # mshr miss rate for ReadReq accesses @@ -358,17 +358,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.061000 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059466 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.061000 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.770083 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40026.445152 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40026.445152 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40022.102180 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40021.511348 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40022.102180 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40021.511348 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.396904 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40041.101502 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40041.101502 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.770083 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40034.351581 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40033.507349 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.770083 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40034.351581 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40033.507349 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 0326fa208..7f5474242 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.025283 # Number of seconds simulated -sim_ticks 25283397500 # Number of ticks simulated -final_tick 25283397500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.027092 # Number of seconds simulated +sim_ticks 27092156000 # Number of ticks simulated +final_tick 27092156000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115178 # Simulator instruction rate (inst/s) -host_op_rate 116005 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32142506 # Simulator tick rate (ticks/s) -host_mem_usage 365228 # Number of bytes of host memory used -host_seconds 786.60 # Real time elapsed on the host -sim_insts 90599358 # Number of instructions simulated -sim_ops 91249911 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 45760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947520 # Number of bytes read from this memory +host_inst_rate 163409 # Simulator instruction rate (inst/s) +host_op_rate 164582 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48864627 # Simulator tick rate (ticks/s) +host_mem_usage 366512 # Number of bytes of host memory used +host_seconds 554.43 # Real time elapsed on the host +sim_insts 90599363 # Number of instructions simulated +sim_ops 91249916 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 45696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947584 # Number of bytes read from this memory system.physmem.bytes_read::total 993280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 45760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 45760 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 715 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14805 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 45696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45696 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 714 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14806 # Number of read requests responded to by this memory system.physmem.num_reads::total 15520 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1809883 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 37475976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 39285859 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1809883 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1809883 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1809883 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 37475976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 39285859 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1686687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 34976323 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36663011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1686687 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1686687 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1686687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 34976323 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 36663011 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15520 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 15520 # Reqs generatd by CPU via cache - shady @@ -36,21 +36,21 @@ system.physmem.bytesConsumedRd 993280 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1013 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 998 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 967 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1012 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 965 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 878 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 902 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 903 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 938 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 937 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 992 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 942 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 1013 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1040 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 931 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 934 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 935 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1022 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 998 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 999 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 977 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 25283243500 # Total gap between requests +system.physmem.totGap 27092026500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,16 +98,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 9030 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 10854 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4463 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 43058501 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 270142501 # Sum of mem lat for all requests +system.physmem.totQLat 41952001 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 275602001 # Sum of mem lat for all requests system.physmem.totBusLat 62080000 # Total cycles spent in databus access -system.physmem.totBankLat 165004000 # Total cycles spent in bank access -system.physmem.avgQLat 2774.39 # Average queueing delay per request -system.physmem.avgBankLat 10631.70 # Average bank access latency per request +system.physmem.totBankLat 171570000 # Total cycles spent in bank access +system.physmem.avgQLat 2703.09 # Average queueing delay per request +system.physmem.avgBankLat 11054.77 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 17406.09 # Average memory access latency -system.physmem.avgRdBW 39.29 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 17757.86 # Average memory access latency +system.physmem.avgRdBW 36.66 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 39.29 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 36.66 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.25 # Data bus utilization in percentage +system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 15094 # Number of row buffer hits during reads +system.physmem.readRowHits 15093 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 97.26 # Row buffer hit rate for reads +system.physmem.readRowHitRate 97.25 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1629074.97 # Average gap between requests +system.physmem.avgGap 1745620.26 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -228,628 +228,630 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 50566796 # number of cpu cycles simulated +system.cpu.numCycles 54184313 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 26827710 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22074051 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 888543 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11563656 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 11363946 # Number of BTB hits +system.cpu.BPredUnit.lookups 26986209 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 22240935 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 891955 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11647054 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 11461257 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 71231 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 482 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 14348377 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 128701471 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26827710 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11435177 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24213451 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4809546 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 8060195 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.BPredUnit.usedRAS 72758 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 485 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 14421407 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 129482789 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26986209 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11534015 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24364148 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4949387 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11145499 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 135 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14028280 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 377661 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 50539595 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.565225 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.255897 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 33 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 14072424 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 353920 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53972527 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.416768 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.215873 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 26364164 52.17% 52.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3431492 6.79% 58.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2034951 4.03% 62.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1571856 3.11% 66.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1677128 3.32% 69.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2962722 5.86% 75.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1482816 2.93% 78.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1106293 2.19% 80.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9908173 19.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29646325 54.93% 54.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3454402 6.40% 61.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2035756 3.77% 65.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1585198 2.94% 68.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1689643 3.13% 71.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2992855 5.55% 76.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1501294 2.78% 79.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1109449 2.06% 81.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9957605 18.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 50539595 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.530540 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.545177 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16886092 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6166490 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22746907 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 831459 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3908647 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4474881 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 9055 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126903101 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 43084 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3908647 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18602269 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1370571 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 152009 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21842488 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4663611 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123722180 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 282360 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3941818 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 144182082 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 538941570 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 538934983 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6587 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36752600 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6474 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6472 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 10800172 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29574364 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5545202 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2016944 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1216593 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118465493 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 10340 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105556460 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 69311 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27028341 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 66448905 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 210 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 50539595 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.088589 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.960694 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 53972527 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.498045 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.389673 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17207234 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9007840 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22744655 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 980413 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4032385 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4494708 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 9020 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 127545337 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 43010 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4032385 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 19020781 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3479230 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 185856 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21813074 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5441201 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 124457435 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 13 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 413531 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4571711 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1235 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 145128165 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 542105971 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 542097092 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 8879 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107429490 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 37698675 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6572 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6570 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12467133 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29726886 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5575716 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2113972 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1267479 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 119141743 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 10445 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105694934 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 87169 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27699731 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 68149614 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 314 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53972527 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.958310 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906959 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13663948 27.04% 27.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10566811 20.91% 47.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7991493 15.81% 63.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6436117 12.73% 76.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4858269 9.61% 86.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3518110 6.96% 93.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2381435 4.71% 97.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 601220 1.19% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 522192 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15655199 29.01% 29.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11785517 21.84% 50.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8331092 15.44% 66.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6816137 12.63% 78.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4950230 9.17% 88.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2999113 5.56% 93.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2477964 4.59% 98.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 523647 0.97% 99.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 433628 0.80% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 50539595 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53972527 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 142805 18.40% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 357317 46.04% 64.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 276029 35.56% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 46062 6.88% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 347309 51.84% 58.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 276528 41.28% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74650431 70.72% 70.72% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10952 0.01% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 213 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 258 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25757662 24.40% 95.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5136941 4.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74789995 70.76% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10964 0.01% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 273 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 352 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25743831 24.36% 95.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5149514 4.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105556460 # Type of FU issued -system.cpu.iq.rate 2.087466 # Inst issue rate -system.cpu.iq.fu_busy_cnt 776178 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007353 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 262497002 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 145505542 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102811583 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1002 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1425 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 429 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 106332135 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 503 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 448933 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105694934 # Type of FU issued +system.cpu.iq.rate 1.950656 # Inst issue rate +system.cpu.iq.fu_busy_cnt 669926 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006338 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 266118166 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 146855539 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 103065096 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1324 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1913 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 572 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 106364200 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 660 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 431890 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6998486 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7563 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 3836 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 798446 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7151007 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8111 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6407 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 828959 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 13664 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 30712 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3908647 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 40058 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10147 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118488563 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 346139 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29574364 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5545202 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6435 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4999 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 113 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 3836 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 475714 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 478249 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 953963 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104402584 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25308083 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1153876 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4032385 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 880978 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 122273 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 119164915 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 339993 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29726886 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5575716 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6543 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 65097 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6980 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6407 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 480710 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 474427 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 955137 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104665581 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25412111 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1029353 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12730 # number of nop insts executed -system.cpu.iew.exec_refs 30381749 # number of memory reference insts executed -system.cpu.iew.exec_branches 21354330 # Number of branches executed -system.cpu.iew.exec_stores 5073666 # Number of stores executed -system.cpu.iew.exec_rate 2.064647 # Inst execution rate -system.cpu.iew.wb_sent 103125475 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102812012 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62190160 # num instructions producing a value -system.cpu.iew.wb_consumers 104171478 # num instructions consuming a value +system.cpu.iew.exec_nop 12727 # number of nop insts executed +system.cpu.iew.exec_refs 30497033 # number of memory reference insts executed +system.cpu.iew.exec_branches 21398144 # Number of branches executed +system.cpu.iew.exec_stores 5084922 # Number of stores executed +system.cpu.iew.exec_rate 1.931658 # Inst execution rate +system.cpu.iew.wb_sent 103359257 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 103065668 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62382767 # num instructions producing a value +system.cpu.iew.wb_consumers 104584630 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.033192 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596998 # average fanout of values written-back +system.cpu.iew.wb_rate 1.902131 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596481 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 27226534 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 10130 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 879646 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 46630949 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.957123 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.526822 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 27905407 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 10131 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 883062 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49940143 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.827438 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.524426 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16429146 35.23% 35.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13384342 28.70% 63.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4483579 9.62% 73.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3865779 8.29% 81.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1521076 3.26% 85.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 802170 1.72% 86.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 837343 1.80% 88.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 265641 0.57% 89.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5041873 10.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20246507 40.54% 40.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13253757 26.54% 67.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4242903 8.50% 75.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3506121 7.02% 82.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1547134 3.10% 85.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 741508 1.48% 87.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 927602 1.86% 89.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 253977 0.51% 89.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5220634 10.45% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 46630949 # Number of insts commited each cycle -system.cpu.commit.committedInsts 90611967 # Number of instructions committed -system.cpu.commit.committedOps 91262520 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 49940143 # Number of insts commited each cycle +system.cpu.commit.committedInsts 90611972 # Number of instructions committed +system.cpu.commit.committedOps 91262525 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27322634 # Number of memory references committed -system.cpu.commit.loads 22575878 # Number of loads committed +system.cpu.commit.refs 27322636 # Number of memory references committed +system.cpu.commit.loads 22575879 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18734216 # Number of branches committed +system.cpu.commit.branches 18734217 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72533322 # Number of committed integer instructions. +system.cpu.commit.int_insts 72533326 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5041873 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5220634 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 160072396 # The number of ROB reads -system.cpu.rob.rob_writes 240909016 # The number of ROB writes -system.cpu.timesIdled 840 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27201 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 90599358 # Number of Instructions Simulated -system.cpu.committedOps 91249911 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 90599358 # Number of Instructions Simulated -system.cpu.cpi 0.558136 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.558136 # CPI: Total CPI of All Threads -system.cpu.ipc 1.791677 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.791677 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 496271114 # number of integer regfile reads -system.cpu.int_regfile_writes 120718739 # number of integer regfile writes -system.cpu.fp_regfile_reads 209 # number of floating regfile reads -system.cpu.fp_regfile_writes 557 # number of floating regfile writes -system.cpu.misc_regfile_reads 182190391 # number of misc regfile reads -system.cpu.misc_regfile_writes 11608 # number of misc regfile writes -system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 643.406523 # Cycle average of tags in use -system.cpu.icache.total_refs 14027306 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 744 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 18853.905914 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 163881707 # The number of ROB reads +system.cpu.rob.rob_writes 242387570 # The number of ROB writes +system.cpu.timesIdled 40508 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 211786 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 90599363 # Number of Instructions Simulated +system.cpu.committedOps 91249916 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 90599363 # Number of Instructions Simulated +system.cpu.cpi 0.598065 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.598065 # CPI: Total CPI of All Threads +system.cpu.ipc 1.672059 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.672059 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 497610089 # number of integer regfile reads +system.cpu.int_regfile_writes 120987803 # number of integer regfile writes +system.cpu.fp_regfile_reads 263 # number of floating regfile reads +system.cpu.fp_regfile_writes 760 # number of floating regfile writes +system.cpu.misc_regfile_reads 183141130 # number of misc regfile reads +system.cpu.misc_regfile_writes 11610 # number of misc regfile writes +system.cpu.icache.replacements 2 # number of replacements +system.cpu.icache.tagsinuse 641.121517 # Cycle average of tags in use +system.cpu.icache.total_refs 14071405 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 743 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 18938.633917 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 643.406523 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.314163 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.314163 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14027306 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14027306 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14027306 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14027306 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14027306 # number of overall hits -system.cpu.icache.overall_hits::total 14027306 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 974 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 974 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 974 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 974 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 974 # number of overall misses -system.cpu.icache.overall_misses::total 974 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30438500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30438500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30438500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30438500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30438500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30438500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14028280 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14028280 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14028280 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14028280 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14028280 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14028280 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000069 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000069 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000069 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000069 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000069 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000069 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31251.026694 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 31251.026694 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 31251.026694 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 31251.026694 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 31251.026694 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 31251.026694 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 641.121517 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.313048 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.313048 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14071405 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14071405 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14071405 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14071405 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14071405 # number of overall hits +system.cpu.icache.overall_hits::total 14071405 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1017 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1017 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1017 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1017 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1017 # number of overall misses +system.cpu.icache.overall_misses::total 1017 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 47244499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 47244499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 47244499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 47244499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 47244499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 47244499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14072422 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14072422 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14072422 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14072422 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14072422 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14072422 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000072 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000072 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000072 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000072 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000072 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000072 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46454.767945 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46454.767945 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46454.767945 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46454.767945 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46454.767945 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46454.767945 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 500 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 45.454545 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3668.756958 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.895693 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.895693 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23721969 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23721969 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4544209 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4544209 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5800 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5800 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 28266178 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28266178 # 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miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040649 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032299 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032299 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001367 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001367 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.039310 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.039310 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039310 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039310 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 4117.400078 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 4117.400078 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17488.639389 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17488.639389 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 5878.945470 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 5878.945470 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 5878.945470 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 5878.945470 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12644 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5800 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5800 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 29639919 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29639919 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29639919 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29639919 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047499 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047499 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040290 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.040290 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046348 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046348 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046348 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046348 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11773.240465 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11773.240465 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27316.736361 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27316.736361 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13931.772386 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13931.772386 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13931.772386 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13931.772386 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 151113 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6519 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23634 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 1.939561 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.393882 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # 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average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41348.318085 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41348.318085 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48999.300699 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41516.704914 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 41861.180864 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48999.300699 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41516.704914 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 41861.180864 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 27 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 13 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 715 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 267 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 982 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 715 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14805 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 714 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 269 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 983 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14537 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14537 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 714 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14806 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 15520 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 715 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14805 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 714 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14806 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15520 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20653050 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8351373 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 29004423 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 284430809 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 284430809 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20653050 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 292782182 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 313435232 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20653050 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 292782182 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 313435232 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961022 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000292 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001075 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.419652 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.419652 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961022 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 26001093 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10248888 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 36249981 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 418962782 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 418962782 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26001093 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 429211670 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 455212763 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26001093 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 429211670 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 455212763 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960969 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000297 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001083 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358593 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358593 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960969 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015623 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.016364 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961022 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960969 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015623 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016364 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28885.384615 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31278.550562 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29536.072301 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 19564.644999 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 19564.644999 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28885.384615 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 19775.898818 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 20195.569072 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28885.384615 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 19775.898818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 20195.569072 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36416.096639 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38099.955390 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36876.888098 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28820.443145 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28820.443145 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36416.096639 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28989.036202 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29330.719265 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36416.096639 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28989.036202 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29330.719265 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 9850fa37f..91d2f15f8 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.147136 # Nu sim_ticks 147135976000 # Number of ticks simulated final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1039833 # Simulator instruction rate (inst/s) -host_op_rate 1047288 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1689137215 # Simulator tick rate (ticks/s) -host_mem_usage 366884 # Number of bytes of host memory used -host_seconds 87.11 # Real time elapsed on the host +host_inst_rate 1200528 # Simulator instruction rate (inst/s) +host_op_rate 1209136 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1950176496 # Simulator tick rate (ticks/s) +host_mem_usage 364464 # Number of bytes of host memory used +host_seconds 75.45 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated sim_ops 91226312 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory @@ -280,9 +280,9 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 9565.271881 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1827210 # Total number of references to valid blocks. +system.cpu.l2cache.total_refs 1827177 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 15323 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 119.246231 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 119.244078 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 8876.925013 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index e3f69f56e..d610f9b78 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.361489 # Nu sim_ticks 361488530000 # Number of ticks simulated final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1171246 # Simulator instruction rate (inst/s) -host_op_rate 1171295 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1736457304 # Simulator tick rate (ticks/s) -host_mem_usage 354676 # Number of bytes of host memory used -host_seconds 208.18 # Real time elapsed on the host +host_inst_rate 1414417 # Simulator instruction rate (inst/s) +host_op_rate 1414475 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2096975339 # Simulator tick rate (ticks/s) +host_mem_usage 357072 # Number of bytes of host memory used +host_seconds 172.39 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory @@ -250,9 +250,9 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 9730.625290 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1813121 # Total number of references to valid blocks. +system.cpu.l2cache.total_refs 1813290 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 15586 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 116.330104 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 116.340947 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index ea6cef3aa..973686ac9 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.061268 # Number of seconds simulated -sim_ticks 61267871000 # Number of ticks simulated -final_tick 61267871000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.067525 # Number of seconds simulated +sim_ticks 67525253000 # Number of ticks simulated +final_tick 67525253000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120787 # Simulator instruction rate (inst/s) -host_op_rate 212686 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46841085 # Simulator tick rate (ticks/s) -host_mem_usage 363680 # Number of bytes of host memory used -host_seconds 1307.99 # Real time elapsed on the host +host_inst_rate 116144 # Simulator instruction rate (inst/s) +host_op_rate 204512 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49640781 # Simulator tick rate (ticks/s) +host_mem_usage 364964 # Number of bytes of host memory used +host_seconds 1360.28 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192462 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 68800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1893248 # Number of bytes read from this memory -system.physmem.bytes_read::total 1962048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 68800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 68800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 20608 # Number of bytes written to this memory -system.physmem.bytes_written::total 20608 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1075 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29582 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30657 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 322 # Number of write requests responded to by this memory -system.physmem.num_writes::total 322 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1122938 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 30901155 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 32024093 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1122938 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1122938 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 336359 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 336359 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 336359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1122938 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 30901155 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 32360452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30662 # Total number of read requests seen -system.physmem.writeReqs 322 # Total number of write requests seen -system.physmem.cpureqs 30989 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1962048 # Total number of bytes read from memory -system.physmem.bytesWritten 20608 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1962048 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 20608 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 28 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 5 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1936 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1969 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 2038 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 2024 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1986 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1872 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1877 # Track reads on a per bank basis +system.physmem.bytes_read::cpu.inst 66944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1886080 # Number of bytes read from this memory +system.physmem.bytes_read::total 1953024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 66944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 66944 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 13568 # Number of bytes written to this memory +system.physmem.bytes_written::total 13568 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1046 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29470 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30516 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 212 # Number of write requests responded to by this memory +system.physmem.num_writes::total 212 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 991392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 27931476 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 28922868 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 991392 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 991392 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 200932 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 200932 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 200932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 991392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 27931476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29123801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30518 # Total number of read requests seen +system.physmem.writeReqs 212 # Total number of write requests seen +system.physmem.cpureqs 30733 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1953024 # Total number of bytes read from memory +system.physmem.bytesWritten 13568 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1953024 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 13568 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 63 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 3 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 1916 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1956 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 2028 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 2002 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1974 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1871 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1873 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1862 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1926 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1900 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1830 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1925 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1905 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1826 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1923 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1961 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1876 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1914 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1878 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1871 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1771 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 18 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 14 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 124 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 18 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 19 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 2 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 4 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 4 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 18 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 11 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 8 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 12 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 55 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 3 # Track writes on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 119 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 23 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 1 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 17 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 6 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 12 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 1 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 10 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 61267857000 # Total gap between requests +system.physmem.totGap 67525239000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 30662 # Categorize read packet sizes +system.physmem.readPktSize::6 30518 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 322 # categorize write packet sizes +system.physmem.writePktSize::6 212 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,16 +102,16 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 5 # categorize neither packet sizes +system.physmem.neitherpktsize::6 3 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 29991 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 29919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -138,30 +138,30 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -171,265 +171,266 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 14166089 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 582752089 # Sum of mem lat for all requests -system.physmem.totBusLat 122532000 # Total cycles spent in databus access -system.physmem.totBankLat 446054000 # Total cycles spent in bank access -system.physmem.avgQLat 462.43 # Average queueing delay per request -system.physmem.avgBankLat 14560.75 # Average bank access latency per request -system.physmem.avgBusLat 3999.87 # Average bus latency per request -system.physmem.avgMemAccLat 19023.05 # Average memory access latency -system.physmem.avgRdBW 32.02 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.34 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 32.02 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.34 # Average consumed write bandwidth in MB/s +system.physmem.totQLat 11553430 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 574779430 # Sum of mem lat for all requests +system.physmem.totBusLat 121820000 # Total cycles spent in databus access +system.physmem.totBankLat 441406000 # Total cycles spent in bank access +system.physmem.avgQLat 379.36 # Average queueing delay per request +system.physmem.avgBankLat 14493.71 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 18873.07 # Average memory access latency +system.physmem.avgRdBW 28.92 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.20 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 28.92 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.20 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.20 # Data bus utilization in percentage +system.physmem.busUtil 0.18 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 4.97 # Average write queue length over time -system.physmem.readRowHits 29782 # Number of row buffer hits during reads -system.physmem.writeRowHits 175 # Number of row buffer hits during writes -system.physmem.readRowHitRate 97.22 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 54.35 # Row buffer hit rate for writes -system.physmem.avgGap 1977403.08 # Average gap between requests +system.physmem.avgWrQLen 2.27 # Average write queue length over time +system.physmem.readRowHits 29673 # Number of row buffer hits during reads +system.physmem.writeRowHits 71 # Number of row buffer hits during writes +system.physmem.readRowHitRate 97.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 33.49 # Row buffer hit rate for writes +system.physmem.avgGap 2197371.92 # Average gap between requests system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 122535743 # number of cpu cycles simulated +system.cpu.numCycles 135050507 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 35570832 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 35570832 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1084026 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 25425275 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 25293552 # Number of BTB hits +system.cpu.BPredUnit.lookups 35279612 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 35279612 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1097690 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 25134949 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 25035866 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27817646 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 193664357 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35570832 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 25293552 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 58615511 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7353362 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 29831602 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 154 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 27179590 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 325172 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 122507486 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.779073 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.404197 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27689493 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 190877273 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35279612 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 25035866 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 58050662 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 7148119 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 43215578 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 200 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 26932643 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 266231 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 134969887 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.491492 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.329843 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66630267 54.39% 54.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2068884 1.69% 56.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2984971 2.44% 58.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3999258 3.26% 61.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7980935 6.51% 68.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5030075 4.11% 72.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2863623 2.34% 74.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1430988 1.17% 75.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 29518485 24.10% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 79660068 59.02% 59.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2061386 1.53% 60.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3001296 2.22% 62.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4024404 2.98% 65.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7960578 5.90% 71.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4856128 3.60% 75.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2895673 2.15% 77.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1440638 1.07% 78.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 29069716 21.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 122507486 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.290289 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.580472 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 38875412 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 22176556 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 48070998 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7141971 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6242549 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336118074 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 6242549 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 43268905 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2886935 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6989 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 50676752 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 19425356 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 332235244 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 62 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 9392 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 17753597 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 139 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 334580463 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 881428154 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 881426042 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2112 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 134969887 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.261233 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.413377 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 38714097 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 35595607 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46068800 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8577479 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6013904 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 332373669 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 6013904 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44296876 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8440142 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9061 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 48816518 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27393386 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 327323595 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 229 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 40548 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 25654370 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 357 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 329853596 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 868074055 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 868071866 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2189 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212744 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 55367719 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 486 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 482 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 44129062 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104954101 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 36485312 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 41562946 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5830806 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 323945312 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1773 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 307769548 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 217281 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 45552285 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 66549913 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1327 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 122507486 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.512251 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.799024 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 50640852 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 483 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 476 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 61788867 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104142858 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 36158946 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40039032 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6050954 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 321707041 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1738 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 307032101 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 190555 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 42805778 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 61072777 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1292 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 134969887 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.274819 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.710764 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 21268867 17.36% 17.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 16938160 13.83% 31.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24590210 20.07% 51.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 23966706 19.56% 70.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19077143 15.57% 86.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 9190745 7.50% 93.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4997191 4.08% 97.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2322305 1.90% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 156159 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 26262527 19.46% 19.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23269182 17.24% 36.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 26059494 19.31% 56.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 26258264 19.45% 75.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19354972 14.34% 89.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8435024 6.25% 96.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4232889 3.14% 99.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 903483 0.67% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 194052 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 122507486 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 134969887 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 51278 1.98% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1865528 72.01% 73.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 673849 26.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 32987 1.63% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1843971 90.87% 92.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 152228 7.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 33341 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 174913911 56.83% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 42 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 98825778 32.11% 88.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33996476 11.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 31299 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 174160366 56.72% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 56 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 99035655 32.26% 88.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33804725 11.01% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 307769548 # Type of FU issued -system.cpu.iq.rate 2.511672 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2590655 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008418 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 740853926 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 369529188 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 304569650 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 592 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1017 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 187 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 310326577 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 285 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 52294659 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 307032101 # Type of FU issued +system.cpu.iq.rate 2.273461 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2029186 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006609 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 751253230 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 364547081 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 303801599 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 600 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1091 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 195 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 309029699 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 289 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 54104965 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14174717 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 50650 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 31690 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 5045561 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13363474 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 46851 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34646 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4719195 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3163 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3287 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8523 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6242549 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 128946 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5786 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 323947085 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 341652 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104954101 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 36485312 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 6013904 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1728221 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 160274 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 321708779 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 372174 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104142858 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 36158946 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 475 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 376 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 886 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 31690 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 595739 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 583103 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1178842 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 305571382 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 98206856 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2198166 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 3195 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73111 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34646 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 603719 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 587627 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1191346 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 304994543 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 98411821 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2037558 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 131649773 # number of memory reference insts executed -system.cpu.iew.exec_branches 31223750 # Number of branches executed -system.cpu.iew.exec_stores 33442917 # Number of stores executed -system.cpu.iew.exec_rate 2.493733 # Inst execution rate -system.cpu.iew.wb_sent 304986534 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 304569837 # cumulative count of insts written-back -system.cpu.iew.wb_producers 226002140 # num instructions producing a value -system.cpu.iew.wb_consumers 312068538 # num instructions consuming a value +system.cpu.iew.exec_refs 131928718 # number of memory reference insts executed +system.cpu.iew.exec_branches 31180940 # Number of branches executed +system.cpu.iew.exec_stores 33516897 # Number of stores executed +system.cpu.iew.exec_rate 2.258374 # Inst execution rate +system.cpu.iew.wb_sent 304306961 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 303801794 # cumulative count of insts written-back +system.cpu.iew.wb_producers 222946371 # num instructions producing a value +system.cpu.iew.wb_consumers 302902430 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.485559 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.724207 # average fanout of values written-back +system.cpu.iew.wb_rate 2.249542 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736034 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 45756293 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 43529723 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1084042 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 116264937 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.392746 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.783730 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1097716 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 128955983 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.157267 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.943706 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 38380575 33.01% 33.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22255868 19.14% 52.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 17068651 14.68% 66.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13099730 11.27% 78.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2025175 1.74% 79.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3235783 2.78% 82.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1359435 1.17% 83.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 653883 0.56% 84.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 18185837 15.64% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59867865 46.43% 46.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19620961 15.22% 61.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11973021 9.28% 70.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9656574 7.49% 78.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1838556 1.43% 79.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2079674 1.61% 81.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1347744 1.05% 82.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 756025 0.59% 83.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 21815563 16.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 116264937 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 128955983 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192462 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -440,305 +441,307 @@ system.cpu.commit.branches 29309705 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186170 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 18185837 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 21815563 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 422027855 # The number of ROB reads -system.cpu.rob.rob_writes 654145762 # The number of ROB writes -system.cpu.timesIdled 622 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 28257 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 428862605 # The number of ROB reads +system.cpu.rob.rob_writes 649464240 # The number of ROB writes +system.cpu.timesIdled 14220 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 80620 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.775599 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.775599 # CPI: Total CPI of All Threads -system.cpu.ipc 1.289326 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.289326 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 598644238 # number of integer regfile reads -system.cpu.int_regfile_writes 305189502 # number of integer regfile writes -system.cpu.fp_regfile_reads 171 # number of floating regfile reads -system.cpu.fp_regfile_writes 94 # number of floating regfile writes -system.cpu.misc_regfile_reads 195525442 # number of misc regfile reads -system.cpu.icache.replacements 87 # number of replacements -system.cpu.icache.tagsinuse 849.665087 # Cycle average of tags in use -system.cpu.icache.total_refs 27178218 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1083 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25095.307479 # Average number of references to valid blocks. +system.cpu.cpi 0.854812 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.854812 # CPI: Total CPI of All Threads +system.cpu.ipc 1.169848 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.169848 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 599211234 # number of integer regfile reads +system.cpu.int_regfile_writes 304304879 # number of integer regfile writes +system.cpu.fp_regfile_reads 178 # number of floating regfile reads +system.cpu.fp_regfile_writes 115 # number of floating regfile writes +system.cpu.misc_regfile_reads 195413561 # number of misc regfile reads +system.cpu.icache.replacements 78 # number of replacements +system.cpu.icache.tagsinuse 851.671106 # Cycle average of tags in use +system.cpu.icache.total_refs 26931242 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1068 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 25216.518727 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 849.665087 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.414876 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.414876 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 27178218 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27178218 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27178218 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27178218 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27178218 # number of overall hits -system.cpu.icache.overall_hits::total 27178218 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1372 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1372 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1372 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1372 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1372 # number of overall misses -system.cpu.icache.overall_misses::total 1372 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 45099500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 45099500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 45099500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 45099500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 45099500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 45099500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27179590 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27179590 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27179590 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27179590 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27179590 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27179590 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000050 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000050 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000050 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000050 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000050 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000050 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 32871.355685 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 32871.355685 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 32871.355685 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 32871.355685 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 32871.355685 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 32871.355685 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 851.671106 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.415855 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.415855 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 26931243 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 26931243 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 26931243 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 26931243 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 26931243 # number of overall hits +system.cpu.icache.overall_hits::total 26931243 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1400 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1400 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1400 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1400 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1400 # number of overall misses +system.cpu.icache.overall_misses::total 1400 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 66418500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 66418500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 66418500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 66418500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 66418500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 66418500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 26932643 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 26932643 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 26932643 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 26932643 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 26932643 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 26932643 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47441.785714 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 47441.785714 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 47441.785714 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 47441.785714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 47441.785714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 47441.785714 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 168 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 283 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 283 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 283 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 283 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 283 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 283 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1089 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1089 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1089 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1089 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1089 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1089 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36146000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36146000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36146000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36146000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36146000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36146000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 328 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 328 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 328 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 328 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 328 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1072 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1072 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1072 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1072 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1072 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1072 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52640000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 52640000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52640000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 52640000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52640000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 52640000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33191.919192 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33191.919192 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33191.919192 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 33191.919192 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33191.919192 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 33191.919192 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49104.477612 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49104.477612 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49104.477612 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49104.477612 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49104.477612 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49104.477612 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2071993 # number of replacements -system.cpu.dcache.tagsinuse 4071.813370 # Cycle average of tags in use -system.cpu.dcache.total_refs 74974075 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2076089 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 36.113131 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21436010000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4071.813370 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994095 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994095 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 43616503 # 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number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45872962 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2072134 # number of replacements +system.cpu.dcache.tagsinuse 4072.225954 # Cycle average of tags in use +system.cpu.dcache.total_refs 72984548 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2076230 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 35.152439 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 22141542000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.225954 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994196 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994196 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 41643096 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 41643096 # 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number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 77312713 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 77312713 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 77312713 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 77312713 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049189 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.049189 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002614 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002614 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.030249 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.030249 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.030249 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.030249 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 4030.036664 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 4030.036664 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 11897.692982 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 11897.692982 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 4306.519849 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 4306.519849 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 4306.519849 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 4306.519849 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 75700823 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 75700823 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 75700823 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 75700823 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.059148 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.059148 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003127 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003127 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.035882 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.035882 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.035882 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.035882 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11952.389747 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11952.389747 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21266.226876 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21266.226876 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12289.480300 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12289.480300 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12289.480300 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12289.480300 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32223 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9490 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.395469 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2064741 # number of writebacks -system.cpu.dcache.writebacks::total 2064741 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 262443 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 262443 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 102 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 102 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 262545 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 262545 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 262545 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 262545 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994016 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994016 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82082 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82082 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076098 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076098 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076098 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076098 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4062202500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4062202500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 812900500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 812900500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4875103000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4875103000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4875103000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4875103000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.043468 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.043468 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002611 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002611 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026853 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026853 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026853 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026853 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2037.196542 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2037.196542 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9903.517214 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9903.517214 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 2348.204661 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 2348.204661 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 2348.204661 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 2348.204661 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2065967 # number of writebacks +system.cpu.dcache.writebacks::total 2065967 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 623929 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 623929 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16120 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16120 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 640049 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 640049 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 640049 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 640049 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994047 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994047 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82189 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82189 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076236 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076236 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076236 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076236 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21985403000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21985403000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1815582998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1815582998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23800985998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23800985998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23800985998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23800985998 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045052 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045052 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002614 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002614 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027427 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027427 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027427 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027427 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11025.518957 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11025.518957 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22090.340532 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22090.340532 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11463.526303 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11463.526303 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11463.526303 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11463.526303 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1477 # number of replacements -system.cpu.l2cache.tagsinuse 19662.234768 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4026933 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 30639 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 131.431607 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 547 # number of replacements +system.cpu.l2cache.tagsinuse 20637.745612 # Cycle average of tags in use +system.cpu.l2cache.total_refs 4028284 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 30500 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 132.074885 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 19155.060613 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 278.346040 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 228.828114 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.584566 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.008494 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.006983 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.600044 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 8 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1993342 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1993350 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2064741 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2064741 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 53165 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 53165 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2046507 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2046515 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2046507 # number of overall hits -system.cpu.l2cache.overall_hits::total 2046515 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1076 # 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number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 30003 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 826405394 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 826405394 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38163141 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 843867119 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 882030260 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38163141 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 843867119 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 882030260 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.979401 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000234 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000758 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.750000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.750000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352529 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352529 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.979401 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014195 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014691 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.979401 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014195 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014691 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36484.838432 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37391.274090 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36764.617317 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28491.825340 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28491.825340 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36484.838432 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28632.841986 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28901.968019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36484.838432 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28632.841986 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28901.968019 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 0458ec538..c24d579f7 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.365994 # Number of seconds simulated -sim_ticks 365994481000 # Number of ticks simulated -final_tick 365994481000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.365989 # Number of seconds simulated +sim_ticks 365989063000 # Number of ticks simulated +final_tick 365989063000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 452383 # Simulator instruction rate (inst/s) -host_op_rate 796575 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1047986231 # Simulator tick rate (ticks/s) -host_mem_usage 363904 # Number of bytes of host memory used -host_seconds 349.24 # Real time elapsed on the host +host_inst_rate 621192 # Simulator instruction rate (inst/s) +host_op_rate 1093819 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1439024491 # Simulator tick rate (ticks/s) +host_mem_usage 361884 # Number of bytes of host memory used +host_seconds 254.33 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192463 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1879680 # Number of bytes read from this memory -system.physmem.bytes_read::total 1931392 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 51712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 51712 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 14528 # Number of bytes written to this memory -system.physmem.bytes_written::total 14528 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 808 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29370 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30178 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 227 # Number of write requests responded to by this memory -system.physmem.num_writes::total 227 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 141292 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5135815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5277107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 141292 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 141292 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 39695 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 39695 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 39695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 141292 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5135815 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5316801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory +system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6400 # Number of bytes written to this memory +system.physmem.bytes_written::total 6400 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29246 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30049 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 100 # Number of write requests responded to by this memory +system.physmem.num_writes::total 100 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 140419 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5114207 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5254627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 140419 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 140419 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17487 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17487 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17487 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 731988962 # number of cpu cycles simulated +system.cpu.numCycles 731978126 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 157988548 # Number of instructions committed @@ -54,16 +54,16 @@ system.cpu.num_mem_refs 122219135 # nu system.cpu.num_load_insts 90779384 # Number of load instructions system.cpu.num_store_insts 31439751 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 731988962 # Number of busy cycles +system.cpu.num_busy_cycles 731978126 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 665.633473 # Cycle average of tags in use +system.cpu.icache.tagsinuse 665.632511 # Cycle average of tags in use system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 665.633473 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 665.632511 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.325016 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 808 # n system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses system.cpu.icache.overall_misses::total 808 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44440000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44440000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44440000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44440000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44440000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44440000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44230000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44230000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44230000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44230000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44230000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 217696165 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 217696165 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 217696165 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.099010 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54740.099010 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54740.099010 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54740.099010 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 808 system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42824000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42824000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42824000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42824000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42824000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42824000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42614000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42614000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42614000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42614000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42614000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42614000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52740.099010 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52740.099010 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2062733 # number of replacements -system.cpu.dcache.tagsinuse 4076.488929 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4076.488641 # Cycle average of tags in use system.cpu.dcache.total_refs 120152368 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 58.133676 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 126079699000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.488929 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995237 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995237 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4076.488641 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995236 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 2066829 # n system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses system.cpu.dcache.overall_misses::total 2066829 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25503766000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25503766000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598582000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2598582000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28102348000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28102348000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28102348000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28102348000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.347301 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.347301 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24489.741681 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24489.741681 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13596.842313 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13596.842313 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13596.842313 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13596.842313 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2061794 # number of writebacks -system.cpu.dcache.writebacks::total 2061794 # number of writebacks +system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks +system.cpu.dcache.writebacks::total 2062484 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21582326000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21582326000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386364000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386364000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23968690000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23968690000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23968690000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23968690000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21577244000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21577244000 # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.589789 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.006430 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.004345 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.600563 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 1960377 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1960377 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2061794 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2061794 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 77082 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 77082 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 2037459 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2037459 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 2037459 # 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miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.273558 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014210 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014595 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014210 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014595 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000113 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000523 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000587 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273558 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273558 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014210 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014595 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014210 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014595 # mshr miss rate for overall accesses +system.cpu.l2cache.writebacks::writebacks 100 # number of writebacks +system.cpu.l2cache.writebacks::total 100 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1025 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29246 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30049 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29246 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30049 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32120000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41000000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1160960000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1160960000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1169840000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1201960000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1169840000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1201960000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000113 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000523 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014533 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014533 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 0b0da80ad..c7236dc45 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.201821 # Number of seconds simulated -sim_ticks 201820850500 # Number of ticks simulated -final_tick 201820850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.209792 # Number of seconds simulated +sim_ticks 209791572500 # Number of ticks simulated +final_tick 209791572500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 158073 # Simulator instruction rate (inst/s) -host_op_rate 178071 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62682331 # Simulator tick rate (ticks/s) -host_mem_usage 261124 # Number of bytes of host memory used -host_seconds 3219.74 # Real time elapsed on the host -sim_insts 508955148 # Number of instructions simulated -sim_ops 573341708 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 219776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10015744 # Number of bytes read from this memory -system.physmem.bytes_read::total 10235520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219776 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6680640 # Number of bytes written to this memory -system.physmem.bytes_written::total 6680640 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3434 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 156496 # Number of read requests responded to by this memory -system.physmem.num_reads::total 159930 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 104385 # Number of write requests responded to by this memory -system.physmem.num_writes::total 104385 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1088966 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 49626904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50715870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1088966 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1088966 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 33101833 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 33101833 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 33101833 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1088966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 49626904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 83817702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 159931 # Total number of read requests seen -system.physmem.writeReqs 104385 # Total number of write requests seen -system.physmem.cpureqs 264320 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10235520 # Total number of bytes read from memory -system.physmem.bytesWritten 6680640 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10235520 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6680640 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 186 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 9715 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10028 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 9563 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 9185 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 9586 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 9626 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9845 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10204 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 9902 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 11404 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10776 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10740 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9984 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9763 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 9956 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 9468 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 6164 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6588 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6206 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6224 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6375 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6383 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6446 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6854 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 6435 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7038 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6926 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6925 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6680 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6603 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6451 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6087 # Track writes on a per bank basis +host_inst_rate 156369 # Simulator instruction rate (inst/s) +host_op_rate 176151 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64455547 # Simulator tick rate (ticks/s) +host_mem_usage 260364 # Number of bytes of host memory used +host_seconds 3254.83 # Real time elapsed on the host +sim_insts 508955223 # Number of instructions simulated +sim_ops 573341783 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 217152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9263872 # Number of bytes read from this memory +system.physmem.bytes_read::total 9481024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 217152 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 217152 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6251520 # Number of bytes written to this memory +system.physmem.bytes_written::total 6251520 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3393 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144748 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148141 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97680 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97680 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1035084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 44157503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 45192588 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1035084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1035084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 29798718 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 29798718 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 29798718 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1035084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 44157503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 74991306 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148142 # Total number of read requests seen +system.physmem.writeReqs 97680 # Total number of write requests seen +system.physmem.cpureqs 245829 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 9481024 # Total number of bytes read from memory +system.physmem.bytesWritten 6251520 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 9481024 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6251520 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 73 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 7 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 9201 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 9165 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 9345 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8789 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 9221 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 8969 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9229 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 9489 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 9153 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10287 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 9703 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9687 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 9133 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 8953 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 8996 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8749 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5968 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6117 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6110 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5946 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6121 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 5961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6032 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6371 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5972 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6670 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6298 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6310 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6055 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6063 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5907 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5779 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 201820829500 # Total gap between requests +system.physmem.totGap 209791554000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 159931 # Categorize read packet sizes +system.physmem.readPktSize::6 148142 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 104385 # categorize write packet sizes +system.physmem.writePktSize::6 97680 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,16 +102,16 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4 # categorize neither packet sizes +system.physmem.neitherpktsize::6 7 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 148144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 10717 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 21 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 138253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 546 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -138,31 +138,31 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,27 +171,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1228593768 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4610173768 # Sum of mem lat for all requests -system.physmem.totBusLat 638980000 # Total cycles spent in databus access -system.physmem.totBankLat 2742600000 # Total cycles spent in bank access -system.physmem.avgQLat 7690.97 # Average queueing delay per request -system.physmem.avgBankLat 17168.61 # Average bank access latency per request +system.physmem.totQLat 1634133662 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4706663662 # Sum of mem lat for all requests +system.physmem.totBusLat 592276000 # Total cycles spent in databus access +system.physmem.totBankLat 2480254000 # Total cycles spent in bank access +system.physmem.avgQLat 11036.30 # Average queueing delay per request +system.physmem.avgBankLat 16750.66 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28859.58 # Average memory access latency -system.physmem.avgRdBW 50.72 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 33.10 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.72 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 33.10 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 31786.96 # Average memory access latency +system.physmem.avgRdBW 45.19 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 29.80 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 45.19 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 29.80 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.52 # Data bus utilization in percentage +system.physmem.busUtil 0.47 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 8.69 # Average write queue length over time -system.physmem.readRowHits 136302 # Number of row buffer hits during reads -system.physmem.writeRowHits 64360 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.32 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 61.66 # Row buffer hit rate for writes -system.physmem.avgGap 763558.88 # Average gap between requests +system.physmem.avgWrQLen 8.47 # Average write queue length over time +system.physmem.readRowHits 128571 # Number of row buffer hits during reads +system.physmem.writeRowHits 35065 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 35.90 # Row buffer hit rate for writes +system.physmem.avgGap 853428.72 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,143 +235,144 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 403641702 # number of cpu cycles simulated +system.cpu.numCycles 419583146 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 183652385 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 143319168 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 7791559 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 98117243 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 90149856 # Number of BTB hits +system.cpu.BPredUnit.lookups 184787901 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 144275662 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7821695 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 98666438 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 90672892 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 12789076 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 115438 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 119026376 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 771196614 # Number of instructions fetch has processed -system.cpu.fetch.Branches 183652385 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 102938932 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 173108927 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 37044032 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 80186575 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 394 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 114778688 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2637185 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 400780006 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.162952 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.978630 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 12865720 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 116804 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 120063384 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 775942019 # Number of instructions fetch has processed +system.cpu.fetch.Branches 184787901 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 103538612 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 174228692 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 37833268 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 88961490 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 89 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 441 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 46 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 115656461 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2629290 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 412465751 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.114116 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.961632 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 227683870 56.81% 56.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14342886 3.58% 60.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 23399081 5.84% 66.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22963566 5.73% 71.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20939416 5.22% 77.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13281175 3.31% 80.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13284797 3.31% 83.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12117870 3.02% 86.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52767345 13.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 238249907 57.76% 57.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14509257 3.52% 61.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 23515530 5.70% 66.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 23126111 5.61% 72.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21084782 5.11% 77.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13401568 3.25% 80.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13317687 3.23% 84.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 12258730 2.97% 87.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 53002179 12.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 400780006 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.454989 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.910597 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129077693 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 74884830 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 163721203 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4713887 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 28382393 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26602700 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 78428 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 842461319 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 313133 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 28382393 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 136940970 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4647966 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 57066662 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 160444938 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13297077 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 812260436 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 946 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2860927 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 6878465 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 58 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 967590618 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3556107711 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3556106126 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1585 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 672200171 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 295390447 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3042631 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3042626 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43966533 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172435046 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 75040987 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 27084528 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 14183257 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 762885569 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4467405 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 672287055 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1597234 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 191943939 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 493452075 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 746288 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 400780006 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.677447 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.741326 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 412465751 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.440408 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.849316 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 130727660 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 83050170 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 164137621 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5414105 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 29136195 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26733440 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 78480 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 847595839 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 313311 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 29136195 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139084470 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9565310 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 58010596 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 161019235 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15649945 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 817254433 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1177 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3017136 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8708482 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 277 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 973333611 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3577975971 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3577974311 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1660 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 672200291 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 301133320 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3043156 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3043152 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 48850446 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 173854149 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 75418146 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 27836757 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 16204833 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 768087050 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4468097 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 675015149 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1537645 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 197142364 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 504679775 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 746965 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 412465751 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.636536 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.726020 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 142470034 35.55% 35.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 73884527 18.44% 53.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 68392945 17.06% 71.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53248174 13.29% 84.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 32249720 8.05% 92.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16393621 4.09% 96.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9384825 2.34% 98.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3453099 0.86% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1303061 0.33% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 150311678 36.44% 36.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 76712349 18.60% 55.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 69700446 16.90% 71.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 54263544 13.16% 85.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31204898 7.57% 92.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16238502 3.94% 96.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9395018 2.28% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3385462 0.82% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1253854 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 400780006 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 412465751 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 434732 4.35% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6807090 68.10% 72.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2754377 27.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 459279 4.79% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6599656 68.89% 73.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2521285 26.32% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 451597333 67.17% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 385890 0.06% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 453432070 67.17% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 386675 0.06% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 120 0.00% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued @@ -397,417 +398,413 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.23% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 155180120 23.08% 90.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 65123593 9.69% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 156063229 23.12% 90.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 65133052 9.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 672287055 # Type of FU issued -system.cpu.iq.rate 1.665554 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9996199 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014869 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1756947282 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 960099456 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 651370563 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 267 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 364 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 675015149 # Type of FU issued +system.cpu.iq.rate 1.608776 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9580220 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014193 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1773613639 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 970503516 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 654104832 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 275 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 376 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 682283119 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 135 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8423591 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 684595230 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 139 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8576140 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 45662006 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 43583 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 806705 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 17437025 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 47081094 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 45082 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810201 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 17814169 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19460 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 290 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19569 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4173 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 28382393 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1656439 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 73515 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 768921673 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1234448 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172435046 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 75040987 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2978685 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 37777 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4191 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 806705 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4752820 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4170938 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8923758 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 661908420 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 151549628 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10378635 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 29136195 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4987646 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 377782 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 774132367 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1246249 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 173854149 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 75418146 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2979362 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 225001 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11770 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810201 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4778565 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4193502 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8972067 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 664703563 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 152403506 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10311586 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1568699 # number of nop insts executed -system.cpu.iew.exec_refs 215209256 # number of memory reference insts executed -system.cpu.iew.exec_branches 139387977 # Number of branches executed -system.cpu.iew.exec_stores 63659628 # Number of stores executed -system.cpu.iew.exec_rate 1.639842 # Inst execution rate -system.cpu.iew.wb_sent 656622179 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 651370579 # cumulative count of insts written-back -system.cpu.iew.wb_producers 376034680 # num instructions producing a value -system.cpu.iew.wb_consumers 649424114 # num instructions consuming a value +system.cpu.iew.exec_nop 1577220 # number of nop insts executed +system.cpu.iew.exec_refs 216142633 # number of memory reference insts executed +system.cpu.iew.exec_branches 139998635 # Number of branches executed +system.cpu.iew.exec_stores 63739127 # Number of stores executed +system.cpu.iew.exec_rate 1.584200 # Inst execution rate +system.cpu.iew.wb_sent 659363122 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 654104848 # cumulative count of insts written-back +system.cpu.iew.wb_producers 377540372 # num instructions producing a value +system.cpu.iew.wb_consumers 650138040 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.613735 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579028 # average fanout of values written-back +system.cpu.iew.wb_rate 1.558940 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.580708 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 194250034 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3721117 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7716233 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 372397614 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.543204 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.198347 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 199474656 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3721132 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 7746281 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 383329557 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.499195 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.189163 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 159514435 42.83% 42.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 102731237 27.59% 70.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 34442629 9.25% 79.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18453291 4.96% 84.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 17522832 4.71% 89.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7762690 2.08% 91.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6910466 1.86% 93.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3138622 0.84% 94.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 21921412 5.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 170483153 44.47% 44.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 103125969 26.90% 71.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 34389586 8.97% 80.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 19012192 4.96% 85.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16256916 4.24% 89.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7587599 1.98% 91.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6965408 1.82% 93.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3084029 0.80% 94.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22424705 5.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 372397614 # Number of insts commited each cycle -system.cpu.commit.committedInsts 510299032 # Number of instructions committed -system.cpu.commit.committedOps 574685592 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 383329557 # Number of insts commited each cycle +system.cpu.commit.committedInsts 510299107 # Number of instructions committed +system.cpu.commit.committedOps 574685667 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 184377002 # Number of memory references committed -system.cpu.commit.loads 126773040 # Number of loads committed +system.cpu.commit.refs 184377032 # Number of memory references committed +system.cpu.commit.loads 126773055 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 122291786 # Number of branches committed +system.cpu.commit.branches 122291801 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 473701633 # Number of committed integer instructions. +system.cpu.commit.int_insts 473701693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 21921412 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22424705 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1119404690 # The number of ROB reads -system.cpu.rob.rob_writes 1566395163 # The number of ROB writes -system.cpu.timesIdled 33245 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2861696 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 508955148 # Number of Instructions Simulated -system.cpu.committedOps 573341708 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 508955148 # Number of Instructions Simulated -system.cpu.cpi 0.793079 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.793079 # CPI: Total CPI of All Threads -system.cpu.ipc 1.260908 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.260908 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3088491950 # number of integer regfile reads -system.cpu.int_regfile_writes 759517885 # number of integer regfile writes +system.cpu.rob.rob_reads 1135058037 # The number of ROB reads +system.cpu.rob.rob_writes 1577598411 # The number of ROB writes +system.cpu.timesIdled 306064 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7117395 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 508955223 # Number of Instructions Simulated +system.cpu.committedOps 573341783 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 508955223 # Number of Instructions Simulated +system.cpu.cpi 0.824401 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.824401 # CPI: Total CPI of All Threads +system.cpu.ipc 1.213002 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.213002 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3101759208 # number of integer regfile reads +system.cpu.int_regfile_writes 762565130 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 999182003 # number of misc regfile reads -system.cpu.misc_regfile_writes 4464054 # number of misc regfile writes -system.cpu.icache.replacements 15774 # number of replacements -system.cpu.icache.tagsinuse 1094.155149 # Cycle average of tags in use -system.cpu.icache.total_refs 114759358 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 17633 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6508.215165 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 1004803161 # number of misc regfile reads +system.cpu.misc_regfile_writes 4464084 # number of misc regfile writes +system.cpu.icache.replacements 15462 # number of replacements +system.cpu.icache.tagsinuse 1099.228607 # Cycle average of tags in use +system.cpu.icache.total_refs 115634831 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 17331 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6672.138422 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1094.155149 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.534255 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.534255 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 114759358 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114759358 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114759358 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114759358 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114759358 # number of overall hits -system.cpu.icache.overall_hits::total 114759358 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19330 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19330 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19330 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19330 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19330 # number of overall misses -system.cpu.icache.overall_misses::total 19330 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 255186500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 255186500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 255186500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 255186500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 255186500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 255186500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114778688 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114778688 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114778688 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114778688 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114778688 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114778688 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000168 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000168 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000168 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000168 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000168 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000168 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13201.577858 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13201.577858 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13201.577858 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13201.577858 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13201.577858 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13201.577858 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1099.228607 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.536733 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.536733 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 115634831 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 115634831 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 115634831 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 115634831 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 115634831 # number of overall hits +system.cpu.icache.overall_hits::total 115634831 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 21629 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 21629 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 21629 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 21629 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 21629 # number of overall misses +system.cpu.icache.overall_misses::total 21629 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 475311000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 475311000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 475311000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 475311000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 475311000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 475311000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 115656460 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 115656460 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 115656460 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 115656460 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 115656460 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 115656460 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000187 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000187 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000187 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000187 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000187 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000187 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21975.634565 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21975.634565 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21975.634565 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21975.634565 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21975.634565 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21975.634565 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 436 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 43.600000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1645 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1645 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1645 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1645 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1645 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1645 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17685 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 17685 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 17685 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 17685 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 17685 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 17685 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170616000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 170616000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170616000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 170616000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170616000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 170616000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000154 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000154 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000154 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000154 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000154 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000154 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9647.497880 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9647.497880 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9647.497880 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 9647.497880 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9647.497880 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 9647.497880 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4227 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4227 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4227 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4227 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4227 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4227 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17402 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 17402 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 17402 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 17402 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 17402 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 17402 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 349731500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 349731500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 349731500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 349731500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 349731500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 349731500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000150 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000150 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000150 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20097.201471 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20097.201471 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20097.201471 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20097.201471 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20097.201471 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20097.201471 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1187152 # number of replacements -system.cpu.dcache.tagsinuse 4054.331998 # Cycle average of tags in use -system.cpu.dcache.total_refs 194883287 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1191248 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 163.595899 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 4629867000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4054.331998 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.989827 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.989827 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 137481946 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 137481946 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 52936216 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 52936216 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233002 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2233002 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 2232026 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 2232026 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 190418162 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 190418162 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 190418162 # number of overall hits -system.cpu.dcache.overall_hits::total 190418162 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1200073 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1200073 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1303090 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1303090 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 42 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 42 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2503163 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2503163 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2503163 # number of overall misses -system.cpu.dcache.overall_misses::total 2503163 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10102287000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10102287000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23193721000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23193721000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 570000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 570000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33296008000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33296008000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33296008000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33296008000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 138682019 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 138682019 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1191468 # number of replacements +system.cpu.dcache.tagsinuse 4055.451159 # Cycle average of tags in use +system.cpu.dcache.total_refs 193136730 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1195564 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 161.544451 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 4668381000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4055.451159 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.990100 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.990100 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 137669566 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 137669566 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51001637 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51001637 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233291 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2233291 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 2232041 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 2232041 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 188671203 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 188671203 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 188671203 # number of overall hits +system.cpu.dcache.overall_hits::total 188671203 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1694127 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1694127 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3237669 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3237669 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 43 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 43 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 4931796 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4931796 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4931796 # number of overall misses +system.cpu.dcache.overall_misses::total 4931796 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25989593000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25989593000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 58741692947 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 58741692947 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 673500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 673500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 84731285947 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 84731285947 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 84731285947 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 84731285947 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 139363693 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 139363693 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233044 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 2233044 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232026 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 2232026 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192921325 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192921325 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192921325 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192921325 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008653 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008653 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024025 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024025 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233334 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 2233334 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232041 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 2232041 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 193602999 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 193602999 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 193602999 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 193602999 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012156 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012156 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059692 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059692 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000019 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000019 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.012975 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.012975 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.012975 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.012975 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8418.060401 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 8418.060401 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17799.016952 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17799.016952 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13571.428571 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13571.428571 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13301.574049 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13301.574049 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13301.574049 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13301.574049 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2849 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 85 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 33.517647 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.025474 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025474 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025474 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025474 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15340.994506 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15340.994506 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18143.205172 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 18143.205172 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15662.790698 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15662.790698 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17180.614516 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17180.614516 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17180.614516 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17180.614516 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15718 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 14943 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1597 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 604 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.842204 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 24.740066 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1101655 # number of writebacks -system.cpu.dcache.writebacks::total 1101655 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 356968 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 356968 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 954898 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 954898 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 42 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 42 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1311866 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1311866 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1311866 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1311866 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 843105 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 843105 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348192 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348192 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1191297 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1191297 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1191297 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1191297 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3721993000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3721993000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3861767000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3861767000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7583760000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7583760000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7583760000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7583760000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006079 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006079 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006420 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006420 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006175 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006175 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006175 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006175 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 4414.625699 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4414.625699 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11090.912485 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 11090.912485 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 6365.969192 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 6365.969192 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 6365.969192 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 6365.969192 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1109851 # number of writebacks +system.cpu.dcache.writebacks::total 1109851 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 846782 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 846782 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2889379 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2889379 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 43 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 43 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3736161 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3736161 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3736161 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3736161 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 847345 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 847345 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348290 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348290 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1195635 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1195635 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1195635 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1195635 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11450908500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11450908500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8277361494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8277361494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19728269994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19728269994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19728269994 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19728269994 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006080 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006080 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006421 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006176 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006176 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006176 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006176 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13513.868023 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13513.868023 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23765.716771 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23765.716771 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16500.244635 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16500.244635 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16500.244635 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16500.244635 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 128756 # number of replacements -system.cpu.l2cache.tagsinuse 26481.749428 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1725200 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 159985 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 10.783511 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 105019230500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 22651.783337 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 310.174210 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 3519.791881 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.691278 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.009466 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.107416 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.808159 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 14188 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 789496 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 803684 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1101655 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1101655 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 45 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 45 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 245235 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 245235 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 14188 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1034731 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1048919 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 14188 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1034731 # number of overall hits -system.cpu.l2cache.overall_hits::total 1048919 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3445 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 53061 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 56506 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 4 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 4 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 103456 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 103456 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3445 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 156517 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 159962 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3445 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 156517 # number of overall misses -system.cpu.l2cache.overall_misses::total 159962 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 138047000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2057062000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2195109000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 4500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 4500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3269316500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3269316500 # 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miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.062976 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.065690 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.081633 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.081633 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.296698 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.296698 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.195372 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.131389 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.132322 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.195372 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.131389 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.132322 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34030.670790 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34160.772558 # average overall miss latency +system.cpu.l2cache.replacements 115394 # number of replacements +system.cpu.l2cache.tagsinuse 26924.508284 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1779847 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 146649 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 12.136782 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 108175523000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 22883.739397 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 368.975633 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 3671.793254 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.698356 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.011260 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.112054 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.821671 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 13925 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 803306 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 817231 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1109851 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1109851 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 63 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 63 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 247487 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 247487 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 13925 # 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number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -816,69 +813,69 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 104385 # number of writebacks -system.cpu.l2cache.writebacks::total 104385 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 31 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36425.685590 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 30287.111204 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30418.955581 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 97680 # number of writebacks +system.cpu.l2cache.writebacks::total 97680 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6093970666 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6243348911 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 149378245 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6093970666 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6243348911 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.195878 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051348 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054245 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.100000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.100000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290368 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290368 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.195878 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121072 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.122140 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.195878 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121072 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.122140 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44025.418509 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45463.268548 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45359.191211 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40656.253498 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40656.253498 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44025.418509 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42100.260907 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42144.354140 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44025.418509 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42100.260907 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42144.354140 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 27346e35d..f9350b670 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.717833 # Number of seconds simulated -sim_ticks 717832876000 # Number of ticks simulated -final_tick 717832876000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.717366 # Number of seconds simulated +sim_ticks 717366012000 # Number of ticks simulated +final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1074460 # Simulator instruction rate (inst/s) -host_op_rate 1210735 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1527332222 # Simulator tick rate (ticks/s) -host_mem_usage 237040 # Number of bytes of host memory used -host_seconds 469.99 # Real time elapsed on the host +host_inst_rate 512177 # Simulator instruction rate (inst/s) +host_op_rate 577137 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 727580493 # Simulator tick rate (ticks/s) +host_mem_usage 234620 # Number of bytes of host memory used +host_seconds 985.96 # Real time elapsed on the host sim_insts 504986853 # Number of instructions simulated sim_ops 569034839 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 178368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9663872 # Number of bytes read from this memory -system.physmem.bytes_read::total 9842240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 178368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 178368 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6574720 # Number of bytes written to this memory -system.physmem.bytes_written::total 6574720 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2787 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 150998 # Number of read requests responded to by this memory -system.physmem.num_reads::total 153785 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 102730 # Number of write requests responded to by this memory -system.physmem.num_writes::total 102730 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 248481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13462565 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13711047 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 248481 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 248481 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 9159124 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 9159124 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 9159124 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 248481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13462565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 22870170 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8952256 # Number of bytes read from this memory +system.physmem.bytes_read::total 9129536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 177280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 177280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6140992 # Number of bytes written to this memory +system.physmem.bytes_written::total 6140992 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2770 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 139879 # Number of read requests responded to by this memory +system.physmem.num_reads::total 142649 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory +system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 247126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12479342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12726469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 247126 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 247126 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8560472 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8560472 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8560472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 247126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12479342 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21286941 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 1435665752 # number of cpu cycles simulated +system.cpu.numCycles 1434732024 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 504986853 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 182890034 # nu system.cpu.num_load_insts 126029555 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1435665752 # Number of busy cycles +system.cpu.num_busy_cycles 1434732024 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 9788 # number of replacements -system.cpu.icache.tagsinuse 982.776891 # Cycle average of tags in use +system.cpu.icache.tagsinuse 982.663229 # Cycle average of tags in use system.cpu.icache.total_refs 516599855 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 44839.845066 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 982.776891 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.479872 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.479872 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.479816 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 266834000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 266834000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 266834000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 266834000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 266834000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 266834000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 266195000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 266195000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 266195000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 266195000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 266195000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 266195000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23160.663137 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23160.663137 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23160.663137 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23160.663137 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23160.663137 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23160.663137 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23105.199201 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23105.199201 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23105.199201 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23105.199201 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23105.199201 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23105.199201 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521 system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243792000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 243792000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243792000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 243792000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243792000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 243792000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243153000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 243153000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243153000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 243153000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243153000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 243153000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21160.663137 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21160.663137 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21160.663137 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21160.663137 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21160.663137 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21160.663137 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21105.199201 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21105.199201 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1134822 # number of replacements -system.cpu.dcache.tagsinuse 4065.317414 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4065.297446 # Cycle average of tags in use system.cpu.dcache.total_refs 179817786 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 157.884752 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4065.317414 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.992509 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.992504 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 1138918 # n system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12178377000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12178377000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8970025000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8970025000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 21148402000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 21148402000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 21148402000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 21148402000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11817433000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11817433000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8864744000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8864744000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20682177000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20682177000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20682177000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20682177000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15560.279202 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15560.279202 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25178.310784 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25178.310784 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18568.853947 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18568.853947 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18568.853947 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18568.853947 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.102034 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.102034 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24882.793465 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24882.793465 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18159.496118 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18159.496118 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1061444 # number of writebacks -system.cpu.dcache.writebacks::total 1061444 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks +system.cpu.dcache.writebacks::total 1064905 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10613061000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10613061000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257505000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257505000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18870566000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18870566000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18870566000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18870566000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10252117000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10252117000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8152224000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8152224000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18404341000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18404341000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18404341000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18404341000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses @@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13560.279202 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13560.279202 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23178.310784 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23178.310784 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16568.853947 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16568.853947 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16568.853947 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16568.853947 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13099.102034 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13099.102034 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22882.793465 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22882.793465 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 122482 # number of replacements -system.cpu.l2cache.tagsinuse 26931.505779 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1623186 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 153644 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 10.564591 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 343812481000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 23220.335885 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 246.652044 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 3464.517849 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.708628 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.007527 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.105729 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.821884 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 8734 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 734961 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 743695 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1061444 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1061444 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 252959 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 252959 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.713558 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.008785 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.109054 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.831396 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 8751 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 743573 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 752324 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1064905 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1064905 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 255466 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 255466 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 8751 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 999039 # 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number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses @@ -346,28 +346,28 @@ system.cpu.l2cache.demand_accesses::total 1150439 # n system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.241906 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.060942 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.063568 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.289960 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.289960 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.241906 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52009.472473 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52009.863371 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52029.602888 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52009.472473 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52009.863371 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -376,52 +376,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5707367000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110882000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5596485000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5707367000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.049939 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.052702 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282923 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282923 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123995 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123995 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40029.602888 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.491109 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.233783 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.158740 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.158740 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40029.602888 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40029.602888 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 72d60096c..0b91be0ea 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.425005 # Number of seconds simulated -sim_ticks 425004962000 # Number of ticks simulated -final_tick 425004962000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.447151 # Number of seconds simulated +sim_ticks 447151291000 # Number of ticks simulated +final_tick 447151291000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69307 # Simulator instruction rate (inst/s) -host_op_rate 128157 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35623080 # Simulator tick rate (ticks/s) -host_mem_usage 342928 # Number of bytes of host memory used -host_seconds 11930.61 # Real time elapsed on the host +host_inst_rate 99582 # Simulator instruction rate (inst/s) +host_op_rate 184139 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53851139 # Simulator tick rate (ticks/s) +host_mem_usage 337048 # Number of bytes of host memory used +host_seconds 8303.47 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988699 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 225344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 27603520 # Number of bytes read from this memory -system.physmem.bytes_read::total 27828864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 225344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 225344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 20794944 # Number of bytes written to this memory -system.physmem.bytes_written::total 20794944 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3521 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 431305 # Number of read requests responded to by this memory -system.physmem.num_reads::total 434826 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 324921 # Number of write requests responded to by this memory -system.physmem.num_writes::total 324921 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 530215 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 64948701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 65478916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 530215 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 530215 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 48928709 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 48928709 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 48928709 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 530215 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 64948701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 114407624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 434829 # Total number of read requests seen -system.physmem.writeReqs 324921 # Total number of write requests seen -system.physmem.cpureqs 946181 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 27828864 # Total number of bytes read from memory -system.physmem.bytesWritten 20794944 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 27828864 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 20794944 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 530 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 186431 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28468 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 25473 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28312 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28794 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28169 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27724 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27247 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 26795 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 25192 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 26852 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 26027 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 26097 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27939 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27190 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27326 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 26694 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 21362 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 19642 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 20883 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 21132 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 20800 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 20650 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 19810 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 19986 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 19177 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 20342 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 19625 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 19675 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 20834 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 20387 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 20379 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 20237 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 207040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24466624 # Number of bytes read from this memory +system.physmem.bytes_read::total 24673664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 207040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 207040 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18786368 # Number of bytes written to this memory +system.physmem.bytes_written::total 18786368 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3235 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382291 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385526 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293537 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293537 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 463020 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 54716657 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 55179677 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 463020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 463020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 42013449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 42013449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 42013449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 463020 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 54716657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 97193127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385528 # Total number of read requests seen +system.physmem.writeReqs 293537 # Total number of write requests seen +system.physmem.cpureqs 863596 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 24673664 # Total number of bytes read from memory +system.physmem.bytesWritten 18786368 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 24673664 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 18786368 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 164 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 184531 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 24996 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 23035 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 24534 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 25301 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 24892 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24563 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 23920 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24683 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 22800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 23577 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 23208 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 23396 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 24161 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 24133 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 24010 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 24155 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 19354 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 17947 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 18690 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 18990 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 19041 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 18723 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 18099 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 18501 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 17450 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 17927 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 17723 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 17609 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 18440 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 18279 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 18321 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 18443 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 425004950500 # Total gap between requests +system.physmem.totGap 447151273000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 434829 # Categorize read packet sizes +system.physmem.readPktSize::6 385528 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 324921 # categorize write packet sizes +system.physmem.writePktSize::6 293537 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,17 +102,17 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 186431 # categorize neither packet sizes +system.physmem.neitherpktsize::6 184531 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 423801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 992 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 380682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4205 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 406 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see @@ -138,31 +138,31 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 14107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 14125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 12758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 12763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 12763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 12763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 12763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 12763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 12763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 12763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 12763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 12763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,266 +171,266 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2315570683 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11699376683 # Sum of mem lat for all requests -system.physmem.totBusLat 1737188000 # Total cycles spent in databus access -system.physmem.totBankLat 7646618000 # Total cycles spent in bank access -system.physmem.avgQLat 5331.74 # Average queueing delay per request -system.physmem.avgBankLat 17606.81 # Average bank access latency per request -system.physmem.avgBusLat 3999.98 # Average bus latency per request -system.physmem.avgMemAccLat 26938.53 # Average memory access latency -system.physmem.avgRdBW 65.48 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 48.93 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 65.48 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 48.93 # Average consumed write bandwidth in MB/s +system.physmem.totQLat 3526127005 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11592689005 # Sum of mem lat for all requests +system.physmem.totBusLat 1541456000 # Total cycles spent in databus access +system.physmem.totBankLat 6525106000 # Total cycles spent in bank access +system.physmem.avgQLat 9150.12 # Average queueing delay per request +system.physmem.avgBankLat 16932.32 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 30082.44 # Average memory access latency +system.physmem.avgRdBW 55.18 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 42.01 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 55.18 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 42.01 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.72 # Data bus utilization in percentage +system.physmem.busUtil 0.61 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 10.61 # Average write queue length over time -system.physmem.readRowHits 372606 # Number of row buffer hits during reads -system.physmem.writeRowHits 225570 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.79 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 69.42 # Row buffer hit rate for writes -system.physmem.avgGap 559401.05 # Average gap between requests +system.physmem.avgWrQLen 8.93 # Average write queue length over time +system.physmem.readRowHits 340552 # Number of row buffer hits during reads +system.physmem.writeRowHits 151633 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 51.66 # Row buffer hit rate for writes +system.physmem.avgGap 658480.81 # Average gap between requests system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 850009925 # number of cpu cycles simulated +system.cpu.numCycles 894302583 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 221647941 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 221647941 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 14406573 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 156865582 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 152803842 # Number of BTB hits +system.cpu.BPredUnit.lookups 221834419 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 221834419 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 14438837 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 157195941 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 152967077 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 187050304 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1232910947 # Number of instructions fetch has processed -system.cpu.fetch.Branches 221647941 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 152803842 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 383000973 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 91957921 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 194367409 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 27532 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 281947 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 179514226 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4153507 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 842043655 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.718190 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.421187 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 187305514 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1233712111 # Number of instructions fetch has processed +system.cpu.fetch.Branches 221834419 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 152967077 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 383213555 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 92482547 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 231997744 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 31125 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 302541 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 64 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 179659779 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4113909 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 880638441 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.600745 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.391861 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 463448237 55.04% 55.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25479263 3.03% 58.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 28153869 3.34% 61.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 29472837 3.50% 64.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 19000698 2.26% 67.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 25093035 2.98% 70.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31632323 3.76% 73.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30740236 3.65% 77.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 189023157 22.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 501847528 56.99% 56.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25496575 2.90% 59.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28121767 3.19% 63.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 29451767 3.34% 66.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 18987914 2.16% 68.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 25123088 2.85% 71.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31720196 3.60% 75.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30784274 3.50% 78.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 189105332 21.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 842043655 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.260759 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.450467 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 241549987 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 153599929 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 326439638 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 43138611 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 77315490 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2235464595 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 77315490 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 274523548 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 31537330 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13263 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 335098725 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 123555299 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2183717460 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4657 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17805168 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 90736739 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 132 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2283770499 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5522648237 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5522400911 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 247326 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 880638441 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.248053 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.379524 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 244537844 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 188536263 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 324191261 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 45585175 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 77787898 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2236907904 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 77787898 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 278585274 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 54813178 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15041 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 333395312 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 136041738 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2184748951 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 34526 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 20261515 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 101530735 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 116 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2284488026 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5524710294 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5524485031 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 225263 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040851 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 669729648 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1332 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1314 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 306041131 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 528315963 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 210729777 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 206411035 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 60542315 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2088035741 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 33633 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1834967448 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 958048 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 553034175 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 917867353 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 33080 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 842043655 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.179183 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.902262 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 670447175 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1310 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1291 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 328673064 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 528947917 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 211077156 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 202192665 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 58804191 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2090539379 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34704 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1836706736 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 960329 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 555260187 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 919296135 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 34151 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 880638441 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.085654 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.886104 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 224002778 26.60% 26.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 138530201 16.45% 43.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 132512875 15.74% 58.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 132981805 15.79% 74.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 103723627 12.32% 86.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60327569 7.16% 94.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 35793527 4.25% 98.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12197617 1.45% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1973656 0.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 249855133 28.37% 28.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 147643393 16.77% 45.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 139523467 15.84% 60.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 137737388 15.64% 76.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 97163823 11.03% 87.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 59916022 6.80% 94.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34917189 3.96% 98.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11990499 1.36% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1891527 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 842043655 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 880638441 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5036793 29.93% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9138103 54.31% 84.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2651049 15.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5040061 32.96% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7632140 49.91% 82.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2619273 17.13% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2710381 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1209906674 65.94% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 444393956 24.22% 90.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 177956437 9.70% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2704214 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1211533027 65.96% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 444457178 24.20% 90.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 178012317 9.69% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1834967448 # Type of FU issued -system.cpu.iq.rate 2.158760 # Inst issue rate -system.cpu.iq.fu_busy_cnt 16825945 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009170 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4529719072 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2641264974 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1791788720 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 43472 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82738 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10238 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1849062833 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 20179 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 168239222 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1836706736 # Type of FU issued +system.cpu.iq.rate 2.053787 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15291474 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008325 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4570263035 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2646020420 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1794037475 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 40681 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 76210 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 9614 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1849275039 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 18957 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 170130474 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 144213807 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 600713 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 256350 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 61570124 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 144845761 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 503638 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 274982 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 61917680 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 8445 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10585 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 592 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 77315490 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4278866 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 415483 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2088069374 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2542491 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 528315963 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 210730309 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5324 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 253060 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 9562 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 256350 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10027874 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4925644 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 14953518 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1804855171 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 436117290 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30112277 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 77787898 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 17508647 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2908748 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2090574083 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2437552 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 528947917 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 211077865 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5687 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1841603 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73588 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 274982 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10048689 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4929582 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 14978271 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1806703840 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 436137965 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30002896 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 608678492 # number of memory reference insts executed -system.cpu.iew.exec_branches 171062939 # Number of branches executed -system.cpu.iew.exec_stores 172561202 # Number of stores executed -system.cpu.iew.exec_rate 2.123334 # Inst execution rate -system.cpu.iew.wb_sent 1799249201 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1791798958 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1362830081 # num instructions producing a value -system.cpu.iew.wb_consumers 2000862713 # num instructions consuming a value +system.cpu.iew.exec_refs 608784008 # number of memory reference insts executed +system.cpu.iew.exec_branches 171260555 # Number of branches executed +system.cpu.iew.exec_stores 172646043 # Number of stores executed +system.cpu.iew.exec_rate 2.020238 # Inst execution rate +system.cpu.iew.wb_sent 1801373489 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1794047089 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1362133405 # num instructions producing a value +system.cpu.iew.wb_consumers 1992639116 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.107974 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.681121 # average fanout of values written-back +system.cpu.iew.wb_rate 2.006085 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.683583 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 559102384 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 561620004 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14433850 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 764728165 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.999389 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.465219 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14469462 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 802850543 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.904450 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.430311 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 272413651 35.62% 35.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 194503439 25.43% 61.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 61238057 8.01% 69.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 90227004 11.80% 80.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 27738655 3.63% 84.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 29159140 3.81% 88.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10333164 1.35% 89.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10341610 1.35% 91.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 68773445 8.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 304835163 37.97% 37.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 198905096 24.77% 62.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 63436109 7.90% 70.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92154984 11.48% 82.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 26044111 3.24% 85.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 29384573 3.66% 89.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9423573 1.17% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10229786 1.27% 91.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 68437148 8.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 764728165 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 802850543 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988699 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -441,311 +441,311 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317557 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 68773445 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 68437148 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2784045803 # The number of ROB reads -system.cpu.rob.rob_writes 4253715555 # The number of ROB writes -system.cpu.timesIdled 179238 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7966270 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2825022098 # The number of ROB reads +system.cpu.rob.rob_writes 4259228710 # The number of ROB writes +system.cpu.timesIdled 301112 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13664142 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988699 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.027976 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.027976 # CPI: Total CPI of All Threads -system.cpu.ipc 0.972785 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.972785 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3390214587 # number of integer regfile reads -system.cpu.int_regfile_writes 1871573439 # number of integer regfile writes -system.cpu.fp_regfile_reads 10236 # number of floating regfile reads +system.cpu.cpi 1.081542 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.081542 # CPI: Total CPI of All Threads +system.cpu.ipc 0.924606 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.924606 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3392416402 # number of integer regfile reads +system.cpu.int_regfile_writes 1873878910 # number of integer regfile writes +system.cpu.fp_regfile_reads 9612 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.misc_regfile_reads 993130827 # number of misc regfile reads -system.cpu.icache.replacements 5731 # number of replacements -system.cpu.icache.tagsinuse 1034.037523 # Cycle average of tags in use -system.cpu.icache.total_refs 179301494 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7346 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 24408.044378 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 993805261 # number of misc regfile reads +system.cpu.icache.replacements 5664 # number of replacements +system.cpu.icache.tagsinuse 1040.414195 # Cycle average of tags in use +system.cpu.icache.total_refs 179444520 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7258 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 24723.686966 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1034.037523 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.504901 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.504901 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 179317731 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 179317731 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 179317731 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 179317731 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 179317731 # number of overall hits -system.cpu.icache.overall_hits::total 179317731 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 196495 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 196495 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 196495 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 196495 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 196495 # number of overall misses -system.cpu.icache.overall_misses::total 196495 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 965132000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 965132000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 965132000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 965132000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 965132000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 965132000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 179514226 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 179514226 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 179514226 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 179514226 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 179514226 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 179514226 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001095 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001095 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001095 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001095 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001095 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001095 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 4911.738212 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 4911.738212 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 4911.738212 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 4911.738212 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 4911.738212 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 4911.738212 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1040.414195 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.508015 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.508015 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 179464097 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 179464097 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 179464097 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 179464097 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 179464097 # number of overall hits +system.cpu.icache.overall_hits::total 179464097 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 195682 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 195682 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 195682 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 195682 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 195682 # number of overall misses +system.cpu.icache.overall_misses::total 195682 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1231899498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1231899498 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1231899498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1231899498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1231899498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1231899498 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 179659779 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 179659779 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 179659779 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 179659779 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 179659779 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 179659779 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001089 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001089 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001089 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001089 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001089 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001089 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6295.415511 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6295.415511 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6295.415511 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6295.415511 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6295.415511 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6295.415511 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 959 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 56.411765 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1287 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1287 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1287 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1287 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1287 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1287 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 195208 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 195208 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 195208 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 195208 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 195208 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 195208 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 532960000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 532960000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 532960000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 532960000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 532960000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 532960000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001087 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001087 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001087 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001087 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001087 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 2730.215975 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 2730.215975 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 2730.215975 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 2730.215975 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 2730.215975 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 2730.215975 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2352 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2352 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2352 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 781617498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 781617498 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 781617498 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001076 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001076 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001076 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001076 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001076 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001076 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4042.918833 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4042.918833 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4042.918833 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4042.918833 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4042.918833 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4042.918833 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2528528 # number of replacements -system.cpu.dcache.tagsinuse 4087.799057 # Cycle average of tags in use -system.cpu.dcache.total_refs 412295597 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2532624 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 162.793844 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1757376000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.799057 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997998 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997998 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 263850158 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 263850158 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148199214 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148199214 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 412049372 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 412049372 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 412049372 # number of overall hits -system.cpu.dcache.overall_hits::total 412049372 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2450927 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2450927 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 960987 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 960987 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3411914 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3411914 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3411914 # number of overall misses -system.cpu.dcache.overall_misses::total 3411914 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 21876345500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 21876345500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10305852000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10305852000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32182197500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32182197500 # 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Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998042 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 261613799 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 261613799 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148186041 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148186041 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 409799840 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 409799840 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 409799840 # number of overall hits +system.cpu.dcache.overall_hits::total 409799840 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2816252 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2816252 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 974160 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 974160 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3790412 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3790412 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3790412 # number of overall misses +system.cpu.dcache.overall_misses::total 3790412 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 49180630000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 49180630000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23742046000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23742046000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 72922676000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 72922676000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 72922676000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 72922676000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264430051 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264430051 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 415461286 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 415461286 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 415461286 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 415461286 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009204 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009204 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006443 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006443 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008212 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008212 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008212 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008212 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8925.743402 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 8925.743402 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10724.236644 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10724.236644 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9432.300316 # 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miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006531 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009165 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009165 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009165 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009165 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17463.149605 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17463.149605 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24371.813665 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24371.813665 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19238.720224 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19238.720224 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19238.720224 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19238.720224 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6306 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 671 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.397914 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2303917 # number of writebacks -system.cpu.dcache.writebacks::total 2303917 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 688869 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 688869 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2605 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2605 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 691474 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 691474 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 691474 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 691474 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762058 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762058 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 958382 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 958382 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2720440 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2720440 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2720440 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2720440 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10938829000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10938829000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8350531500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8350531500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19289360500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19289360500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19289360500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19289360500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006617 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006617 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006425 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006425 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006548 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006548 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006548 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006548 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 6207.984641 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 6207.984641 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8713.155610 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8713.155610 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7090.529657 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7090.529657 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7090.529657 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7090.529657 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2331455 # 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average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15265.606437 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22592.272634 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22592.272634 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17844.303202 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17844.303202 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17844.303202 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17844.303202 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 408648 # number of replacements -system.cpu.l2cache.tagsinuse 29292.470597 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3610957 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 440981 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 8.188464 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 210382320000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21099.010589 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 149.285898 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8044.174110 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.643891 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.004556 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.245489 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.893935 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3792 # 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number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 771582 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 771582 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 7214 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2533891 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2541105 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 7214 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2533891 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2541105 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.448572 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099680 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.101102 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991807 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991807 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.267847 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.267847 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.448572 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150888 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151733 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.448572 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150888 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151733 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 58036.155748 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52603.676029 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52701.938799 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39.473470 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39.473470 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53163.786012 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53163.786012 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 58036.155748 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52906.437469 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52949.490122 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 58036.155748 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52906.437469 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52949.490122 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -754,60 +754,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 324921 # number of writebacks -system.cpu.l2cache.writebacks::total 324921 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3522 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222082 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 225604 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 186394 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 186394 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209262 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 209262 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3522 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 431344 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 434866 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3522 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 431344 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 434866 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 130409329 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6743844087 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6874253416 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 191417941 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 191417941 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5332990356 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5332990356 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 130409329 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12076834443 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12207243772 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 130409329 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12076834443 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12207243772 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.481542 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126115 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127585 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992439 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992439 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.271180 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271180 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.481542 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170315 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.171211 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.481542 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170315 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.171211 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37027.066723 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30366.459628 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 30470.441198 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 1026.953341 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 1026.953341 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 25484.752874 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 25484.752874 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37027.066723 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 27998.150995 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28071.276605 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37027.066723 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 27998.150995 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28071.276605 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 293537 # number of writebacks +system.cpu.l2cache.writebacks::total 293537 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3236 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175667 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 178903 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 184491 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 184491 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206666 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206666 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3236 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 382333 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 385569 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3236 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 382333 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 385569 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 146938362 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6979134954 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7126073316 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1849956331 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1849956331 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8352740653 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8352740653 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 146938362 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15331875607 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15478813969 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 146938362 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15331875607 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15478813969 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.448572 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099680 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101102 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991807 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991807 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.267847 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.267847 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.448572 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150888 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151733 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.448572 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150888 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151733 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45407.404821 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39729.345603 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39832.050418 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10027.352722 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10027.352722 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40416.617407 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40416.617407 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 45407.404821 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40100.843001 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40145.379865 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45407.404821 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40100.843001 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40145.379865 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 3dab46390..fbbc37948 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.649901 # Number of seconds simulated -sim_ticks 1649900881000 # Number of ticks simulated -final_tick 1649900881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.647873 # Number of seconds simulated +sim_ticks 1647872847000 # Number of ticks simulated +final_tick 1647872847000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 669860 # Simulator instruction rate (inst/s) -host_op_rate 1238647 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1336598464 # Simulator tick rate (ticks/s) -host_mem_usage 232964 # Number of bytes of host memory used -host_seconds 1234.40 # Real time elapsed on the host +host_inst_rate 897428 # Simulator instruction rate (inst/s) +host_op_rate 1659445 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1788472844 # Simulator tick rate (ticks/s) +host_mem_usage 230968 # Number of bytes of host memory used +host_seconds 921.39 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988700 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 123584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 27359872 # Number of bytes read from this memory -system.physmem.bytes_read::total 27483456 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 123584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 123584 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 20708480 # Number of bytes written to this memory -system.physmem.bytes_written::total 20708480 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1931 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 427498 # Number of read requests responded to by this memory -system.physmem.num_reads::total 429429 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 323570 # Number of write requests responded to by this memory -system.physmem.num_writes::total 323570 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 74904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 16582737 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16657641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 74904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 74904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 12551348 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 12551348 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 12551348 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 74904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 16582737 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29208989 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24272448 # Number of bytes read from this memory +system.physmem.bytes_read::total 24393152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 120704 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 120704 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18706304 # Number of bytes written to this memory +system.physmem.bytes_written::total 18706304 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1886 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 379257 # Number of read requests responded to by this memory +system.physmem.num_reads::total 381143 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292286 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292286 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 73248 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14729564 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14802812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 73248 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 73248 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 11351788 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11351788 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11351788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 26154601 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3299801762 # number of cpu cycles simulated +system.cpu.numCycles 3295745694 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877110 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 533262341 # nu system.cpu.num_load_insts 384102156 # Number of load instructions system.cpu.num_store_insts 149160185 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3299801762 # Number of busy cycles +system.cpu.num_busy_cycles 3295745694 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1253 # number of replacements -system.cpu.icache.tagsinuse 881.283724 # Cycle average of tags in use +system.cpu.icache.tagsinuse 881.356492 # Cycle average of tags in use system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 881.283724 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.430314 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.430314 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 881.356492 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.430350 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 117690500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 117690500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 117690500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 117690500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 117690500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 117690500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 115806000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 115806000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 115806000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 115806000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 115806000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 115806000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1068347066 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1068347066 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1068347066 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41823.205402 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41823.205402 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41823.205402 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41823.205402 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41823.205402 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41823.205402 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41153.518124 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41153.518124 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41153.518124 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41153.518124 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814 system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112062500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 112062500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112062500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 112062500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112062500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 112062500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 110178000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 110178000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 110178000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 110178000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 110178000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 110178000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39823.205402 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39823.205402 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39823.205402 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39823.205402 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39823.205402 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39823.205402 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39153.518124 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39153.518124 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2514362 # number of replacements -system.cpu.dcache.tagsinuse 4086.427569 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4086.415788 # Cycle average of tags in use system.cpu.dcache.total_refs 530743928 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 8211722000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.427569 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997663 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997663 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4086.415788 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997660 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 2518458 # n system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses system.cpu.dcache.overall_misses::total 2518458 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31594062000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31594062000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19100972000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19100972000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 50695034000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 50695034000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 50695034000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 50695034000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704283000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29704283000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964601500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18964601500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 48668884500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 48668884500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 48668884500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18289.803139 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18289.803139 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24146.535465 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24146.535465 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20129.394256 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20129.394256 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20129.394256 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20129.394256 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.810037 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.810037 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.142399 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.142399 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19324.874387 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19324.874387 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2297113 # number of writebacks -system.cpu.dcache.writebacks::total 2297113 # number of writebacks +system.cpu.dcache.writebacks::writebacks 2323523 # number of writebacks +system.cpu.dcache.writebacks::total 2323523 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28139234000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 28139234000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17518884000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17518884000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45658118000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45658118000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45658118000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45658118000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26249455000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26249455000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17382513500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17382513500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43631968500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 43631968500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43631968500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 43631968500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses @@ -226,68 +226,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16289.803139 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16289.803139 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22146.535465 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22146.535465 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18129.394256 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18129.394256 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18129.394256 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18129.394256 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15195.810037 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15195.810037 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21974.142399 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21974.142399 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 403150 # number of replacements -system.cpu.l2cache.tagsinuse 29110.547277 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3572765 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 435501 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 8.203804 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 772497646000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21034.967888 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 79.712550 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 7995.866840 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.641936 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.002433 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.244014 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.888383 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 883 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1509854 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1510737 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2297113 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2297113 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 581106 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 581106 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 883 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2090960 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2091843 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 883 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2090960 # number of overall hits -system.cpu.l2cache.overall_hits::total 2091843 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1931 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 217560 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 219491 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 209938 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 209938 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1931 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 427498 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 429429 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1931 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 427498 # number of overall misses -system.cpu.l2cache.overall_misses::total 429429 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100418500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11313280000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 11413698500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10916780000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10916780000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 100418500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22230060000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22330478500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 100418500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22230060000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22330478500 # number of overall miss cycles +system.cpu.l2cache.replacements 348459 # number of replacements +system.cpu.l2cache.tagsinuse 29286.402699 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3655011 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 380814 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 9.597890 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 755936429000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 21041.299363 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 139.758520 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 8105.344817 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.893750 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 928 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1554848 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1555776 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2323523 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2323523 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 584353 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 584353 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 928 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2139201 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2140129 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 928 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2139201 # number of overall hits +system.cpu.l2cache.overall_hits::total 2140129 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1886 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 172566 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 174452 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 206691 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206691 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1886 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 379257 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 381143 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1886 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 379257 # number of overall misses +system.cpu.l2cache.overall_misses::total 381143 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 98084000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8973561000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 9071645000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10747939500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10747939500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 98084000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 19721500500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 19819584500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 98084000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 19721500500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 19819584500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2297113 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2297113 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2323523 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2323523 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 791044 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses @@ -296,28 +296,28 @@ system.cpu.l2cache.demand_accesses::total 2521272 # n system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.686212 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.125945 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.126857 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.265394 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.265394 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.686212 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.169746 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.170322 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.686212 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.169746 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.170322 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52003.366132 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.735429 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.758573 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.019053 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.019053 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52003.366132 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.383628 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.397039 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52003.366132 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.383628 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.397039 # average overall miss latency +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.670220 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099898 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.100826 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.261289 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.261289 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.670220 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150591 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151171 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.670220 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150591 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151171 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52006.362672 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.747540 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.808245 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.036286 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.036286 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.389618 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.389618 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -326,52 +326,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 323570 # number of writebacks -system.cpu.l2cache.writebacks::total 323570 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1931 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 217560 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 219491 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209938 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 209938 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1931 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 427498 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 429429 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1931 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 427498 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 429429 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 77246000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8702551000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8779797000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8397520000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8397520000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 77246000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17100071000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17177317000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 77246000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17100071000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17177317000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.125945 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.126857 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265394 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265394 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.169746 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.170322 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.169746 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.170322 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40003.107198 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.694061 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.715291 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40003.107198 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.353218 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.365602 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.107198 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.353218 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.365602 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 292286 # number of writebacks +system.cpu.l2cache.writebacks::total 292286 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1886 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 172566 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 174452 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206691 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206691 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1886 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 379257 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 381143 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1886 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 379257 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 381143 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 75452000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6902758000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6978210000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8267645000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8267645000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 75452000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15170403000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15245855000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 75452000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15170403000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15245855000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099898 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.100826 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.261289 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.261289 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151171 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151171 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.362672 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.683796 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.745191 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.024191 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.024191 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index 1c69e7033..a158074c5 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.141149 # Number of seconds simulated -sim_ticks 141148809500 # Number of ticks simulated -final_tick 141148809500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.141089 # Number of seconds simulated +sim_ticks 141089296500 # Number of ticks simulated +final_tick 141089296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76319 # Simulator instruction rate (inst/s) -host_op_rate 76319 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27020959 # Simulator tick rate (ticks/s) -host_mem_usage 222760 # Number of bytes of host memory used -host_seconds 5223.68 # Real time elapsed on the host +host_inst_rate 83115 # Simulator instruction rate (inst/s) +host_op_rate 83115 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29414893 # Simulator tick rate (ticks/s) +host_mem_usage 223012 # Number of bytes of host memory used +host_seconds 4796.53 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory -system.physmem.bytes_read::total 468608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 214592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 214592 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3353 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 468992 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 214976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 214976 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7322 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1520325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1799633 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3319957 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1520325 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1520325 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1520325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1799633 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3319957 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7322 # Total number of read requests seen +system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1523688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1800392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3324079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1523688 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1523688 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1523688 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1800392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3324079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7328 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7322 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 468608 # Total number of bytes read from memory +system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 468992 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 468608 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 468992 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed @@ -41,17 +41,17 @@ system.physmem.perBankRdReqs::1 464 # Tr system.physmem.perBankRdReqs::2 518 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 382 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 397 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 398 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 457 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 443 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 405 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 444 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 407 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 457 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 588 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 397 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 529 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 418 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 395 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 487 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 396 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 488 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 141148757500 # Total gap between requests +system.physmem.totGap 141089244500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7322 # Categorize read packet sizes +system.physmem.readPktSize::6 7328 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 5336 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1506 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 331 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4661 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 520 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,14 +164,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 28738807 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 171664807 # Sum of mem lat for all requests -system.physmem.totBusLat 29288000 # Total cycles spent in databus access -system.physmem.totBankLat 113638000 # Total cycles spent in bank access -system.physmem.avgQLat 3924.99 # Average queueing delay per request -system.physmem.avgBankLat 15520.08 # Average bank access latency per request +system.physmem.totQLat 39617295 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 175175295 # Sum of mem lat for all requests +system.physmem.totBusLat 29312000 # Total cycles spent in databus access +system.physmem.totBankLat 106246000 # Total cycles spent in bank access +system.physmem.avgQLat 5406.29 # Average queueing delay per request +system.physmem.avgBankLat 14498.64 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23445.07 # Average memory access latency +system.physmem.avgMemAccLat 23904.93 # Average memory access latency system.physmem.avgRdBW 3.32 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 3.32 # Average consumed read bandwidth in MB/s @@ -180,31 +180,31 @@ system.physmem.peakBW 16000.00 # Th system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6437 # Number of row buffer hits during reads +system.physmem.readRowHits 6442 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19277350.11 # Average gap between requests +system.physmem.avgGap 19253444.94 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94755019 # DTB read hits +system.cpu.dtb.read_hits 94754611 # DTB read hits system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94755040 # DTB read accesses -system.cpu.dtb.write_hits 73522092 # DTB write hits +system.cpu.dtb.read_accesses 94754632 # DTB read accesses +system.cpu.dtb.write_hits 73521102 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73522127 # DTB write accesses -system.cpu.dtb.data_hits 168277111 # DTB hits +system.cpu.dtb.write_accesses 73521137 # DTB write accesses +system.cpu.dtb.data_hits 168275713 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168277167 # DTB accesses -system.cpu.itb.fetch_hits 49111843 # ITB hits -system.cpu.itb.fetch_misses 88782 # ITB misses +system.cpu.dtb.data_accesses 168275769 # DTB accesses +system.cpu.itb.fetch_hits 49091192 # ITB hits +system.cpu.itb.fetch_misses 88817 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 49200625 # ITB accesses +system.cpu.itb.fetch_accesses 49180009 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,42 +218,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 282297620 # number of cpu cycles simulated +system.cpu.numCycles 282178594 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 53870359 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 30921660 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 16037209 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 33426943 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 15653988 # Number of BTB hits +system.cpu.branch_predictor.lookups 53863325 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 30909619 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 16029157 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 33388385 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 15622160 # Number of BTB hits system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 18 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 46.830451 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 29683847 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 24186512 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280818433 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 19 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 46.789205 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 29654286 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 24209039 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 280812298 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 440154292 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119907695 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 440148157 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 119908557 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 220104176 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100457659 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 168700458 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 14475221 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 1561329 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 16036550 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 28551001 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 35.966429 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 205750873 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 2124330 # Number of Multipy Operations Executed +system.cpu.regfile_manager.floatRegFileAccesses 220105038 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100451904 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 168699560 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 14461353 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 1567145 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 16028498 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 28559053 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 35.948370 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 205751378 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 2124332 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 281928004 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 281883987 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 8014 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13423125 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 268874495 # Number of cycles cpu stages are processed. -system.cpu.activity 95.245045 # Percentage of cycles cpu is active +system.cpu.timesIdled 7632 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13336617 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 268841977 # Number of cycles cpu stages are processed. +system.cpu.activity 95.273696 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -265,144 +265,144 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.708108 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.707810 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.708108 # CPI: Total CPI of All Threads -system.cpu.ipc 1.412214 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.707810 # CPI: Total CPI of All Threads +system.cpu.ipc 1.412809 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.412214 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 78483642 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 203813978 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.198263 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 108810922 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 173486698 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.455246 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 104588213 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177709407 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.951082 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 183516209 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98781411 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 34.991939 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 92605054 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189692566 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.195949 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 1974 # number of replacements -system.cpu.icache.tagsinuse 1830.000422 # Cycle average of tags in use -system.cpu.icache.total_refs 49107453 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12588.426814 # Average number of references to valid blocks. +system.cpu.ipc_total 1.412809 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 78396963 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 203781631 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 72.217254 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 108683745 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 173494849 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.484058 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 104474173 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 177704421 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.975869 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 183396585 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98782009 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 35.006911 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 92487828 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189690766 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.223656 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 1982 # number of replacements +system.cpu.icache.tagsinuse 1831.235862 # Cycle average of tags in use +system.cpu.icache.total_refs 49086683 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 3910 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12554.138875 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1830.000422 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.893555 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.893555 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 49107453 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 49107453 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 49107453 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 49107453 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 49107453 # number of overall hits -system.cpu.icache.overall_hits::total 49107453 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4389 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4389 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4389 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4389 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4389 # number of overall misses -system.cpu.icache.overall_misses::total 4389 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 191814500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 191814500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 191814500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 191814500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 191814500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 191814500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 49111842 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 49111842 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 49111842 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 49111842 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 49111842 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 49111842 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000089 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000089 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000089 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000089 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000089 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43703.463203 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43703.463203 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43703.463203 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43703.463203 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43703.463203 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43703.463203 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 66 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 66 # average number of cycles each access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1831.235862 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.894158 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.894158 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 49086683 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 49086683 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 49086683 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 49086683 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 49086683 # number of overall hits +system.cpu.icache.overall_hits::total 49086683 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4508 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4508 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4508 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4508 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4508 # number of overall misses +system.cpu.icache.overall_misses::total 4508 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 196984000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 196984000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 196984000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 196984000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 196984000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 196984000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 49091191 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 49091191 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 49091191 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 49091191 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 49091191 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 49091191 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43696.539485 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43696.539485 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43696.539485 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43696.539485 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43696.539485 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43696.539485 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 220 # 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number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 488 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3901 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 3901 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 3901 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 3901 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 3901 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 3901 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 169767000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 169767000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 169767000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 169767000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 169767000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 169767000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43518.841323 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43518.841323 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43518.841323 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 43518.841323 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43518.841323 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 43518.841323 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 598 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 598 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 598 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 598 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 598 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 598 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3910 # 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number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44015.473146 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44015.473146 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44015.473146 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 44015.473146 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44015.473146 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 44015.473146 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3285.037423 # Cycle average of tags in use -system.cpu.dcache.total_refs 168261838 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3285.555145 # Cycle average of tags in use +system.cpu.dcache.total_refs 168254416 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40525.490848 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40523.703276 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3285.037423 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.802011 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.802011 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 94753259 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94753259 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73508579 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73508579 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168261838 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168261838 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168261838 # number of overall hits -system.cpu.dcache.overall_hits::total 168261838 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1230 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1230 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 12150 # 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number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 588686500 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 3285.555145 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.802137 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.802137 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 94753185 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94753185 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501231 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501231 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168254416 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168254416 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168254416 # number of overall hits +system.cpu.dcache.overall_hits::total 168254416 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1304 # 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miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000013 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000165 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000165 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000080 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000080 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000080 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000080 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51188.617886 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51188.617886 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43269.506173 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43269.506173 # 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miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000265 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000124 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000124 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000124 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000124 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49792.944785 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49792.944785 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36421.120115 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36421.120115 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37259.350062 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37259.350062 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37259.350062 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37259.350062 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15899 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 535 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.717757 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 649 # number of writebacks system.cpu.dcache.writebacks::total 649 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 280 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8948 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 8948 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 9228 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 9228 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 9228 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 9228 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 354 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 354 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16296 # 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mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861592 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861231 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981279 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859079 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.909226 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.908956 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859079 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.909226 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35190.244855 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42310.946602 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36594.951161 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33460.133545 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33460.133545 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35190.244855 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35297.641723 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35248.460940 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35190.244855 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35297.641723 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35248.460940 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.908956 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35764.973206 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42837.638350 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37158.202008 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35338.099205 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35338.099205 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35764.973206 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36895.070799 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36377.057997 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35764.973206 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36895.070799 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36377.057997 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index bdc3bba7f..698b9cfa0 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.080450 # Number of seconds simulated -sim_ticks 80450416000 # Number of ticks simulated -final_tick 80450416000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.080478 # Number of seconds simulated +sim_ticks 80478305500 # Number of ticks simulated +final_tick 80478305500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 142052 # Simulator instruction rate (inst/s) -host_op_rate 142052 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30428395 # Simulator tick rate (ticks/s) -host_mem_usage 223780 # Number of bytes of host memory used -host_seconds 2643.93 # Real time elapsed on the host +host_inst_rate 240864 # Simulator instruction rate (inst/s) +host_op_rate 240864 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51612452 # Simulator tick rate (ticks/s) +host_mem_usage 224036 # Number of bytes of host memory used +host_seconds 1559.28 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 222592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255232 # Number of bytes read from this memory -system.physmem.bytes_read::total 477824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 222592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 222592 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3478 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3988 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7466 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2766822 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3172538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5939360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2766822 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2766822 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2766822 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3172538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5939360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7466 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 222272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory +system.physmem.bytes_read::total 477632 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 222272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 222272 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3473 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3990 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7463 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2761887 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3173029 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5934916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2761887 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2761887 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2761887 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3173029 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5934916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7463 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7466 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 477824 # Total number of bytes read from memory +system.physmem.cpureqs 7463 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 477632 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 477824 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 477632 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 484 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 488 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 483 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 533 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 530 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 529 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 384 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 388 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 401 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 463 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 460 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 447 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 405 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 456 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 591 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 590 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 408 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 548 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 429 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 401 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 504 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 428 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 399 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 503 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 80450362000 # Total gap between requests +system.physmem.totGap 80478237000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7466 # Categorize read packet sizes +system.physmem.readPktSize::6 7463 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,16 +98,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 3927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2012 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 826 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2068 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 746 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 54925938 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 190713938 # Sum of mem lat for all requests -system.physmem.totBusLat 29864000 # Total cycles spent in databus access -system.physmem.totBankLat 105924000 # Total cycles spent in bank access -system.physmem.avgQLat 7356.81 # Average queueing delay per request -system.physmem.avgBankLat 14187.52 # Average bank access latency per request +system.physmem.totQLat 40041940 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 178323940 # Sum of mem lat for all requests +system.physmem.totBusLat 29852000 # Total cycles spent in databus access +system.physmem.totBankLat 108430000 # Total cycles spent in bank access +system.physmem.avgQLat 5365.39 # Average queueing delay per request +system.physmem.avgBankLat 14529.01 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25544.33 # Average memory access latency -system.physmem.avgRdBW 5.94 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 23894.40 # Average memory access latency +system.physmem.avgRdBW 5.93 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 5.94 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 5.93 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6527 # Number of row buffer hits during reads +system.physmem.readRowHits 6524 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 87.42 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10775564.16 # Average gap between requests +system.physmem.avgGap 10783630.85 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 103443494 # DTB read hits -system.cpu.dtb.read_misses 89204 # DTB read misses -system.cpu.dtb.read_acv 48604 # DTB read access violations -system.cpu.dtb.read_accesses 103532698 # DTB read accesses -system.cpu.dtb.write_hits 79020707 # DTB write hits -system.cpu.dtb.write_misses 1585 # DTB write misses +system.cpu.dtb.read_hits 103426473 # DTB read hits +system.cpu.dtb.read_misses 88806 # DTB read misses +system.cpu.dtb.read_acv 48603 # DTB read access violations +system.cpu.dtb.read_accesses 103515279 # DTB read accesses +system.cpu.dtb.write_hits 79003400 # DTB write hits +system.cpu.dtb.write_misses 1622 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 79022292 # DTB write accesses -system.cpu.dtb.data_hits 182464201 # DTB hits -system.cpu.dtb.data_misses 90789 # DTB misses -system.cpu.dtb.data_acv 48606 # DTB access violations -system.cpu.dtb.data_accesses 182554990 # DTB accesses -system.cpu.itb.fetch_hits 52635617 # ITB hits -system.cpu.itb.fetch_misses 446 # ITB misses +system.cpu.dtb.write_accesses 79005022 # DTB write accesses +system.cpu.dtb.data_hits 182429873 # DTB hits +system.cpu.dtb.data_misses 90428 # DTB misses +system.cpu.dtb.data_acv 48605 # DTB access violations +system.cpu.dtb.data_accesses 182520301 # DTB accesses +system.cpu.itb.fetch_hits 52621913 # ITB hits +system.cpu.itb.fetch_misses 460 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 52636063 # ITB accesses +system.cpu.itb.fetch_accesses 52622373 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,146 +218,147 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 160900834 # number of cpu cycles simulated +system.cpu.numCycles 160956613 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 52082511 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 30304197 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1627462 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 28687866 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 24364965 # Number of BTB hits +system.cpu.BPredUnit.lookups 52100857 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 30315970 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1626186 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 28771875 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 24368935 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 9358559 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1149 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 53712913 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 462927523 # Number of instructions fetch has processed -system.cpu.fetch.Branches 52082511 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33723524 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 81628321 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7863564 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19256748 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 186 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8496 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 52635617 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 625198 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 160803654 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.878837 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.313069 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 9361706 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1114 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 53696929 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 462928228 # Number of instructions fetch has processed +system.cpu.fetch.Branches 52100857 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33730641 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 81620286 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 7858922 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19257347 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 187 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9632 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 52621913 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 634331 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 160777203 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.879315 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.313319 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 79175333 49.24% 49.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4378645 2.72% 51.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 7276914 4.53% 56.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5654242 3.52% 60.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 12481747 7.76% 67.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 8090070 5.03% 72.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5699527 3.54% 76.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1919584 1.19% 77.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36127592 22.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 79156917 49.23% 49.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4375069 2.72% 51.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 7280350 4.53% 56.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5649836 3.51% 60.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12467952 7.75% 67.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 8098174 5.04% 72.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5694595 3.54% 76.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1921777 1.20% 77.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36132533 22.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 160803654 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.323693 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.877098 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 59260573 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 14714376 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76844391 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3791608 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6192706 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9758398 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4357 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 457340975 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12460 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6192706 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 62581380 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4767420 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 396481 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 77424943 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9440724 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 451604153 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 25 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 23405 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 7795110 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 295281147 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 593898440 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 314599798 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 279298642 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 160777203 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.323695 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.876106 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 59247838 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 14720272 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76811336 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3809242 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6188515 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9757922 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4354 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 457314858 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12387 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6188515 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 62549995 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4761260 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 404034 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 77430709 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9442690 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 451606730 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 77 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 23776 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7810662 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 295220073 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 593857298 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 314533396 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 279323902 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35748818 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 38358 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 348 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27322373 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 107078098 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 81809760 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8914792 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6385731 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 416755970 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 334 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 407971342 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1213804 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 40920126 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20099668 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 119 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 160803654 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.537078 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.007577 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 35687744 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 38419 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 331 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27285006 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 107056185 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 81810329 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8900910 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6383401 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 416688223 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 322 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 407927915 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1196295 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 40854151 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20088069 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 107 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 160777203 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.537225 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.006885 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 32260500 20.06% 20.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 26539337 16.50% 36.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 26078054 16.22% 52.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24787830 15.41% 68.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21571430 13.41% 81.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15523746 9.65% 91.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8624317 5.36% 96.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4085465 2.54% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1332975 0.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 32206126 20.03% 20.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 26582948 16.53% 36.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 26044704 16.20% 52.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24850018 15.46% 68.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21542644 13.40% 81.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15495200 9.64% 91.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8651076 5.38% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4083423 2.54% 99.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1321064 0.82% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 160803654 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 160777203 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 36186 0.30% 0.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35727 0.30% 0.30% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.30% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 74788 0.63% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 4408 0.04% 0.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3062 0.03% 1.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1840642 15.50% 16.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1784659 15.03% 31.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 31.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 31.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5098486 42.94% 74.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3030945 25.53% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 75761 0.64% 0.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 4382 0.04% 0.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3108 0.03% 1.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1825209 15.42% 16.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1783394 15.07% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5084367 42.96% 74.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3023635 25.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 158101841 38.75% 38.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126541 0.52% 39.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 158069721 38.75% 38.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126542 0.52% 39.28% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33488456 8.21% 47.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7847707 1.92% 49.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2841085 0.70% 50.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16565313 4.06% 54.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1591977 0.39% 54.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33490518 8.21% 47.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7849895 1.92% 49.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2841429 0.70% 50.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16561983 4.06% 54.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1589872 0.39% 54.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.56% # Type of FU issued @@ -379,84 +380,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.56% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 105357579 25.82% 80.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 80017262 19.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 105338931 25.82% 80.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 80025443 19.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 407971342 # Type of FU issued -system.cpu.iq.rate 2.535545 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11873176 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029103 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 648496700 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 270371889 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237775030 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 341336618 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 187355366 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 162947679 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 245502336 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 174308601 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 14799025 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 407927915 # Type of FU issued +system.cpu.iq.rate 2.534397 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11835583 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029014 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 648317888 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 270248085 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237722545 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 341347023 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 187344847 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 162957273 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 245426205 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 174303712 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 14794032 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12323611 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 124858 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 50857 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8289031 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12301698 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 125436 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 50278 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8289600 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260769 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 122 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260794 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2630 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6192706 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2493954 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 366810 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 441694516 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 229015 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 107078098 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 81809760 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 334 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 117 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 78 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 50857 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1275804 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 567133 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1842937 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 403387908 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 103581364 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4583434 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6188515 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2498531 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 365597 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 441640864 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 208656 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 107056185 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 81810329 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 322 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 105 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 92 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 50278 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1277121 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 568437 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1845558 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 403336755 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103563942 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4591160 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24938212 # number of nop insts executed -system.cpu.iew.exec_refs 182603691 # number of memory reference insts executed -system.cpu.iew.exec_branches 47210628 # Number of branches executed -system.cpu.iew.exec_stores 79022327 # Number of stores executed -system.cpu.iew.exec_rate 2.507059 # Inst execution rate -system.cpu.iew.wb_sent 401574040 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 400722709 # cumulative count of insts written-back -system.cpu.iew.wb_producers 195201608 # num instructions producing a value -system.cpu.iew.wb_consumers 273256469 # num instructions consuming a value +system.cpu.iew.exec_nop 24952319 # number of nop insts executed +system.cpu.iew.exec_refs 182568992 # number of memory reference insts executed +system.cpu.iew.exec_branches 47207101 # Number of branches executed +system.cpu.iew.exec_stores 79005050 # Number of stores executed +system.cpu.iew.exec_rate 2.505873 # Inst execution rate +system.cpu.iew.wb_sent 401526892 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 400679818 # cumulative count of insts written-back +system.cpu.iew.wb_producers 195200441 # num instructions producing a value +system.cpu.iew.wb_consumers 273221552 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.490495 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.714353 # average fanout of values written-back +system.cpu.iew.wb_rate 2.489365 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.714440 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 43076400 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 43021782 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1623178 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 154610948 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.578502 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.964409 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1621908 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 154588688 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.578873 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.965339 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58949463 38.13% 38.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 23452675 15.17% 53.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13321237 8.62% 61.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11705960 7.57% 69.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8475693 5.48% 74.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5493357 3.55% 78.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5136307 3.32% 81.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3345893 2.16% 84.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 24730363 16.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58995602 38.16% 38.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 23401293 15.14% 53.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13308874 8.61% 61.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11694068 7.56% 69.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8446337 5.46% 74.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5505575 3.56% 78.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5146283 3.33% 81.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3352831 2.17% 84.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 24737825 16.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 154610948 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 154588688 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -467,204 +468,204 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 24730363 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 24737825 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 571618591 # The number of ROB reads -system.cpu.rob.rob_writes 889688372 # The number of ROB writes -system.cpu.timesIdled 2869 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 97180 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 571534251 # The number of ROB reads +system.cpu.rob.rob_writes 889574996 # The number of ROB writes +system.cpu.timesIdled 3393 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 179410 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.428412 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.428412 # CPI: Total CPI of All Threads -system.cpu.ipc 2.334201 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.334201 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 402943078 # number of integer regfile reads -system.cpu.int_regfile_writes 172629700 # number of integer regfile writes -system.cpu.fp_regfile_reads 158343488 # number of floating regfile reads -system.cpu.fp_regfile_writes 105222580 # number of floating regfile writes +system.cpu.cpi 0.428561 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.428561 # CPI: Total CPI of All Threads +system.cpu.ipc 2.333392 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.333392 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 402843963 # number of integer regfile reads +system.cpu.int_regfile_writes 172601197 # number of integer regfile writes +system.cpu.fp_regfile_reads 158371131 # number of floating regfile reads +system.cpu.fp_regfile_writes 105217877 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 2200 # number of replacements -system.cpu.icache.tagsinuse 1838.464064 # Cycle average of tags in use -system.cpu.icache.total_refs 52630329 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4132 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12737.252904 # Average number of references to valid blocks. +system.cpu.icache.replacements 2196 # number of replacements +system.cpu.icache.tagsinuse 1834.742216 # Cycle average of tags in use +system.cpu.icache.total_refs 52616364 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4124 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12758.575170 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1838.464064 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.897688 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.897688 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 52630329 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 52630329 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 52630329 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 52630329 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 52630329 # number of overall hits -system.cpu.icache.overall_hits::total 52630329 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5288 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5288 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5288 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5288 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5288 # number of overall misses -system.cpu.icache.overall_misses::total 5288 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 146095500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 146095500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 146095500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 146095500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 146095500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 146095500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 52635617 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 52635617 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 52635617 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 52635617 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 52635617 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 52635617 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000100 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000100 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000100 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000100 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000100 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000100 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27627.742057 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27627.742057 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27627.742057 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27627.742057 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27627.742057 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27627.742057 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1834.742216 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.895870 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.895870 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 52616364 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 52616364 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 52616364 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 52616364 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 52616364 # number of overall hits +system.cpu.icache.overall_hits::total 52616364 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5549 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5549 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5549 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5549 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5549 # number of overall misses +system.cpu.icache.overall_misses::total 5549 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 228035499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 228035499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 228035499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 228035499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 228035499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 228035499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 52621913 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 52621913 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 52621913 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 52621913 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 52621913 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 52621913 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000105 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000105 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000105 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000105 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000105 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000105 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41094.881781 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41094.881781 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41094.881781 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41094.881781 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41094.881781 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41094.881781 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 278 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 46.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1156 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1156 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1156 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1156 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1156 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1156 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4132 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4132 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4132 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4132 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4132 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4132 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 115307000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 115307000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 115307000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 115307000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 115307000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 115307000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27905.856728 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27905.856728 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27905.856728 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27905.856728 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27905.856728 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27905.856728 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1425 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1425 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1425 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1425 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1425 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1425 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4124 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4124 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4124 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4124 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4124 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4124 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176594499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 176594499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176594499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 176594499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176594499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 176594499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000078 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000078 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000078 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000078 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42821.168526 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42821.168526 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42821.168526 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 42821.168526 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42821.168526 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 42821.168526 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 781 # number of replacements -system.cpu.dcache.tagsinuse 3295.904807 # Cycle average of tags in use -system.cpu.dcache.total_refs 161883653 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4181 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 38718.883760 # Average number of references to valid blocks. +system.cpu.dcache.replacements 785 # number of replacements +system.cpu.dcache.tagsinuse 3296.121228 # Cycle average of tags in use +system.cpu.dcache.total_refs 161868539 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4185 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 38678.264994 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3295.904807 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.804664 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.804664 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88381720 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88381720 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501913 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501913 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 20 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 20 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 161883633 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161883633 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 161883633 # number of overall hits -system.cpu.dcache.overall_hits::total 161883633 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1838 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1838 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 18816 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 18816 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 20654 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20654 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 20654 # number of overall misses -system.cpu.dcache.overall_misses::total 20654 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63964000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63964000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 503501000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 503501000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 567465000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 567465000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 567465000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 567465000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88383558 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88383558 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 3296.121228 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.804717 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.804717 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88367648 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88367648 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73500876 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73500876 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 161868524 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161868524 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 161868524 # number of overall hits +system.cpu.dcache.overall_hits::total 161868524 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1780 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1780 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19853 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19853 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21633 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21633 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21633 # number of overall misses +system.cpu.dcache.overall_misses::total 21633 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 82604000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 82604000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 720118126 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 720118126 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 802722126 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 802722126 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 802722126 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 802722126 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88369428 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88369428 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 20 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 161904287 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 161904287 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 161904287 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 161904287 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000256 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000256 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000128 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000128 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000128 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34800.870511 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34800.870511 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26759.194303 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26759.194303 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 27474.823279 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 27474.823279 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 27474.823279 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 27474.823279 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 613 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 161890157 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 161890157 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 161890157 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 161890157 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000270 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000270 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000134 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000134 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000134 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000134 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46406.741573 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 46406.741573 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36272.509243 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36272.509243 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37106.371100 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37106.371100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37106.371100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37106.371100 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23536 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 627 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 153.250000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.537480 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 659 # number of writebacks -system.cpu.dcache.writebacks::total 659 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 852 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 852 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15621 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15621 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16473 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16473 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16473 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16473 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 986 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 986 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3195 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3195 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4181 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4181 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4181 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4181 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35567000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 35567000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 111777000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 111777000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 147344000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 147344000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 147344000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 147344000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 663 # number of writebacks +system.cpu.dcache.writebacks::total 663 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 792 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 792 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16656 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16656 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17448 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17448 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17448 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17448 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 988 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 988 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3197 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3197 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4185 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4185 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4185 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4185 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51049000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 51049000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 155266000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 155266000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 206315000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 206315000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 206315000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 206315000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -673,150 +674,150 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36072.008114 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36072.008114 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34984.976526 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34984.976526 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35241.329825 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35241.329825 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35241.329825 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 35241.329825 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51669.028340 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51669.028340 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48566.155771 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48566.155771 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49298.685783 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 49298.685783 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49298.685783 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 49298.685783 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 4031.024226 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 4033.088389 # Cycle average of tags in use system.cpu.l2cache.total_refs 872 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4868 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.179129 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 371.780085 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3001.770453 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 657.473688 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011346 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.091607 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020065 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.123017 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 654 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 129 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 783 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 659 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 659 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 64 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 64 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 654 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 193 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 847 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 654 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 193 # number of overall hits -system.cpu.l2cache.overall_hits::total 847 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3478 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 857 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4335 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 3131 # 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average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34625.519004 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34625.519004 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 31770.557792 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 35810.305918 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 33928.408786 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 31770.557792 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35810.305918 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 33928.408786 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 578 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::writebacks 372.600673 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3001.103813 # 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number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3473 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3990 # number of overall misses +system.cpu.l2cache.overall_misses::total 7463 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 165942000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48709500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 214651500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 151316000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 151316000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 165942000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 200025500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 365967500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 165942000 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 129608656 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 227771470 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.841723 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869168 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.847011 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.979969 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.979969 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.841723 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.953839 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.898111 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.841723 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28223.925819 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32499.662989 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30507.831503 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3473 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 858 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4331 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3132 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3132 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3473 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3990 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7463 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 122186799 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 150677003 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 272863802 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.842144 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.868421 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.847222 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.979668 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.979668 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.842144 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.953405 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.898183 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.842144 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.953405 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.898183 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35181.917363 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44349.649184 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36998.106211 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35959.452107 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35959.452107 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35181.917363 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37763.659900 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36562.213855 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35181.917363 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37763.659900 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36562.213855 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 10dc822fe..26c4b55f8 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.567335 # Nu sim_ticks 567335093000 # Number of ticks simulated final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1259990 # Simulator instruction rate (inst/s) -host_op_rate 1259990 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1793077476 # Simulator tick rate (ticks/s) -host_mem_usage 225476 # Number of bytes of host memory used -host_seconds 316.40 # Real time elapsed on the host +host_inst_rate 1803555 # Simulator instruction rate (inst/s) +host_op_rate 1803555 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2566617886 # Simulator tick rate (ticks/s) +host_mem_usage 223016 # Number of bytes of host memory used +host_seconds 221.04 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory @@ -262,9 +262,9 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 3772.485305 # Cycle average of tags in use -system.cpu.l2cache.total_refs 674 # Total number of references to valid blocks. +system.cpu.l2cache.total_refs 677 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4566 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.147613 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.148270 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 371.540221 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 2770.469924 # Average occupied blocks per requestor diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 843436b83..d021c65df 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.071023 # Number of seconds simulated -sim_ticks 71023388000 # Number of ticks simulated -final_tick 71023388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.071124 # Number of seconds simulated +sim_ticks 71123520500 # Number of ticks simulated +final_tick 71123520500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 129198 # Simulator instruction rate (inst/s) -host_op_rate 165172 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33606101 # Simulator tick rate (ticks/s) -host_mem_usage 240544 # Number of bytes of host memory used -host_seconds 2113.41 # Real time elapsed on the host -sim_insts 273048441 # Number of instructions simulated -sim_ops 349076165 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 194880 # Number of bytes read from this memory +host_inst_rate 165652 # Simulator instruction rate (inst/s) +host_op_rate 211776 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43149002 # Simulator tick rate (ticks/s) +host_mem_usage 241844 # Number of bytes of host memory used +host_seconds 1648.32 # Real time elapsed on the host +sim_insts 273048466 # Number of instructions simulated +sim_ops 349076190 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 194944 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 272832 # Number of bytes read from this memory -system.physmem.bytes_read::total 467712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 194880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 194880 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3045 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 467776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 194944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 194944 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3046 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4263 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7308 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2743885 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3841439 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6585324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2743885 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2743885 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2743885 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3841439 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6585324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7308 # Total number of read requests seen +system.physmem.num_reads::total 7309 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2740922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3836031 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6576952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2740922 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2740922 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2740922 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3836031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6576952 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7309 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7308 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 467712 # Total number of bytes read from memory +system.physmem.cpureqs 7309 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 467776 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 467712 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 467776 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 345 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 467 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 513 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 346 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 470 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 514 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 578 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 475 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 461 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 441 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 510 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 477 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 456 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 440 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 507 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 480 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 494 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 484 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 551 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 363 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 415 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 369 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 362 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 365 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 416 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 368 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 363 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 71023232000 # Total gap between requests +system.physmem.totGap 71123348000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7308 # Categorize read packet sizes +system.physmem.readPktSize::6 7309 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,13 +98,13 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2152 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 666 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 75 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 41389289 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 172709289 # Sum of mem lat for all requests -system.physmem.totBusLat 29232000 # Total cycles spent in databus access -system.physmem.totBankLat 102088000 # Total cycles spent in bank access -system.physmem.avgQLat 5663.56 # Average queueing delay per request -system.physmem.avgBankLat 13969.35 # Average bank access latency per request +system.physmem.totQLat 38077286 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 170549286 # Sum of mem lat for all requests +system.physmem.totBusLat 29236000 # Total cycles spent in databus access +system.physmem.totBankLat 103236000 # Total cycles spent in bank access +system.physmem.avgQLat 5209.64 # Average queueing delay per request +system.physmem.avgBankLat 14124.50 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23632.91 # Average memory access latency -system.physmem.avgRdBW 6.59 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 23334.15 # Average memory access latency +system.physmem.avgRdBW 6.58 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.59 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 6.58 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6370 # Number of row buffer hits during reads +system.physmem.readRowHits 6380 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.16 # Row buffer hit rate for reads +system.physmem.readRowHitRate 87.29 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9718559.39 # Average gap between requests +system.physmem.avgGap 9730927.35 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -228,107 +228,108 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 142046777 # number of cpu cycles simulated +system.cpu.numCycles 142247042 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 43162042 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 21862143 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2121703 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 28877793 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 17918646 # Number of BTB hits +system.cpu.BPredUnit.lookups 43100384 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 21816758 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2115490 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 28214597 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 17877846 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 6972885 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 7671 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 40968439 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 329355833 # Number of instructions fetch has processed -system.cpu.fetch.Branches 43162042 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24891531 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 73809901 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8464308 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 20842753 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2971 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 39491995 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 707720 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 141956225 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.979912 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.453592 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 6960493 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 7483 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 41104486 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 329097721 # Number of instructions fetch has processed +system.cpu.fetch.Branches 43100384 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24838339 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 73741038 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8424830 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 20890852 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 101 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 3376 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 39439386 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 697861 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 142038328 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.976886 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.453881 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68825893 48.48% 48.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 7402388 5.21% 53.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5830184 4.11% 57.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6288593 4.43% 62.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4967322 3.50% 65.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4323548 3.05% 68.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3311772 2.33% 71.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4321361 3.04% 74.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36685164 25.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68979513 48.56% 48.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 7395782 5.21% 53.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5795573 4.08% 57.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6270161 4.41% 62.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4963047 3.49% 65.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4315752 3.04% 68.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3304919 2.33% 71.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4334607 3.05% 74.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36678974 25.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 141956225 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.303858 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.318643 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 47854672 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16043866 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 69433090 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2362421 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6262176 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7513619 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 70716 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 415062954 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 220817 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6262176 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 53639950 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1545689 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 333184 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 65936980 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14238246 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 404539854 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 67 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1667551 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10176735 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 553 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 443995291 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2389355526 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1302857658 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1086497868 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 384584946 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 59410345 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 14542 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 14541 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 35671511 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 105577606 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 93228051 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4593885 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5660351 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 392311117 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25611 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 378254160 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1403521 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 42287591 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 111052876 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1134 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 141956225 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.664583 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.042822 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 142038328 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.302997 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.313565 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 47965638 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16109831 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 69363004 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2371211 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6228644 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7501471 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 70557 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 414890822 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 218836 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6228644 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 53736634 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1580220 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 347679 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 65886950 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14258201 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 404388597 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 136 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1669522 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10203430 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 860 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 443737755 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2388674830 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1302452182 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1086222648 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 384584986 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 59152769 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 14467 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 14465 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 35681480 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 105493757 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 93214934 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4606734 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5678105 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 392069014 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25544 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 378019437 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1377395 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 42071369 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 110527513 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1062 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 142038328 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.661390 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.043453 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28896984 20.36% 20.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20515288 14.45% 34.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20937445 14.75% 49.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18231025 12.84% 62.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24110473 16.98% 79.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15997056 11.27% 90.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9050570 6.38% 97.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3298757 2.32% 99.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 918627 0.65% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 29008018 20.42% 20.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20551186 14.47% 34.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20935508 14.74% 49.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18224796 12.83% 62.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24071271 16.95% 79.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15985787 11.25% 90.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9045864 6.37% 97.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3293540 2.32% 99.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 922358 0.65% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 141956225 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 142038328 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9062 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4694 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9132 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4698 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -347,22 +348,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 45808 0.25% 0.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 45614 0.25% 0.33% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7711 0.04% 0.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 383 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7807 0.04% 0.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 399 0.00% 0.38% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 193806 1.08% 1.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 5491 0.03% 1.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241038 1.34% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9458380 52.63% 55.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 8006771 44.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 193826 1.08% 1.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 4889 0.03% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 240972 1.34% 2.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9466915 52.66% 55.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 8004617 44.52% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 128369790 33.94% 33.94% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2174598 0.57% 34.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 128267116 33.93% 33.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2174674 0.58% 34.51% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.51% # Type of FU issued @@ -381,315 +382,315 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.51% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6843583 1.81% 36.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6840592 1.81% 36.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8689764 2.30% 38.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3465929 0.92% 39.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1622822 0.43% 39.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21343412 5.64% 45.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7172666 1.90% 47.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7136167 1.89% 49.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175288 0.05% 49.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 102562726 27.11% 76.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88697415 23.45% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8692743 2.30% 38.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3457219 0.91% 39.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1621907 0.43% 39.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21346208 5.65% 45.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7171870 1.90% 47.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7135741 1.89% 49.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 102459140 27.10% 76.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88676941 23.46% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 378254160 # Type of FU issued -system.cpu.iq.rate 2.662884 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17973147 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047516 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 666559792 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 301879538 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 252435570 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 251281421 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 132758695 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118859507 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266684443 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 129542864 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 10845590 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 378019437 # Type of FU issued +system.cpu.iq.rate 2.657485 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17978872 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047561 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 666289235 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 301587031 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 252300909 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 251144234 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 132592793 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118832927 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266512180 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 129486129 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 10875090 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10926514 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 120350 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14368 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10850116 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10842660 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 119827 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14278 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10836994 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 27154 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 78 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19866 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1167 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6262176 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 55211 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 11686 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 392346402 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1078418 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 105577606 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 93228051 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 14439 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 194 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 331 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14368 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1702737 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 499287 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2202024 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 373561232 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101191974 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4692928 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6228644 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 80063 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4890 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 392103714 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1113019 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 105493757 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 93214934 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 14372 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 353 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 361 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14278 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1696490 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 500488 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2196978 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 373371007 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101101213 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4648430 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9674 # number of nop insts executed -system.cpu.iew.exec_refs 188550520 # number of memory reference insts executed -system.cpu.iew.exec_branches 38725245 # Number of branches executed -system.cpu.iew.exec_stores 87358546 # Number of stores executed -system.cpu.iew.exec_rate 2.629847 # Inst execution rate -system.cpu.iew.wb_sent 372099364 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 371295077 # cumulative count of insts written-back -system.cpu.iew.wb_producers 184920977 # num instructions producing a value -system.cpu.iew.wb_consumers 367888043 # num instructions consuming a value +system.cpu.iew.exec_nop 9156 # number of nop insts executed +system.cpu.iew.exec_refs 188456752 # number of memory reference insts executed +system.cpu.iew.exec_branches 38701393 # Number of branches executed +system.cpu.iew.exec_stores 87355539 # Number of stores executed +system.cpu.iew.exec_rate 2.624807 # Inst execution rate +system.cpu.iew.wb_sent 371934669 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 371133836 # cumulative count of insts written-back +system.cpu.iew.wb_producers 184775670 # num instructions producing a value +system.cpu.iew.wb_consumers 367646771 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.613893 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.502656 # average fanout of values written-back +system.cpu.iew.wb_rate 2.609079 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.502590 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 43269770 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 24477 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2051746 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 135694050 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.572528 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.654395 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 43027028 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 24482 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2045711 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 135809685 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.570338 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.654112 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 38297743 28.22% 28.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 29217550 21.53% 49.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13522381 9.97% 59.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11119570 8.19% 67.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13774007 10.15% 78.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7289874 5.37% 83.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3949510 2.91% 86.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3974023 2.93% 89.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14549392 10.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 38417531 28.29% 28.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 29199317 21.50% 49.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13525216 9.96% 59.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11128430 8.19% 67.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13789447 10.15% 78.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7275712 5.36% 83.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3957925 2.91% 86.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3970991 2.92% 89.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14545116 10.71% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 135694050 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273049053 # Number of instructions committed -system.cpu.commit.committedOps 349076777 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 135809685 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273049078 # Number of instructions committed +system.cpu.commit.committedOps 349076802 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 177029027 # Number of memory references committed -system.cpu.commit.loads 94651092 # Number of loads committed +system.cpu.commit.refs 177029037 # Number of memory references committed +system.cpu.commit.loads 94651097 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 36549055 # Number of branches committed +system.cpu.commit.branches 36549060 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 279593983 # Number of committed integer instructions. +system.cpu.commit.int_insts 279594003 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14549392 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14545116 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 513488682 # The number of ROB reads -system.cpu.rob.rob_writes 790959694 # The number of ROB writes -system.cpu.timesIdled 2717 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 90552 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273048441 # Number of Instructions Simulated -system.cpu.committedOps 349076165 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 273048441 # Number of Instructions Simulated -system.cpu.cpi 0.520226 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.520226 # CPI: Total CPI of All Threads -system.cpu.ipc 1.922243 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.922243 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1784209945 # number of integer regfile reads -system.cpu.int_regfile_writes 236299492 # number of integer regfile writes -system.cpu.fp_regfile_reads 189823111 # number of floating regfile reads -system.cpu.fp_regfile_writes 133661428 # number of floating regfile writes -system.cpu.misc_regfile_reads 991633784 # number of misc regfile reads -system.cpu.misc_regfile_writes 34426469 # number of misc regfile writes -system.cpu.icache.replacements 13962 # number of replacements -system.cpu.icache.tagsinuse 1856.548325 # Cycle average of tags in use -system.cpu.icache.total_refs 39475406 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15856 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2489.619450 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 513365876 # The number of ROB reads +system.cpu.rob.rob_writes 790440754 # The number of ROB writes +system.cpu.timesIdled 6359 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 208714 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273048466 # Number of Instructions Simulated +system.cpu.committedOps 349076190 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 273048466 # Number of Instructions Simulated +system.cpu.cpi 0.520959 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.520959 # CPI: Total CPI of All Threads +system.cpu.ipc 1.919537 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.919537 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1783321389 # number of integer regfile reads +system.cpu.int_regfile_writes 236147934 # number of integer regfile writes +system.cpu.fp_regfile_reads 189806588 # number of floating regfile reads +system.cpu.fp_regfile_writes 133619756 # number of floating regfile writes +system.cpu.misc_regfile_reads 991070858 # number of misc regfile reads +system.cpu.misc_regfile_writes 34426479 # number of misc regfile writes +system.cpu.icache.replacements 14002 # number of replacements +system.cpu.icache.tagsinuse 1857.450296 # Cycle average of tags in use +system.cpu.icache.total_refs 39422164 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15897 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2479.849280 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1856.548325 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.906518 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.906518 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 39475406 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 39475406 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 39475406 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 39475406 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 39475406 # number of overall hits -system.cpu.icache.overall_hits::total 39475406 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 16589 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 16589 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 16589 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 16589 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 16589 # number of overall misses -system.cpu.icache.overall_misses::total 16589 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 174124000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 174124000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 174124000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 174124000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 174124000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 174124000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 39491995 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 39491995 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 39491995 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 39491995 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 39491995 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 39491995 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000420 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000420 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000420 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000420 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000420 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000420 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10496.353005 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10496.353005 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10496.353005 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10496.353005 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10496.353005 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10496.353005 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1857.450296 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.906958 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.906958 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 39422164 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 39422164 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 39422164 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 39422164 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 39422164 # number of overall hits +system.cpu.icache.overall_hits::total 39422164 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17219 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17219 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17219 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17219 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17219 # number of overall misses +system.cpu.icache.overall_misses::total 17219 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 362034000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 362034000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 362034000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 362034000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 362034000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 362034000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 39439383 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 39439383 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 39439383 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 39439383 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 39439383 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 39439383 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000437 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000437 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000437 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000437 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000437 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000437 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21025.262791 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21025.262791 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21025.262791 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21025.262791 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21025.262791 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21025.262791 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 660 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 733 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 733 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 733 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 733 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 733 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 733 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15856 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15856 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15856 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15856 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15856 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15856 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 125938500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 125938500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 125938500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 125938500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125938500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 125938500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000401 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000401 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000401 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000401 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000401 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000401 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7942.640010 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7942.640010 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7942.640010 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7942.640010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7942.640010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7942.640010 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1322 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1322 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1322 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1322 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1322 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1322 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15897 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15897 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15897 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15897 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15897 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15897 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 295359000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 295359000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 295359000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 295359000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 295359000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 295359000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000403 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000403 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000403 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18579.543310 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18579.543310 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18579.543310 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18579.543310 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18579.543310 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18579.543310 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1428 # number of replacements -system.cpu.dcache.tagsinuse 3114.448538 # Cycle average of tags in use -system.cpu.dcache.total_refs 172176390 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4628 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37203.195765 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1413 # number of replacements +system.cpu.dcache.tagsinuse 3122.832455 # Cycle average of tags in use +system.cpu.dcache.total_refs 172062891 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4620 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37243.050000 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3114.448538 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.760363 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.760363 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 90117753 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 90117753 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031823 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031823 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 13562 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 13562 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 13252 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 13252 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 172149576 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 172149576 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 172149576 # number of overall hits -system.cpu.dcache.overall_hits::total 172149576 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3920 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3920 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 20837 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 20837 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 3122.832455 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.762410 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.762410 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 90004626 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 90004626 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031443 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031443 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 13565 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 13565 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 13257 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 13257 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 172036069 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 172036069 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 172036069 # number of overall hits +system.cpu.dcache.overall_hits::total 172036069 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4061 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4061 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21217 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21217 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 24757 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 24757 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 24757 # number of overall misses -system.cpu.dcache.overall_misses::total 24757 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 107051000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 107051000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 536036000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 536036000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 83000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 83000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 643087000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 643087000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 643087000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 643087000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 90121673 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 90121673 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 25278 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25278 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25278 # number of overall misses +system.cpu.dcache.overall_misses::total 25278 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 164288500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 164288500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 827896681 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 827896681 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 992185181 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 992185181 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 992185181 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 992185181 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 90008687 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 90008687 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13564 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13564 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 13252 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 13252 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 172174333 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 172174333 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 172174333 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 172174333 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000043 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000254 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000254 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13567 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13567 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 13257 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 13257 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 172061347 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 172061347 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 172061347 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 172061347 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000259 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000259 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000147 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000147 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000144 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000144 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000144 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000144 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27308.928571 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27308.928571 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25725.200365 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25725.200365 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 41500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 41500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25975.966393 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25975.966393 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25975.966393 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25975.966393 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 365 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 30.416667 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40455.183452 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40455.183452 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39020.440260 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39020.440260 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39250.936823 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39250.936823 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39250.936823 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39250.936823 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13009 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 844 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 400 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.522500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 52.750000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1045 # number of writebacks -system.cpu.dcache.writebacks::total 1045 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2105 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2105 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18024 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18024 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1035 # number of writebacks +system.cpu.dcache.writebacks::total 1035 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2253 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2253 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18405 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18405 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20129 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20129 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20129 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20129 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1815 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1815 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2813 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2813 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4628 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4628 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4628 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4628 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50564500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 50564500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84395500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84395500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 134960000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 134960000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 134960000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 134960000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 20658 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20658 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20658 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20658 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1808 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1808 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2812 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2812 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4620 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4620 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4620 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4620 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79609500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 79609500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131989000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 131989000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211598500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 211598500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211598500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 211598500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses @@ -698,98 +699,98 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27859.228650 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27859.228650 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30001.955208 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30001.955208 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29161.624892 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29161.624892 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29161.624892 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29161.624892 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44031.803097 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44031.803097 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46937.766714 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46937.766714 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45800.541126 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45800.541126 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45800.541126 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45800.541126 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3987.642168 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13211 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 5425 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.435207 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3986.038510 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13248 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 5422 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.443379 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 370.156310 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2800.588114 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 816.897744 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011296 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.085467 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.024930 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.121693 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12793 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 306 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13099 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.254929 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993957 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993957 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191621 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922727 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.356259 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191621 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922727 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.356259 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36744.794485 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37381.865031 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36951.881232 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33745.878040 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33745.878040 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36744.794485 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34997.107905 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35725.450130 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36744.794485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34997.107905 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35725.450130 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index bd567cfd0..ca0137184 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.652381 # Number of seconds simulated -sim_ticks 652381344000 # Number of ticks simulated -final_tick 652381344000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.643360 # Number of seconds simulated +sim_ticks 643359514000 # Number of ticks simulated +final_tick 643359514000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 170851 # Simulator instruction rate (inst/s) -host_op_rate 170851 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61139648 # Simulator tick rate (ticks/s) -host_mem_usage 240236 # Number of bytes of host memory used -host_seconds 10670.35 # Real time elapsed on the host +host_inst_rate 181804 # Simulator instruction rate (inst/s) +host_op_rate 181804 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64159253 # Simulator tick rate (ticks/s) +host_mem_usage 240484 # Number of bytes of host memory used +host_seconds 10027.54 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 191616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94459904 # Number of bytes read from this memory -system.physmem.bytes_read::total 94651520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 191616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 191616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4281472 # Number of bytes written to this memory -system.physmem.bytes_written::total 4281472 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2994 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1475936 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1478930 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 293718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 144792467 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 145086184 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 293718 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 293718 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6562836 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6562836 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6562836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 293718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 144792467 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 151649021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1478931 # Total number of read requests seen -system.physmem.writeReqs 66898 # Total number of write requests seen -system.physmem.cpureqs 1545829 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 94651520 # Total number of bytes read from memory -system.physmem.bytesWritten 4281472 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 94651520 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 4281472 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 3904 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 179328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30296192 # Number of bytes read from this memory +system.physmem.bytes_read::total 30475520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 179328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 179328 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory +system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2802 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 473378 # Number of read requests responded to by this memory +system.physmem.num_reads::total 476180 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 278737 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47090610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47369347 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 278737 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 278737 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6655862 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6655862 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6655862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 278737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47090610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54025209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 476180 # Total number of read requests seen +system.physmem.writeReqs 66908 # Total number of write requests seen +system.physmem.cpureqs 543088 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30475520 # Total number of bytes read from memory +system.physmem.bytesWritten 4282112 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 30475520 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 78 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 91678 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 92672 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 91873 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 92907 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 92232 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 92052 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 92519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 92192 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 92430 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 91951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 91930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 92149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 91869 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 92596 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 91765 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 92212 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 29588 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29640 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29713 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29989 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29897 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 29812 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29833 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29883 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29824 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29670 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29716 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29651 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29711 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29667 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29710 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29798 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 4187 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 4171 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 4158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 4346 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 4296 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 4154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 4345 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 4311 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 4159 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 4199 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 4202 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 4170 # Tr system.physmem.perBankWrReqs::15 4213 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 652381327000 # Total gap between requests +system.physmem.totGap 643359452500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1478931 # Categorize read packet sizes +system.physmem.readPktSize::6 476180 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 66898 # categorize write packet sizes +system.physmem.writePktSize::6 66908 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1404621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 67056 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2986 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 406668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 67034 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -138,8 +138,8 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 2909 # What write queue length does an incoming req see @@ -152,17 +152,17 @@ system.physmem.wrQLenPdf::10 2909 # Wh system.physmem.wrQLenPdf::11 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 2908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,47 +171,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 5885504293 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 50112950293 # Sum of mem lat for all requests -system.physmem.totBusLat 5900108000 # Total cycles spent in databus access -system.physmem.totBankLat 38327338000 # Total cycles spent in bank access -system.physmem.avgQLat 3990.10 # Average queueing delay per request -system.physmem.avgBankLat 25984.16 # Average bank access latency per request +system.physmem.totQLat 1657778750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 15956610750 # Sum of mem lat for all requests +system.physmem.totBusLat 1904408000 # Total cycles spent in databus access +system.physmem.totBankLat 12394424000 # Total cycles spent in bank access +system.physmem.avgQLat 3481.98 # Average queueing delay per request +system.physmem.avgBankLat 26033.13 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 33974.26 # Average memory access latency -system.physmem.avgRdBW 145.09 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 6.56 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 145.09 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.56 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 33515.11 # Average memory access latency +system.physmem.avgRdBW 47.37 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 6.66 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 47.37 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.66 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.95 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.08 # Average read queue length over time -system.physmem.avgWrQLen 10.99 # Average write queue length over time -system.physmem.readRowHits 824972 # Number of row buffer hits during reads -system.physmem.writeRowHits 37277 # Number of row buffer hits during writes -system.physmem.readRowHitRate 55.93 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 55.72 # Row buffer hit rate for writes -system.physmem.avgGap 422026.84 # Average gap between requests +system.physmem.busUtil 0.34 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.02 # Average read queue length over time +system.physmem.avgWrQLen 10.97 # Average write queue length over time +system.physmem.readRowHits 265466 # Number of row buffer hits during reads +system.physmem.writeRowHits 48780 # Number of row buffer hits during writes +system.physmem.readRowHitRate 55.76 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.91 # Row buffer hit rate for writes +system.physmem.avgGap 1184632.05 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 526096858 # DTB read hits -system.cpu.dtb.read_misses 613073 # DTB read misses +system.cpu.dtb.read_hits 526069225 # DTB read hits +system.cpu.dtb.read_misses 579156 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 526709931 # DTB read accesses -system.cpu.dtb.write_hits 292394059 # DTB write hits -system.cpu.dtb.write_misses 53899 # DTB write misses +system.cpu.dtb.read_accesses 526648381 # DTB read accesses +system.cpu.dtb.write_hits 297161949 # DTB write hits +system.cpu.dtb.write_misses 50214 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 292447958 # DTB write accesses -system.cpu.dtb.data_hits 818490917 # DTB hits -system.cpu.dtb.data_misses 666972 # DTB misses +system.cpu.dtb.write_accesses 297212163 # DTB write accesses +system.cpu.dtb.data_hits 823231174 # DTB hits +system.cpu.dtb.data_misses 629370 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 819157889 # DTB accesses -system.cpu.itb.fetch_hits 401734157 # ITB hits -system.cpu.itb.fetch_misses 1039 # ITB misses +system.cpu.dtb.data_accesses 823860544 # DTB accesses +system.cpu.itb.fetch_hits 405407805 # ITB hits +system.cpu.itb.fetch_misses 819 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 401735196 # ITB accesses +system.cpu.itb.fetch_accesses 405408624 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,245 +225,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1304762689 # number of cpu cycles simulated +system.cpu.numCycles 1286719029 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 395100113 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 257879210 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 27591675 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 325941438 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 262133239 # Number of BTB hits +system.cpu.BPredUnit.lookups 402098178 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 264077360 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 27592144 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 331664988 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 265014495 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 57700479 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 6698 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 421496575 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3322405570 # Number of instructions fetch has processed -system.cpu.fetch.Branches 395100113 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 319833718 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 638480554 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 162110923 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 102053744 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9801 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 401734157 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8363180 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1296072068 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.563442 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.138795 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 57783698 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 7200 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 424132228 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3367367633 # Number of instructions fetch has processed +system.cpu.fetch.Branches 402098178 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 322798193 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 646196241 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 166511643 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 68824339 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 161 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9321 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 70 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 405407805 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 9489583 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1277592072 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.635714 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.156498 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 657591514 50.74% 50.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 60871982 4.70% 55.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 44636510 3.44% 58.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71794407 5.54% 64.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 126302912 9.75% 74.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 45673565 3.52% 77.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41643401 3.21% 80.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7024748 0.54% 81.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 240533029 18.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 631395831 49.42% 49.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 61908546 4.85% 54.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 44955490 3.52% 57.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 72442913 5.67% 63.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 127234893 9.96% 73.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 45699485 3.58% 76.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41229418 3.23% 80.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8398105 0.66% 80.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 244327391 19.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1296072068 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.302814 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.546368 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 453815792 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 84580008 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 615145766 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8511561 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 134018941 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 34684248 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12433 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3231024090 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46816 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 134018941 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 483692761 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37815213 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 26926 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 592981976 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 47536251 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3144588480 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1177 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 7026 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 41373292 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2089769744 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3655475569 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3535468644 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 120006925 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1277592072 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.312499 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.617019 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 452657714 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 55753482 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 621910588 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8852787 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 138417501 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 35688961 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12608 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3272292546 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46854 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 138417501 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 480561611 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 21495863 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 27669 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 602513400 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 34576028 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3180651525 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 116 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 14808 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 29849843 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2112719200 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3696606448 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3567977970 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 128628478 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 704800674 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4226 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 127 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 142344309 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 735042012 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 359395829 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 68166545 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9320020 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2645223582 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 121 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2193823681 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17946245 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 822107127 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 708225593 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 82 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1296072068 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.692671 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.804037 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 727750130 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4257 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 122 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 112675652 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 746614838 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 365012896 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68733869 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9300063 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2678263841 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 113 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2207816608 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17947963 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 855152506 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 736519407 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 74 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1277592072 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.728108 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.823912 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 475835975 36.71% 36.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 218666129 16.87% 53.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 251350949 19.39% 72.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 122837911 9.48% 82.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 105713044 8.16% 90.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 77520434 5.98% 96.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 21238629 1.64% 98.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17216175 1.33% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5692822 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 463406335 36.27% 36.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 208221001 16.30% 52.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 253020667 19.80% 72.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119517466 9.35% 81.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 107963864 8.45% 90.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 79412827 6.22% 96.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 22155797 1.73% 98.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 18005418 1.41% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5888697 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1296072068 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1277592072 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1168166 3.19% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 25201102 68.89% 72.08% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 10214807 27.92% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1146338 3.02% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 26001591 68.56% 71.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 10776371 28.42% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1258217376 57.35% 57.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 16681 0.00% 57.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 29224824 1.33% 58.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254695 0.38% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204652 0.33% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587046185 26.76% 86.15% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 303856512 13.85% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1263752223 57.24% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 17092 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 29225332 1.32% 58.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254699 0.37% 58.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204653 0.33% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 590734000 26.76% 86.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 308625853 13.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2193823681 # Type of FU issued -system.cpu.iq.rate 1.681397 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36584075 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016676 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5583657415 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3378809764 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2023568909 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 154592335 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 88593840 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 75404787 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2151259351 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 79145653 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62323542 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2207816608 # Type of FU issued +system.cpu.iq.rate 1.715850 # Inst issue rate +system.cpu.iq.fu_busy_cnt 37924300 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017177 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5591649635 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3435076999 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2032506919 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 157447916 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 98414178 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 76358311 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2164690748 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 81047408 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 59332604 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 223971986 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 12645 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 76017 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 148600933 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 235544812 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11687 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 77448 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 154218000 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4436 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 69 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4399 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2001 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 134018941 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 11876310 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 832949 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3002252422 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2341492 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 735042012 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 359395829 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 121 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 187560 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4854 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 76017 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 27589712 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 31349 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 27621061 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2103239947 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 526710042 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 90583734 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 138417501 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 7967616 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 401073 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3039337687 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 731219 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 746614838 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 365012896 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 113 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 191088 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1450 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 77448 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 27584304 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 31589 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 27615893 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2113102879 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 526648496 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 94713729 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 357028719 # number of nop insts executed -system.cpu.iew.exec_refs 819158443 # number of memory reference insts executed -system.cpu.iew.exec_branches 282386049 # Number of branches executed -system.cpu.iew.exec_stores 292448401 # Number of stores executed -system.cpu.iew.exec_rate 1.611971 # Inst execution rate -system.cpu.iew.wb_sent 2101749466 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2098973696 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1185216175 # num instructions producing a value -system.cpu.iew.wb_consumers 1752698092 # num instructions consuming a value +system.cpu.iew.exec_nop 361073733 # number of nop insts executed +system.cpu.iew.exec_refs 823861177 # number of memory reference insts executed +system.cpu.iew.exec_branches 283370996 # Number of branches executed +system.cpu.iew.exec_stores 297212681 # Number of stores executed +system.cpu.iew.exec_rate 1.642241 # Inst execution rate +system.cpu.iew.wb_sent 2111610495 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2108865230 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1193923515 # num instructions producing a value +system.cpu.iew.wb_consumers 1771725000 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.608702 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.676224 # average fanout of values written-back +system.cpu.iew.wb_rate 1.638948 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.673876 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 976452699 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1013373341 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 27579406 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1162053127 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.728826 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.486115 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 27579934 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1139174571 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.763547 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.475615 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 542846661 46.71% 46.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 230306455 19.82% 66.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119679848 10.30% 76.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 57176464 4.92% 81.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 50189917 4.32% 86.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25112757 2.16% 88.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18284566 1.57% 89.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 15890460 1.37% 91.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102565999 8.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 512941432 45.03% 45.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 233024401 20.46% 65.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 122205483 10.73% 76.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 58495999 5.13% 81.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 54572847 4.79% 86.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24070176 2.11% 88.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 18202956 1.60% 89.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 17085980 1.50% 91.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 98575297 8.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1162053127 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1139174571 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -474,358 +475,374 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 102565999 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 98575297 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4039291021 # The number of ROB reads -system.cpu.rob.rob_writes 6104902002 # The number of ROB writes -system.cpu.timesIdled 33492 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8690621 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 4057323809 # The number of ROB reads +system.cpu.rob.rob_writes 6183141843 # The number of ROB writes +system.cpu.timesIdled 212566 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 9126957 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.715706 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.715706 # CPI: Total CPI of All Threads -system.cpu.ipc 1.397222 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.397222 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2679345799 # number of integer regfile reads -system.cpu.int_regfile_writes 1518234716 # number of integer regfile writes -system.cpu.fp_regfile_reads 81979255 # number of floating regfile reads -system.cpu.fp_regfile_writes 54034777 # number of floating regfile writes +system.cpu.cpi 0.705808 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.705808 # CPI: Total CPI of All Threads +system.cpu.ipc 1.416815 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.416815 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2692001611 # number of integer regfile reads +system.cpu.int_regfile_writes 1522401675 # number of integer regfile writes +system.cpu.fp_regfile_reads 82933521 # number of floating regfile reads +system.cpu.fp_regfile_writes 54035244 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8417 # number of replacements -system.cpu.icache.tagsinuse 1668.126238 # Cycle average of tags in use -system.cpu.icache.total_refs 401722811 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10139 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 39621.541671 # Average number of references to valid blocks. +system.cpu.icache.replacements 8405 # number of replacements +system.cpu.icache.tagsinuse 1669.043453 # Cycle average of tags in use +system.cpu.icache.total_refs 405395000 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10125 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 40039.012346 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1668.126238 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.814515 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.814515 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 401722811 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 401722811 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 401722811 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 401722811 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 401722811 # number of overall hits -system.cpu.icache.overall_hits::total 401722811 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11346 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11346 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11346 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11346 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11346 # number of overall misses -system.cpu.icache.overall_misses::total 11346 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 190399000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 190399000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 190399000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 190399000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 190399000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 190399000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 401734157 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 401734157 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 401734157 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 401734157 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 401734157 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 401734157 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000028 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000028 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000028 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000028 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000028 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13295.315582 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13295.315582 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23007.455955 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23007.455955 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23007.455955 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23007.455955 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23007.455955 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23007.455955 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1527641 # 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number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 466730361 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 44 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 44 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 674563676 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 674563676 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 674563676 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 674563676 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004149 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004149 # 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average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38742.754607 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38742.754607 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38742.754607 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 411 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 57 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 45 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 45 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 677525257 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 677525257 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 677525257 # 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miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30753.560758 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30753.560758 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31674.314118 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31674.314118 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31080.770085 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31080.770085 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31080.770085 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31080.770085 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12002 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 95 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 360 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.833333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 57 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.338889 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 95 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 109439 # number of writebacks -system.cpu.dcache.writebacks::total 109439 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 464250 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 464250 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 988187 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 988187 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1452437 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1452437 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1452437 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1452437 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460128 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460128 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71609 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71609 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1531737 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1531737 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1531737 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1531737 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 56005383000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 56005383000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3751591500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3751591500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 59756974500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 59756974500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 59756974500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 59756974500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003148 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003148 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 95938 # number of writebacks +system.cpu.dcache.writebacks::total 95938 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465267 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 465267 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990045 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 990045 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1455312 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1455312 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1455312 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1455312 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460587 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460587 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71641 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71641 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1532228 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1532228 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1532228 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1532228 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35449802000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 35449802000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3677102500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3677102500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 49000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 49000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39126904500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 39126904500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39126904500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 39126904500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003129 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003129 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002271 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002271 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002271 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002271 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 38356.488609 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 38356.488609 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52389.944001 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52389.944001 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39012.555354 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 39012.555354 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39012.555354 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 39012.555354 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.022222 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.022222 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002262 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002262 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002262 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002262 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24270.928058 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24270.928058 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51326.789129 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51326.789129 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 49000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 49000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25535.954505 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25535.954505 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25535.954505 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25535.954505 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480645 # number of replacements -system.cpu.l2cache.tagsinuse 32710.209844 # Cycle average of tags in use -system.cpu.l2cache.total_refs 65998 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1513380 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.043610 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 443402 # number of replacements +system.cpu.l2cache.tagsinuse 32704.051187 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1090376 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 476137 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.290047 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3222.965201 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 44.591861 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29442.652782 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.098357 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001361 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.898518 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.998236 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7145 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 51047 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 58192 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 109439 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 109439 # 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number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1542355 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 10126 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1532229 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1542355 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.276812 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278330 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.278319 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933167 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.933167 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.276812 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.308947 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.308736 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.276812 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.308947 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.308736 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53373.528362 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57679.226370 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 57649.741772 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53205.757408 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53205.757408 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53373.528362 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57047.458902 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 57025.832614 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53373.528362 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57047.458902 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 57025.832614 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 15.526316 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 66898 # number of writebacks -system.cpu.l2cache.writebacks::total 66898 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2995 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1409081 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1412076 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66855 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66855 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2995 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1475936 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1478931 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2995 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1475936 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1478931 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106523142 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 49028505930 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 49135029072 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3470186582 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3470186582 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106523142 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 52498692512 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 52605215654 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106523142 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 52498692512 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 52605215654 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.295365 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.965039 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.960421 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933612 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933612 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.295365 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963570 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.959176 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.295365 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963570 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.959176 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35566.992321 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34794.668248 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34796.306340 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 51906.163817 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 51906.163817 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35566.992321 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35569.762179 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35569.756570 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35566.992321 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35569.762179 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35569.756570 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks +system.cpu.l2cache.writebacks::total 66908 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2803 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406525 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 409328 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66853 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66853 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2803 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 473378 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 476181 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2803 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 473378 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 476181 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 114329941 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18253645467 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18367975408 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2750960138 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2750960138 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114329941 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21004605605 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21118935546 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114329941 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21004605605 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21118935546 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.276812 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278330 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278319 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933167 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933167 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.276812 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308947 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.308736 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.276812 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308947 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.308736 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40788.419907 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44901.655414 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 44873.488762 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41149.389526 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41149.389526 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40788.419907 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44371.740142 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44350.647224 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40788.419907 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44371.740142 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44350.647224 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index a8bcfc08a..c58eb2bea 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.811836 # Number of seconds simulated -sim_ticks 2811836424000 # Number of ticks simulated -final_tick 2811836424000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.769740 # Number of seconds simulated +sim_ticks 2769739533000 # Number of ticks simulated +final_tick 2769739533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1325085 # Simulator instruction rate (inst/s) -host_op_rate 1325085 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1854626286 # Simulator tick rate (ticks/s) -host_mem_usage 228472 # Number of bytes of host memory used -host_seconds 1516.12 # Real time elapsed on the host +host_inst_rate 1761560 # Simulator instruction rate (inst/s) +host_op_rate 1761559 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2428616742 # Simulator tick rate (ticks/s) +host_mem_usage 226024 # Number of bytes of host memory used +host_seconds 1140.46 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated sim_ops 2008987605 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 152128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94417856 # Number of bytes read from this memory -system.physmem.bytes_read::total 94569984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 152128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 152128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4281472 # Number of bytes written to this memory -system.physmem.bytes_written::total 4281472 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2377 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1475279 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1477656 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 54103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 33578716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33632818 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 54103 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 54103 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1522660 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1522660 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1522660 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 54103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 33578716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 35155479 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30284544 # Number of bytes read from this memory +system.physmem.bytes_read::total 30422336 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 137792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 137792 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory +system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2153 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 473196 # Number of read requests responded to by this memory +system.physmem.num_reads::total 475349 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 49749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10934077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10983826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 49749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 49749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1546034 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1546034 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1546034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 49749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10934077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12529860 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 5623672848 # number of cpu cycles simulated +system.cpu.numCycles 5539479066 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2008987605 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 722298387 # nu system.cpu.num_load_insts 511488910 # Number of load instructions system.cpu.num_store_insts 210809477 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5623672848 # Number of busy cycles +system.cpu.num_busy_cycles 5539479066 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 9046 # number of replacements -system.cpu.icache.tagsinuse 1478.427768 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1478.418050 # Cycle average of tags in use system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1478.427768 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.721889 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.721889 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.721884 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 10596 # n system.cpu.icache.demand_misses::total 10596 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 10596 # number of overall misses system.cpu.icache.overall_misses::total 10596 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 237582000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 237582000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 237582000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 237582000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 237582000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 237582000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 228174000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 228174000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 228174000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 228174000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 228174000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 228174000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2009421071 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2009421071 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2009421071 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22421.857305 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22421.857305 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22421.857305 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22421.857305 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22421.857305 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22421.857305 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21533.975085 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21533.975085 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21533.975085 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21533.975085 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21533.975085 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21533.975085 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10596 system.cpu.icache.demand_mshr_misses::total 10596 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10596 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10596 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216390000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 216390000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 216390000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 216390000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216390000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 216390000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 206982000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 206982000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 206982000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 206982000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 206982000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 206982000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20421.857305 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20421.857305 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20421.857305 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19533.975085 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19533.975085 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1526048 # number of replacements -system.cpu.dcache.tagsinuse 4095.209846 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.197836 # Cycle average of tags in use system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.209846 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999807 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999807 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999804 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 1530144 # n system.cpu.dcache.demand_misses::total 1530144 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1530144 # number of overall misses system.cpu.dcache.overall_misses::total 1530144 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 78109548000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 78109548000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36022065000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36022065000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 3744042000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 3744042000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 81853590000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 81853590000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 81853590000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 81853590000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39766107000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39766107000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39766107000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39766107000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 511070026 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 511070026 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002120 system.cpu.dcache.demand_miss_rate::total 0.002120 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002120 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002120 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53566.024227 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53566.024227 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24703.238668 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24703.238668 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52035.273516 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 52035.273516 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53494.043698 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53494.043698 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53494.043698 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53494.043698 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25988.473634 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25988.473634 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25988.473634 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25988.473634 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 109771 # number of writebacks -system.cpu.dcache.writebacks::total 109771 # number of writebacks +system.cpu.dcache.writebacks::writebacks 96129 # number of writebacks +system.cpu.dcache.writebacks::total 96129 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1458192 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1458192 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71952 # number of WriteReq MSHR misses @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1530144 system.cpu.dcache.demand_mshr_misses::total 1530144 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1530144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1530144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75193164000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75193164000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33105681000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33105681000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600138000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600138000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78793302000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 78793302000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78793302000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 78793302000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36705819000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 36705819000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36705819000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36705819000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000341 # mshr miss rate for WriteReq accesses @@ -258,68 +258,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002120 system.cpu.dcache.demand_mshr_miss_rate::total 0.002120 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002120 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51566.024227 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51566.024227 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22703.238668 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22703.238668 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51494.043698 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51494.043698 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51494.043698 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51494.043698 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1479705 # number of replacements -system.cpu.l2cache.tagsinuse 32704.499819 # Cycle average of tags in use -system.cpu.l2cache.total_refs 65761 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1512436 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.043480 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 442570 # number of replacements +system.cpu.l2cache.tagsinuse 32706.854192 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1089464 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 475302 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.292151 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3254.482584 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 33.474832 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29416.542403 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.099319 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001022 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.897722 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.998062 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 8219 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 49786 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 58005 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 109771 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 109771 # number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 1300.510334 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 26.518402 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31379.825456 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.039688 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000809 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.957636 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.998134 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 8443 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1051869 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1060312 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 96129 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 96129 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 5079 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 5079 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8219 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 54865 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 63084 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8219 # 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number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 76714508000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 76838112000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 123604000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 76714508000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 76838112000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 111956000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 24606195000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24718151000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 111956000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 24606195000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24718151000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 10596 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1458192 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1468788 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 109771 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 109771 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 96129 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 96129 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 71952 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 71952 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 10596 # number of demand (read+write) accesses @@ -328,28 +328,28 @@ system.cpu.l2cache.demand_accesses::total 1540740 # n system.cpu.l2cache.overall_accesses::cpu.inst 10596 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1530144 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1540740 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.224330 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.965858 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.960508 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.203190 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278648 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.278104 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.929411 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.929411 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.224330 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.964144 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.959056 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.224330 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.964144 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.959056 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.203190 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.309249 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.308520 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.203190 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.309249 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.308520 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.007383 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.007344 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.006340 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.006311 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.006340 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.006311 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -358,52 +358,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 66898 # number of writebacks -system.cpu.l2cache.writebacks::total 66898 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2377 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1408406 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1410783 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks +system.cpu.l2cache.writebacks::total 66908 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2153 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406323 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 408476 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66873 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66873 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2377 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1475279 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1477656 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2377 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1475279 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1477656 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 95080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56336240000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56431320000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2153 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 473196 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 475349 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2153 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 473196 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 475349 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 86120000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16252923000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16339043000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2674920000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2674920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 95080000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59011160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 59106240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 95080000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59011160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 59106240000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.965858 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.960508 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 86120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18927843000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19013963000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 86120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18927843000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19013963000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.203190 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278648 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278104 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.929411 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.929411 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964144 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.959056 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964144 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.959056 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.203190 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309249 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.308520 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.203190 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309249 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.308520 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.007383 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.007344 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.006340 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.006311 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.006340 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.006311 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 1e57970d1..ac8776e10 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.659992 # Number of seconds simulated -sim_ticks 659991928000 # Number of ticks simulated -final_tick 659991928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.635788 # Number of seconds simulated +sim_ticks 635788224000 # Number of ticks simulated +final_tick 635788224000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102750 # Simulator instruction rate (inst/s) -host_op_rate 139931 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48985343 # Simulator tick rate (ticks/s) -host_mem_usage 254632 # Number of bytes of host memory used -host_seconds 13473.25 # Real time elapsed on the host -sim_insts 1384374560 # Number of instructions simulated -sim_ops 1885329312 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 198528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94517696 # Number of bytes read from this memory -system.physmem.bytes_read::total 94716224 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 198528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 198528 # Number of instructions bytes read from this memory +host_inst_rate 107590 # Simulator instruction rate (inst/s) +host_op_rate 146523 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49411882 # Simulator tick rate (ticks/s) +host_mem_usage 254872 # Number of bytes of host memory used +host_seconds 12867.11 # Real time elapsed on the host +sim_insts 1384378595 # Number of instructions simulated +sim_ops 1885333347 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 160512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30246144 # Number of bytes read from this memory +system.physmem.bytes_read::total 30406656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 160512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 160512 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3102 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1476839 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1479941 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2508 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 472596 # Number of read requests responded to by this memory +system.physmem.num_reads::total 475104 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 300804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 143210382 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 143511185 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 300804 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 300804 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6409581 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6409581 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6409581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 300804 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 143210382 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 149920767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1479941 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 252461 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47572671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47825132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 252461 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 252461 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6653587 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6653587 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6653587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 252461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47572671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54478719 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 475105 # Total number of read requests seen system.physmem.writeReqs 66098 # Total number of write requests seen -system.physmem.cpureqs 1550203 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 94716224 # Total number of bytes read from memory +system.physmem.cpureqs 545524 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30406656 # Total number of bytes read from memory system.physmem.bytesWritten 4230272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 94716224 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30406656 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 4222 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4164 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 92954 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 91941 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 92050 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 91689 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 92209 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 92061 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 92149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 92666 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 91875 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 92213 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 92439 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 92957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 92247 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 91863 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 92572 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 91834 # Track reads on a per bank basis +system.physmem.servicedByWrQ 162 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4321 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 29681 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29709 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29623 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29546 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29672 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 29640 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29628 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29737 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29753 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29773 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29801 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29855 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29675 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29602 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29637 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29611 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 4129 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 4141 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 4096 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 4108 # Tr system.physmem.perBankWrReqs::15 4128 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 659991863500 # Total gap between requests +system.physmem.totGap 635788203500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1479941 # Categorize read packet sizes +system.physmem.readPktSize::6 475105 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -102,18 +102,18 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4164 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4321 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1408404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 407840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 312 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see @@ -138,7 +138,7 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2874 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 2874 # What write queue length does an incoming req see @@ -161,7 +161,7 @@ system.physmem.wrQLenPdf::19 2873 # Wh system.physmem.wrQLenPdf::20 2873 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 2873 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 2873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -171,27 +171,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 5597502027 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 50332290027 # Sum of mem lat for all requests -system.physmem.totBusLat 5902876000 # Total cycles spent in databus access -system.physmem.totBankLat 38831912000 # Total cycles spent in bank access -system.physmem.avgQLat 3793.07 # Average queueing delay per request -system.physmem.avgBankLat 26313.89 # Average bank access latency per request +system.physmem.totQLat 2296699471 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 17086173471 # Sum of mem lat for all requests +system.physmem.totBusLat 1899772000 # Total cycles spent in databus access +system.physmem.totBankLat 12889702000 # Total cycles spent in bank access +system.physmem.avgQLat 4835.74 # Average queueing delay per request +system.physmem.avgBankLat 27139.47 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 34106.96 # Average memory access latency -system.physmem.avgRdBW 143.51 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 6.41 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 143.51 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.41 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 35975.21 # Average memory access latency +system.physmem.avgRdBW 47.83 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 6.65 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 47.83 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.65 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.94 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.08 # Average read queue length over time -system.physmem.avgWrQLen 14.18 # Average write queue length over time -system.physmem.readRowHits 809039 # Number of row buffer hits during reads -system.physmem.writeRowHits 36662 # Number of row buffer hits during writes -system.physmem.readRowHitRate 54.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 55.47 # Row buffer hit rate for writes -system.physmem.avgGap 426892.12 # Average gap between requests +system.physmem.busUtil 0.34 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.03 # Average read queue length over time +system.physmem.avgWrQLen 17.42 # Average write queue length over time +system.physmem.readRowHits 249227 # Number of row buffer hits during reads +system.physmem.writeRowHits 48069 # Number of row buffer hits during writes +system.physmem.readRowHitRate 52.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.72 # Row buffer hit rate for writes +system.physmem.avgGap 1174768.44 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,576 +235,577 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1319983857 # number of cpu cycles simulated +system.cpu.numCycles 1271576449 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 454350981 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 358310478 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 33373061 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 312072233 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 240275028 # Number of BTB hits +system.cpu.BPredUnit.lookups 450228409 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 355532784 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 33221025 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 286250905 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 237054856 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 53876645 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2808673 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 374001286 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2331861224 # Number of instructions fetch has processed -system.cpu.fetch.Branches 454350981 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 294151673 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 622796021 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 170528608 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 135818762 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2051 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 24217 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 352463772 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11980006 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1269746213 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.542801 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.164977 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 53630453 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2814194 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 368782120 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2317566621 # Number of instructions fetch has processed +system.cpu.fetch.Branches 450228409 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 290685309 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 618187609 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 167802769 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 122950545 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2044 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 34033 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 120 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 346967374 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10833079 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1244485983 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.575716 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.174798 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 646995456 50.95% 50.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 44687712 3.52% 54.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 102379693 8.06% 62.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 59922071 4.72% 67.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 74129472 5.84% 73.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 45582835 3.59% 76.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31361893 2.47% 79.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30601811 2.41% 81.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 234085270 18.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 626344117 50.33% 50.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 45317842 3.64% 53.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101227769 8.13% 62.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 59470859 4.78% 66.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 73017121 5.87% 72.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 44727211 3.59% 76.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30024154 2.41% 78.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31448495 2.53% 81.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 232908415 18.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1269746213 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.344209 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.766583 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 425403268 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 107718588 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 581478902 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18055452 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 137090003 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 51078179 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 15137 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3127640414 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 28961 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 137090003 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 461511464 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39177126 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 530700 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 561763722 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 69673198 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3042064401 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 391 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4490697 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 56029467 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 2572 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2999547883 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14489457877 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13880825981 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 608631896 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993146442 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1006401441 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 29463 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25504 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 180658895 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 975543094 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 514319343 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 34765547 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 38827815 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2864053634 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 32821 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2484775177 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 12535683 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 966091505 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2435627475 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 10643 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1269746213 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.956907 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.886378 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1244485983 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.354071 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.822593 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 419135073 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95311788 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 577111124 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18421558 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 134506440 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 50263790 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 26327 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3103411757 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 60284 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 134506440 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 455352486 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 27182944 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 495803 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 558181591 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 68766719 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3020461835 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 80 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1786182 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 58542729 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2987223490 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14381793689 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13781741718 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 600051971 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993152898 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 994070592 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 26249 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23484 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 177920569 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 971527729 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 505697139 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 29364054 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 38323451 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2844663565 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34202 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2471693501 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 7154025 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 946732451 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2394075214 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 11217 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1244485983 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.986116 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.887022 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 414113290 32.61% 32.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 194811826 15.34% 47.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 206120235 16.23% 64.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 171548762 13.51% 77.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 130841431 10.30% 88.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 97116191 7.65% 95.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37554058 2.96% 98.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12317792 0.97% 99.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5322628 0.42% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 394145382 31.67% 31.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 193214413 15.53% 47.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 204405304 16.42% 63.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 171173190 13.75% 77.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 129740055 10.43% 87.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 97310600 7.82% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 36398713 2.92% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12543196 1.01% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5555130 0.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1269746213 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1244485983 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 947301 1.02% 1.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24145 0.03% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 56191268 60.42% 61.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 35841535 38.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 746380 0.82% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24393 0.03% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55867065 61.34% 62.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 34441237 37.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1133457764 45.62% 45.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11237396 0.45% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876496 0.28% 46.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5506177 0.22% 46.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23536328 0.95% 47.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 838863420 33.76% 81.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 463922306 18.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1129092447 45.68% 45.68% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11228574 0.45% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876479 0.28% 46.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5501982 0.22% 46.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23586280 0.95% 47.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 837187213 33.87% 81.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 456845236 18.48% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2484775177 # Type of FU issued -system.cpu.iq.rate 1.882428 # Inst issue rate -system.cpu.iq.fu_busy_cnt 93004249 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.037430 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6215984950 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3740236476 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2293829225 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 128851549 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 90009348 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 59026271 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2510712861 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 67066565 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 78532237 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2471693501 # Type of FU issued +system.cpu.iq.rate 1.943803 # Inst issue rate +system.cpu.iq.fu_busy_cnt 91079075 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.036849 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6158633993 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3704145010 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2281572785 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 127472092 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 87353789 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 58523777 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2496546302 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 66226274 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 80772254 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 344155119 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5694 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1300004 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 237323252 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 340138947 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4271 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 411099 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 228700241 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 284 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 137090003 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 17084434 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1439762 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2864100864 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 11154453 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 975543094 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 514319343 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22441 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1430096 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1153 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1300004 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 35278606 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1697024 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 36975630 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2406030122 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 793312488 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 78745055 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 134506440 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8643138 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 547079 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2844711818 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 10610498 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 971527729 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 505697139 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23185 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 540297 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2527 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 411099 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 34712988 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1840552 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 36553540 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2395281486 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 793221583 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 76412015 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 14409 # number of nop insts executed -system.cpu.iew.exec_refs 1235149676 # number of memory reference insts executed -system.cpu.iew.exec_branches 329779468 # Number of branches executed -system.cpu.iew.exec_stores 441837188 # Number of stores executed -system.cpu.iew.exec_rate 1.822772 # Inst execution rate -system.cpu.iew.wb_sent 2378266547 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2352855496 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1358943525 # num instructions producing a value -system.cpu.iew.wb_consumers 2560958188 # num instructions consuming a value +system.cpu.iew.exec_nop 14051 # number of nop insts executed +system.cpu.iew.exec_refs 1229345389 # number of memory reference insts executed +system.cpu.iew.exec_branches 327128098 # Number of branches executed +system.cpu.iew.exec_stores 436123806 # Number of stores executed +system.cpu.iew.exec_rate 1.883710 # Inst execution rate +system.cpu.iew.wb_sent 2368179118 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2340096562 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1354502475 # num instructions producing a value +system.cpu.iew.wb_consumers 2541864992 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.782488 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.530639 # average fanout of values written-back +system.cpu.iew.wb_rate 1.840311 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.532877 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 978761117 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 22178 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 33359188 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1132656212 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.664530 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.366367 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 959367728 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 22985 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 33197953 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1109979545 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.698540 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.378671 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 484847147 42.81% 42.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 300235204 26.51% 69.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 89818902 7.93% 77.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 73190759 6.46% 83.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 44951546 3.97% 87.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23093029 2.04% 89.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15848859 1.40% 91.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9835568 0.87% 91.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 90835198 8.02% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 463287159 41.74% 41.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 297974077 26.85% 68.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 91457957 8.24% 76.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 72253905 6.51% 83.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 45208298 4.07% 87.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23225084 2.09% 89.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15854658 1.43% 90.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10141159 0.91% 91.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 90577248 8.16% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1132656212 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384385576 # Number of instructions committed -system.cpu.commit.committedOps 1885340328 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1109979545 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1384389611 # Number of instructions committed +system.cpu.commit.committedOps 1885344363 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908384066 # Number of memory references committed -system.cpu.commit.loads 631387975 # Number of loads committed +system.cpu.commit.refs 908385680 # Number of memory references committed +system.cpu.commit.loads 631388782 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 299635189 # Number of branches committed +system.cpu.commit.branches 299635996 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653702043 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653705271 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 90835198 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 90577248 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3905904114 # The number of ROB reads -system.cpu.rob.rob_writes 5865307964 # The number of ROB writes -system.cpu.timesIdled 1232544 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 50237644 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384374560 # Number of Instructions Simulated -system.cpu.committedOps 1885329312 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1384374560 # Number of Instructions Simulated -system.cpu.cpi 0.953488 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.953488 # CPI: Total CPI of All Threads -system.cpu.ipc 1.048781 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.048781 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11951457171 # number of integer regfile reads -system.cpu.int_regfile_writes 2254061534 # number of integer regfile writes -system.cpu.fp_regfile_reads 71109797 # number of floating regfile reads -system.cpu.fp_regfile_writes 50119198 # number of floating regfile writes -system.cpu.misc_regfile_reads 3727888158 # number of misc regfile reads -system.cpu.misc_regfile_writes 13774490 # number of misc regfile writes -system.cpu.icache.replacements 23076 # number of replacements -system.cpu.icache.tagsinuse 1653.132974 # Cycle average of tags in use -system.cpu.icache.total_refs 352429997 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 24765 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14230.971007 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 3864096043 # The number of ROB reads +system.cpu.rob.rob_writes 5823945497 # The number of ROB writes +system.cpu.timesIdled 351641 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27090466 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1384378595 # Number of Instructions Simulated +system.cpu.committedOps 1885333347 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1384378595 # Number of Instructions Simulated +system.cpu.cpi 0.918518 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.918518 # CPI: Total CPI of All Threads +system.cpu.ipc 1.088710 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.088710 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11907054979 # number of integer regfile reads +system.cpu.int_regfile_writes 2251695031 # number of integer regfile writes +system.cpu.fp_regfile_reads 70501707 # number of floating regfile reads +system.cpu.fp_regfile_writes 50326111 # number of floating regfile writes +system.cpu.misc_regfile_reads 3707678526 # number of misc regfile reads +system.cpu.misc_regfile_writes 13776104 # number of misc regfile writes +system.cpu.icache.replacements 23916 # number of replacements +system.cpu.icache.tagsinuse 1661.487549 # Cycle average of tags in use +system.cpu.icache.total_refs 346930644 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 25614 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13544.571094 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1653.132974 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.807194 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.807194 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 352434103 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 352434103 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 352434103 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 352434103 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 352434103 # number of overall hits -system.cpu.icache.overall_hits::total 352434103 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 29669 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 29669 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 29669 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 29669 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 29669 # number of overall misses -system.cpu.icache.overall_misses::total 29669 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 256567500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 256567500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 256567500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 256567500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 256567500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 256567500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 352463772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 352463772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 352463772 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 352463772 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 352463772 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 352463772 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000084 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000084 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000084 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000084 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000084 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8647.662543 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8647.662543 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8647.662543 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8647.662543 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8647.662543 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8647.662543 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1661.487549 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.811273 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.811273 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 346934721 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 346934721 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 346934721 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 346934721 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 346934721 # number of overall hits +system.cpu.icache.overall_hits::total 346934721 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 32652 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 32652 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 32652 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 32652 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 32652 # number of overall misses +system.cpu.icache.overall_misses::total 32652 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 492196499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 492196499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 492196499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 492196499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 492196499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 492196499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 346967373 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 346967373 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 346967373 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 346967373 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 346967373 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 346967373 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000094 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000094 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000094 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000094 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000094 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000094 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15074.007687 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15074.007687 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15074.007687 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15074.007687 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15074.007687 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15074.007687 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1459 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 35 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 41.685714 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 738 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 738 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 738 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 738 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 738 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 738 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28931 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 28931 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 28931 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 28931 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 28931 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 28931 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 178433000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 178433000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 178433000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 178433000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 178433000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 178433000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000082 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000082 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000082 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6167.536552 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6167.536552 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6167.536552 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6167.536552 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6167.536552 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6167.536552 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2714 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2714 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2714 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2714 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2714 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2714 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 29938 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 29938 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 29938 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 29938 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 29938 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 29938 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 396628999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 396628999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 396628999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 396628999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 396628999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 396628999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13248.346550 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13248.346550 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13248.346550 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13248.346550 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13248.346550 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13248.346550 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1533235 # number of replacements -system.cpu.dcache.tagsinuse 4094.869938 # Cycle average of tags in use -system.cpu.dcache.total_refs 976399177 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1537331 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 635.126188 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 278705000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.869938 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999724 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999724 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 700249991 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 700249991 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276118441 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276118441 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11312 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11312 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 10779 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 10779 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 976368432 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 976368432 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 976368432 # number of overall hits -system.cpu.dcache.overall_hits::total 976368432 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2072491 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2072491 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 817237 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 817237 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 10 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 10 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2889728 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2889728 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2889728 # number of overall misses -system.cpu.dcache.overall_misses::total 2889728 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 84515499000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 84515499000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31029320000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31029320000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 296000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 296000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 115544819000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 115544819000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 115544819000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 115544819000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 702322482 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 702322482 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1533079 # number of replacements +system.cpu.dcache.tagsinuse 4094.602102 # Cycle average of tags in use +system.cpu.dcache.total_refs 974126836 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1537175 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 633.712385 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 342496000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.602102 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999659 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999659 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 697989238 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 697989238 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276101323 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276101323 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 12267 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 12267 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11586 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11586 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 974090561 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 974090561 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 974090561 # number of overall hits +system.cpu.dcache.overall_hits::total 974090561 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2001936 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2001936 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 834355 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 834355 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2836291 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2836291 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2836291 # number of overall misses +system.cpu.dcache.overall_misses::total 2836291 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 68815075500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 68815075500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 39938491970 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 39938491970 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 99000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 99000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 108753567470 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 108753567470 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 108753567470 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 108753567470 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 699991174 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 699991174 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11322 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11322 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 10779 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 10779 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 979258160 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 979258160 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 979258160 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 979258160 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002951 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002951 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002951 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002951 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000883 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000883 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002951 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002951 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002951 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002951 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40779.669972 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40779.669972 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37968.569705 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37968.569705 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 29600 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 29600 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39984.669491 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39984.669491 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39984.669491 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39984.669491 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 86 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 21.500000 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12269 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 12269 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11586 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11586 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 976926852 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 976926852 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 976926852 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 976926852 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002860 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002860 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003013 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003013 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000163 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000163 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002903 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002903 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002903 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002903 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34374.263463 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34374.263463 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47867.504803 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47867.504803 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38343.585856 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38343.585856 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38343.585856 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38343.585856 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1801 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 752 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 60 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 85 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.016667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8.847059 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 108671 # number of writebacks -system.cpu.dcache.writebacks::total 108671 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 607721 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 607721 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 740509 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 740509 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 10 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 10 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1348230 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1348230 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1348230 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1348230 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464770 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464770 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76728 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76728 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541498 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541498 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541498 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541498 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 56538138500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 56538138500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2635948000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2635948000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 59174086500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 59174086500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 59174086500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 59174086500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002086 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002086 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001574 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001574 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001574 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001574 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 38598.645862 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 38598.645862 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34354.446877 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34354.446877 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38387.391031 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 38387.391031 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38387.391031 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 38387.391031 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 96247 # number of writebacks +system.cpu.dcache.writebacks::total 96247 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 537314 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 537314 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757477 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 757477 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1294791 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1294791 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1294791 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1294791 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464622 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464622 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76878 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76878 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541500 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541500 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541500 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541500 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36879858500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36879858500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3477356000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3477356000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40357214500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 40357214500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40357214500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 40357214500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002092 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002092 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001578 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001578 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001578 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001578 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25180.461921 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25180.461921 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45232.134031 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45232.134031 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26180.482971 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26180.482971 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26180.482971 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26180.482971 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480138 # number of replacements -system.cpu.l2cache.tagsinuse 32697.181297 # Cycle average of tags in use -system.cpu.l2cache.total_refs 84298 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1512881 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.055720 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 442324 # number of replacements +system.cpu.l2cache.tagsinuse 32688.980204 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1110893 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 475069 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.338382 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43223820 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43223820 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2389121519 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2389121519 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 99443391 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22079457683 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22178901074 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 99443391 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22079457683 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22178901074 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.097950 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277558 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274471 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999306 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999306 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910742 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910742 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.097950 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307444 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.304011 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.097950 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307444 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.304011 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39634.671582 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48436.566558 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 48382.575123 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10003.198334 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10003.198334 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36156.080980 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36156.080980 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39634.671582 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46719.518750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 46682.104112 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39634.671582 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46719.518750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 46682.104112 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 1b9ad306d..ac5d108eb 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.368273 # Number of seconds simulated -sim_ticks 2368273403000 # Number of ticks simulated -final_tick 2368273403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.326119 # Number of seconds simulated +sim_ticks 2326118592000 # Number of ticks simulated +final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 821983 # Simulator instruction rate (inst/s) -host_op_rate 1115078 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1408999350 # Simulator tick rate (ticks/s) -host_mem_usage 241788 # Number of bytes of host memory used -host_seconds 1680.82 # Real time elapsed on the host +host_inst_rate 541548 # Simulator instruction rate (inst/s) +host_op_rate 734649 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 911769830 # Simulator tick rate (ticks/s) +host_mem_usage 240408 # Number of bytes of host memory used +host_seconds 2551.21 # Real time elapsed on the host sim_insts 1381604339 # Number of instructions simulated sim_ops 1874244941 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 144448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94437440 # Number of bytes read from this memory -system.physmem.bytes_read::total 94581888 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 144448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 144448 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 113472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30232512 # Number of bytes read from this memory +system.physmem.bytes_read::total 30345984 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 113472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 113472 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2257 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1475585 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1477842 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1773 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 472383 # Number of read requests responded to by this memory +system.physmem.num_reads::total 474156 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 60993 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39876072 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 39937065 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 60993 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 60993 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1786253 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1786253 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1786253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 60993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39876072 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41723318 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 48782 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12996978 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13045760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 48782 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 48782 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1818624 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1818624 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1818624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 48782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12996978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14864384 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 4736546806 # number of cpu cycles simulated +system.cpu.numCycles 4652237184 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1381604339 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 908382479 # nu system.cpu.num_load_insts 631387181 # Number of load instructions system.cpu.num_store_insts 276995298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4736546806 # Number of busy cycles +system.cpu.num_busy_cycles 4652237184 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 18364 # number of replacements -system.cpu.icache.tagsinuse 1392.329214 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1392.317060 # Cycle average of tags in use system.cpu.icache.total_refs 1390251699 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 70204.095289 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1392.329214 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.679848 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.679848 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.679842 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 19803 # n system.cpu.icache.demand_misses::total 19803 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 19803 # number of overall misses system.cpu.icache.overall_misses::total 19803 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 352238000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 352238000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 352238000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 352238000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 352238000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 352238000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 331911000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 331911000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 331911000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 331911000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 331911000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 331911000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1390271502 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1390271502 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1390271502 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000014 system.cpu.icache.demand_miss_rate::total 0.000014 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000014 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000014 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17787.102964 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17787.102964 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17787.102964 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17787.102964 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17787.102964 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17787.102964 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16760.642327 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16760.642327 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16760.642327 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16760.642327 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16760.642327 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16760.642327 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 19803 system.cpu.icache.demand_mshr_misses::total 19803 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 19803 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 19803 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312632000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 312632000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312632000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 312632000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312632000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 312632000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 292305000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 292305000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 292305000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 292305000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 292305000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 292305000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000014 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15787.102964 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15787.102964 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15787.102964 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15787.102964 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15787.102964 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15787.102964 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14760.642327 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14760.642327 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1529557 # number of replacements -system.cpu.dcache.tagsinuse 4094.965929 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.947189 # Cycle average of tags in use system.cpu.dcache.total_refs 895757408 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 584.067848 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 991199000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.965929 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999748 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999748 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999743 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 1533653 # n system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses system.cpu.dcache.overall_misses::total 1533653 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 78190013000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 78190013000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36055529000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36055529000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 3722046000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 3722046000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 81912059000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 81912059000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 81912059000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 81912059000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39777575000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39777575000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39777575000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39777575000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 620335413 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 620335413 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53522.799723 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53522.799723 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24680.810036 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24680.810036 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51141.055235 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 51141.055235 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53409.773267 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53409.773267 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53409.773267 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53409.773267 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25936.489545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25936.489545 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 109047 # number of writebacks -system.cpu.dcache.writebacks::total 109047 # number of writebacks +system.cpu.dcache.writebacks::writebacks 96257 # number of writebacks +system.cpu.dcache.writebacks::total 96257 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460873 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1460873 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72780 # number of WriteReq MSHR misses @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1533653 system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75268267000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75268267000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33133783000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33133783000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78844753000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 78844753000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78844753000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 78844753000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36710269000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 36710269000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36710269000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36710269000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses @@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51522.799723 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51522.799723 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22680.810036 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22680.810036 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51409.773267 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51409.773267 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51409.773267 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51409.773267 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1478696 # number of replacements -system.cpu.l2cache.tagsinuse 32690.092056 # Cycle average of tags in use -system.cpu.l2cache.total_refs 77413 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1511439 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.051218 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 441378 # number of replacements +system.cpu.l2cache.tagsinuse 32692.891822 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1102614 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 474121 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.325596 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3194.112587 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 32.917167 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29463.062302 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.097477 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001005 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.899141 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997622 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 17546 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 51381 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 68927 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 109047 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 109047 # number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 1298.141733 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 30.233408 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31364.516681 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.039616 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000923 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.957169 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.997708 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 18030 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1054583 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1072613 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 96257 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 96257 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 6687 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 6687 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 17546 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 58068 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 75614 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 17546 # 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number of demand (read+write) accesses @@ -346,28 +346,28 @@ system.cpu.l2cache.demand_accesses::total 1553456 # n system.cpu.l2cache.overall_accesses::cpu.inst 19803 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1533653 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1553456 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113973 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964829 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.953449 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.089532 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278115 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.275592 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908120 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.908120 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113973 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.962137 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.951325 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113973 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.962137 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.951325 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.215330 # average ReadReq miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.089532 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.308012 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.305227 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.089532 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.308012 # 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number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2257 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1475585 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1477842 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 90285000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56379680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56469965000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1773 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 472383 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 474156 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1773 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 472383 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 474156 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70926000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16251600000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16322526000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2643720000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2643720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 90285000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59023400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 59113685000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 90285000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59023400000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 59113685000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964829 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.953449 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70926000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18895320000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18966246000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70926000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18895320000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18966246000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.089532 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278115 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.275592 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908120 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908120 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962137 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.951325 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962137 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.951325 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.215330 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.089532 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308012 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.305227 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.089532 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308012 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.305227 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40003.384095 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.003542 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.014704 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.215330 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40003.384095 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.003383 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.215330 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.012654 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.384095 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.003383 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.012654 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 14d4b21df..e532ddba3 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.046394 # Number of seconds simulated -sim_ticks 46393648500 # Number of ticks simulated -final_tick 46393648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.043596 # Number of seconds simulated +sim_ticks 43595903500 # Number of ticks simulated +final_tick 43595903500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 96549 # Simulator instruction rate (inst/s) -host_op_rate 96549 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50704548 # Simulator tick rate (ticks/s) -host_mem_usage 252684 # Number of bytes of host memory used -host_seconds 914.98 # Real time elapsed on the host +host_inst_rate 146921 # Simulator instruction rate (inst/s) +host_op_rate 146921 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72505010 # Simulator tick rate (ticks/s) +host_mem_usage 252940 # Number of bytes of host memory used +host_seconds 601.28 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 514944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10272704 # Number of bytes read from this memory -system.physmem.bytes_read::total 10787648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 514944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 514944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7422400 # Number of bytes written to this memory -system.physmem.bytes_written::total 7422400 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8046 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 160511 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168557 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115975 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115975 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11099450 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 221424793 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 232524243 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11099450 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11099450 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 159987417 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 159987417 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 159987417 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11099450 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 221424793 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 392511660 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168557 # Total number of read requests seen -system.physmem.writeReqs 115975 # Total number of write requests seen -system.physmem.cpureqs 284532 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10787648 # Total number of bytes read from memory -system.physmem.bytesWritten 7422400 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10787648 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7422400 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 12 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 454912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10138304 # Number of bytes read from this memory +system.physmem.bytes_read::total 10593216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 454912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 454912 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7295808 # Number of bytes written to this memory +system.physmem.bytes_written::total 7295808 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7108 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158411 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165519 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory +system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 10434742 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 232551758 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 242986500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10434742 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10434742 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 167350770 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 167350770 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 167350770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10434742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 232551758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 410337269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165519 # Total number of read requests seen +system.physmem.writeReqs 113997 # Total number of write requests seen +system.physmem.cpureqs 279516 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10593216 # Total number of bytes read from memory +system.physmem.bytesWritten 7295808 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 10593216 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10983 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10544 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10882 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10471 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10499 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10300 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10074 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10523 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10483 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10797 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10531 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10543 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 10030 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10827 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10322 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7511 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7019 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7391 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7077 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7441 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7201 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7286 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6969 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7287 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6971 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7555 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7177 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7254 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7052 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7484 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7300 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 10672 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10220 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10695 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10332 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10219 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 10232 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 9969 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10371 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10218 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10609 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10332 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10345 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 9920 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10624 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10240 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7408 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6899 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7248 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6949 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7300 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7039 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7150 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6837 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7210 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6879 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7379 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7080 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7117 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6935 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7374 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7193 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 46393600000 # Total gap between requests +system.physmem.totGap 43595883500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 168557 # Categorize read packet sizes +system.physmem.readPktSize::6 165519 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 115975 # categorize write packet sizes +system.physmem.writePktSize::6 113997 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 162958 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1045 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 71904 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17020 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -138,80 +138,80 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4950 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1271098054 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4666794054 # Sum of mem lat for all requests -system.physmem.totBusLat 674180000 # Total cycles spent in databus access -system.physmem.totBankLat 2721516000 # Total cycles spent in bank access -system.physmem.avgQLat 7541.59 # Average queueing delay per request -system.physmem.avgBankLat 16147.12 # Average bank access latency per request +system.physmem.totQLat 9323896604 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11720942604 # Sum of mem lat for all requests +system.physmem.totBusLat 662068000 # Total cycles spent in databus access +system.physmem.totBankLat 1734978000 # Total cycles spent in bank access +system.physmem.avgQLat 56331.96 # Average queueing delay per request +system.physmem.avgBankLat 10482.17 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27688.71 # Average memory access latency -system.physmem.avgRdBW 232.52 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 159.99 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 232.52 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 159.99 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 70814.13 # Average memory access latency +system.physmem.avgRdBW 242.99 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 167.35 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 242.99 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 167.35 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.45 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.10 # Average read queue length over time -system.physmem.avgWrQLen 10.39 # Average write queue length over time -system.physmem.readRowHits 152922 # Number of row buffer hits during reads -system.physmem.writeRowHits 84722 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.73 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.05 # Row buffer hit rate for writes -system.physmem.avgGap 163052.31 # Average gap between requests +system.physmem.busUtil 2.56 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.27 # Average read queue length over time +system.physmem.avgWrQLen 10.36 # Average write queue length over time +system.physmem.readRowHits 151893 # Number of row buffer hits during reads +system.physmem.writeRowHits 41557 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.77 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 36.45 # Row buffer hit rate for writes +system.physmem.avgGap 155969.19 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277224 # DTB read hits +system.cpu.dtb.read_hits 20277538 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367372 # DTB read accesses -system.cpu.dtb.write_hits 14736801 # DTB write hits +system.cpu.dtb.read_accesses 20367686 # DTB read accesses +system.cpu.dtb.write_hits 14728672 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14744053 # DTB write accesses -system.cpu.dtb.data_hits 35014025 # DTB hits +system.cpu.dtb.write_accesses 14735924 # DTB write accesses +system.cpu.dtb.data_hits 35006210 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35111425 # DTB accesses -system.cpu.itb.fetch_hits 12475425 # ITB hits -system.cpu.itb.fetch_misses 12954 # ITB misses +system.cpu.dtb.data_accesses 35103610 # DTB accesses +system.cpu.itb.fetch_hits 12476759 # ITB hits +system.cpu.itb.fetch_misses 12943 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12488379 # ITB accesses +system.cpu.itb.fetch_accesses 12489702 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 92787298 # number of cpu cycles simulated +system.cpu.numCycles 87191808 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 18828887 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 12440846 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 5023695 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 16217673 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 5047073 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 1660946 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 1031 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 31.120821 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 8474385 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10354502 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74331965 # Number of Reads from Int. Register File +system.cpu.branch_predictor.lookups 18827150 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 12439421 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 5024981 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 16201522 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 5047120 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 1660945 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.RASInCorrect 1030 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 31.152135 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 8476186 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10350964 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74333119 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126651215 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 65206 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126652369 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 65259 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 292836 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14119774 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35064022 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4679410 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 233785 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4913195 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 8859107 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 35.674465 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44776036 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 292889 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14121677 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35064639 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4680318 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 234163 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4914481 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 8857790 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 35.683882 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44776328 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 78069956 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77836216 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 311324 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 22508104 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 70279194 # Number of cycles cpu stages are processed. -system.cpu.activity 75.742257 # Percentage of cycles cpu is active +system.cpu.timesIdled 230753 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16919077 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 70272731 # Number of cycles cpu stages are processed. +system.cpu.activity 80.595566 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -272,144 +272,144 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 1.050335 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.986995 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.050335 # CPI: Total CPI of All Threads -system.cpu.ipc 0.952077 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.986995 # CPI: Total CPI of All Threads +system.cpu.ipc 1.013176 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.952077 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 39364116 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 53423182 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 57.575965 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 50132225 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42655073 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 45.970811 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 49662532 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43124766 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 46.477015 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 70666607 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22120691 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 23.840215 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 46683402 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46103896 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 49.687723 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 85246 # number of replacements -system.cpu.icache.tagsinuse 1892.367381 # Cycle average of tags in use -system.cpu.icache.total_refs 12357191 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 87292 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 141.561552 # Average number of references to valid blocks. +system.cpu.ipc_total 1.013176 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 33768817 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 53422991 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 61.270654 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 44539685 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42652123 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 48.917581 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 44072021 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43119787 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.453943 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65076368 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22115440 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 25.364126 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 41085926 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46105882 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 52.878686 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 85196 # number of replacements +system.cpu.icache.tagsinuse 1908.917223 # Cycle average of tags in use +system.cpu.icache.total_refs 12358549 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 87242 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 141.658249 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1892.367381 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.924008 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.924008 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12357191 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12357191 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12357191 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12357191 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12357191 # number of overall hits -system.cpu.icache.overall_hits::total 12357191 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 118187 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 118187 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 118187 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 118187 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 118187 # number of overall misses -system.cpu.icache.overall_misses::total 118187 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1883931500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1883931500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1883931500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1883931500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1883931500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1883931500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12475378 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12475378 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12475378 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12475378 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12475378 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12475378 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1908.917223 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.932088 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.932088 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12358549 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12358549 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12358549 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12358549 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12358549 # number of overall hits +system.cpu.icache.overall_hits::total 12358549 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 118203 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 118203 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 118203 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 118203 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 118203 # number of overall misses +system.cpu.icache.overall_misses::total 118203 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1846898500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1846898500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1846898500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1846898500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1846898500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1846898500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12476752 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12476752 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12476752 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12476752 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12476752 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12476752 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009474 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.009474 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.009474 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.009474 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.009474 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.009474 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15940.259927 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15940.259927 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15940.259927 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15940.259927 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15940.259927 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15940.259927 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1882 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 108 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 17.425926 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15624.802247 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15624.802247 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15624.802247 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15624.802247 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15624.802247 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15624.802247 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 306 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 26 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 24 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 12.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 6.500000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1292347500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1292347500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1292347500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1292347500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006992 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006992 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006992 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006992 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006992 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006992 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14813.363976 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14813.363976 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14813.363976 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14813.363976 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14813.363976 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14813.363976 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200251 # number of replacements -system.cpu.dcache.tagsinuse 4074.773035 # Cycle average of tags in use -system.cpu.dcache.total_refs 34126001 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4078.664341 # Cycle average of tags in use +system.cpu.dcache.total_refs 33754987 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.000254 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 420616000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4074.773035 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994818 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994818 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180529 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180529 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13945472 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13945472 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34126001 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34126001 # 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number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 32880134000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 36538436500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36538436500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 36538436500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36538436500 # number of overall miss cycles +system.cpu.dcache.avg_refs 165.184647 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 249990000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4078.664341 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995768 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995768 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180268 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180268 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574719 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574719 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 33754987 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33754987 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33754987 # number of overall hits +system.cpu.dcache.overall_hits::total 33754987 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96370 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96370 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1038658 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1038658 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1135028 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1135028 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1135028 # number of overall misses +system.cpu.dcache.overall_misses::total 1135028 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3954988500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3954988500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 91520281000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 91520281000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 95475269500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 95475269500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 95475269500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 95475269500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -418,40 +418,40 @@ system.cpu.dcache.demand_accesses::cpu.data 34890015 # system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004740 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004740 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045705 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045705 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021898 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.021898 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021898 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.021898 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38064.099096 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38064.099096 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49228.758581 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 49228.758581 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47824.302303 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47824.302303 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47824.302303 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47824.302303 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1355 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 11803841 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 124100 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 271 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 95.115560 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071076 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071076 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.032532 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032532 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032532 # 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number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 116295 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.098104 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 397 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 165814 # number of writebacks -system.cpu.dcache.writebacks::total 165814 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35342 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35342 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524325 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 524325 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 559667 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 559667 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 559667 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 559667 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 168353 # number of writebacks +system.cpu.dcache.writebacks::total 168353 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35603 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35603 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895078 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895078 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 930681 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 930681 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 930681 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 930681 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses @@ -460,14 +460,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204347 system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1847026500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1847026500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6899064500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6899064500 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16486810000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16486810000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -476,152 +476,152 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30395.222736 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30395.222736 # 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mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785483 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.577965 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092173 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785483 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.577965 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42158.812205 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37131.710969 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38210.038256 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38046.806154 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38046.806154 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42158.812205 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37878.827856 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38083.131172 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42158.812205 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37878.827856 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38083.131172 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 113997 # number of writebacks +system.cpu.l2cache.writebacks::total 113997 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7108 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27520 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 34628 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130891 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130891 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7108 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158411 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165519 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7108 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158411 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 165519 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 310665087 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1192490455 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1503155542 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12652907225 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12652907225 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 310665087 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13845397680 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14156062767 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 310665087 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13845397680 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14156062767 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081475 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454298 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.234259 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910419 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910419 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081475 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775206 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.567645 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081475 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775206 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.567645 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43706.399409 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43331.775254 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 43408.673386 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96667.511326 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96667.511326 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43706.399409 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87401.744071 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 85525.303844 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43706.399409 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87401.744071 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85525.303844 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index ce6ab2ad0..04dfac9bb 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.021820 # Number of seconds simulated -sim_ticks 21820020000 # Number of ticks simulated -final_tick 21820020000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024767 # Number of seconds simulated +sim_ticks 24766869000 # Number of ticks simulated +final_tick 24766869000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 158943 # Simulator instruction rate (inst/s) -host_op_rate 158943 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43574235 # Simulator tick rate (ticks/s) -host_mem_usage 253708 # Number of bytes of host memory used -host_seconds 500.76 # Real time elapsed on the host +host_inst_rate 162319 # Simulator instruction rate (inst/s) +host_op_rate 162319 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50509376 # Simulator tick rate (ticks/s) +host_mem_usage 253968 # Number of bytes of host memory used +host_seconds 490.34 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 559680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10296000 # Number of bytes read from this memory -system.physmem.bytes_read::total 10855680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 559680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 559680 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7426944 # Number of bytes written to this memory -system.physmem.bytes_written::total 7426944 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8745 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 160875 # Number of read requests responded to by this memory -system.physmem.num_reads::total 169620 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116046 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116046 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25649839 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 471860246 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 497510085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 25649839 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 25649839 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 340372924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 340372924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 340372924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25649839 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 471860246 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 837883008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 169621 # Total number of read requests seen -system.physmem.writeReqs 116046 # Total number of write requests seen -system.physmem.cpureqs 285667 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10855680 # Total number of bytes read from memory -system.physmem.bytesWritten 7426944 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10855680 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7426944 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 491520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10154752 # Number of bytes read from this memory +system.physmem.bytes_read::total 10646272 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 491520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 491520 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7296960 # Number of bytes written to this memory +system.physmem.bytes_written::total 7296960 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7680 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158668 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166348 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114015 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114015 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19845867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 410013555 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 429859422 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19845867 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19845867 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 294625857 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 294625857 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 294625857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19845867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 410013555 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 724485279 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166348 # Total number of read requests seen +system.physmem.writeReqs 114015 # Total number of write requests seen +system.physmem.cpureqs 280363 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10646272 # Total number of bytes read from memory +system.physmem.bytesWritten 7296960 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 10646272 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7296960 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 11095 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10656 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10958 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10512 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10822 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10578 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10358 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10136 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10631 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10535 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10838 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10589 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10582 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 10059 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10909 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10352 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7516 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7034 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7412 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7083 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7440 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7204 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7289 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7287 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6976 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7555 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7178 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7257 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7051 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7488 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7299 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 10739 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10314 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10735 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10372 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10586 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10283 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 10277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10016 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10446 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10273 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10645 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10379 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10383 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 9952 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10691 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10255 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7408 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6902 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7249 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6952 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7298 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7042 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7150 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6839 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7207 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6885 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7381 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7081 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7120 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6935 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7375 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7191 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 21820003000 # Total gap between requests +system.physmem.totGap 24766835500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 169621 # Categorize read packet sizes +system.physmem.readPktSize::6 166348 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 116046 # categorize write packet sizes +system.physmem.writePktSize::6 114015 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 66903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 55166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38777 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7012 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 475 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 47 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 70675 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64436 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 24903 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -138,80 +138,80 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5024 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 5060410122 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7401532122 # Sum of mem lat for all requests -system.physmem.totBusLat 678440000 # Total cycles spent in databus access -system.physmem.totBankLat 1662682000 # Total cycles spent in bank access -system.physmem.avgQLat 29835.56 # Average queueing delay per request -system.physmem.avgBankLat 9802.97 # Average bank access latency per request +system.physmem.totQLat 9402171924 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11754135924 # Sum of mem lat for all requests +system.physmem.totBusLat 665384000 # Total cycles spent in databus access +system.physmem.totBankLat 1686580000 # Total cycles spent in bank access +system.physmem.avgQLat 56521.78 # Average queueing delay per request +system.physmem.avgBankLat 10138.99 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 43638.54 # Average memory access latency -system.physmem.avgRdBW 497.51 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 340.37 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 497.51 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 340.37 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 70660.77 # Average memory access latency +system.physmem.avgRdBW 429.86 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 294.63 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 429.86 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 294.63 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 5.24 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.34 # Average read queue length over time -system.physmem.avgWrQLen 10.53 # Average write queue length over time -system.physmem.readRowHits 153635 # Number of row buffer hits during reads -system.physmem.writeRowHits 84286 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.63 # Row buffer hit rate for writes -system.physmem.avgGap 76382.65 # Average gap between requests +system.physmem.busUtil 4.53 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.47 # Average read queue length over time +system.physmem.avgWrQLen 9.66 # Average write queue length over time +system.physmem.readRowHits 152267 # Number of row buffer hits during reads +system.physmem.writeRowHits 40679 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.54 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 35.68 # Row buffer hit rate for writes +system.physmem.avgGap 88338.46 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22500738 # DTB read hits -system.cpu.dtb.read_misses 216644 # DTB read misses -system.cpu.dtb.read_acv 44 # DTB read access violations -system.cpu.dtb.read_accesses 22717382 # DTB read accesses -system.cpu.dtb.write_hits 15795905 # DTB write hits -system.cpu.dtb.write_misses 41245 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 15837150 # DTB write accesses -system.cpu.dtb.data_hits 38296643 # DTB hits -system.cpu.dtb.data_misses 257889 # DTB misses -system.cpu.dtb.data_acv 44 # DTB access violations -system.cpu.dtb.data_accesses 38554532 # DTB accesses -system.cpu.itb.fetch_hits 14148494 # ITB hits -system.cpu.itb.fetch_misses 39336 # ITB misses +system.cpu.dtb.read_hits 22524754 # DTB read hits +system.cpu.dtb.read_misses 221109 # DTB read misses +system.cpu.dtb.read_acv 49 # DTB read access violations +system.cpu.dtb.read_accesses 22745863 # DTB read accesses +system.cpu.dtb.write_hits 15800982 # DTB write hits +system.cpu.dtb.write_misses 41722 # DTB write misses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_accesses 15842704 # DTB write accesses +system.cpu.dtb.data_hits 38325736 # DTB hits +system.cpu.dtb.data_misses 262831 # DTB misses +system.cpu.dtb.data_acv 50 # DTB access violations +system.cpu.dtb.data_accesses 38588567 # DTB accesses +system.cpu.itb.fetch_hits 14187534 # ITB hits +system.cpu.itb.fetch_misses 37797 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14187830 # ITB accesses +system.cpu.itb.fetch_accesses 14225331 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,245 +225,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 43640043 # number of cpu cycles simulated +system.cpu.numCycles 49533742 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16741832 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10806668 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 477582 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12162476 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7482577 # Number of BTB hits +system.cpu.BPredUnit.lookups 16746521 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10800034 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 477053 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12193904 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7496910 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1995510 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 45710 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15036393 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 106856108 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16741832 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9478087 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19828359 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2147542 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 4492220 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 8232 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 323266 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14148494 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 220972 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 41243035 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.590889 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.177319 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 2006546 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 45028 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 16102899 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 106919359 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16746521 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9503456 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19851092 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2196928 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 6491501 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 8361 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 314458 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 32 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 14187534 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 227935 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44359313 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.410302 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.133631 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21414676 51.92% 51.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1548321 3.75% 55.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1410779 3.42% 59.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1521748 3.69% 62.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4201075 10.19% 72.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1864766 4.52% 77.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 686260 1.66% 79.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1087985 2.64% 81.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7507425 18.20% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24508221 55.25% 55.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1552927 3.50% 58.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1407762 3.17% 61.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1534147 3.46% 65.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4200830 9.47% 74.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1874236 4.23% 79.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 688640 1.55% 80.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1098273 2.48% 83.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7494277 16.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 41243035 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.383635 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.448579 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16096491 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4096982 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18769266 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 833511 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1446785 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3807119 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 110554 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 104936406 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 308694 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1446785 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16548633 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1976361 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 82879 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19114757 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2073620 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 103469028 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 341 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 14640 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1956889 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 62372396 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 124769861 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 124309039 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 460822 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44359313 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.338083 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.158516 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17202144 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 6044851 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18844952 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 783382 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1483984 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3808507 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 109388 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 105012446 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 304839 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1483984 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17687031 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3815602 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 84566 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19093119 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2195011 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 103566225 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 486 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2675 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2071816 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 62457346 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 124882897 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 124424416 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 458481 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9825515 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5546 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5543 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4207574 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23385563 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16393614 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1121004 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 386917 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91482649 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5403 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89074963 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 123031 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11309425 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4934372 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 820 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 41243035 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.159758 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.116316 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9910465 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5561 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5559 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4548155 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23430190 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16410014 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1178549 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 390985 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91582200 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5227 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89129103 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 121099 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11405338 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5024468 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 644 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44359313 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.009253 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.109781 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12823282 31.09% 31.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6988742 16.95% 48.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5560534 13.48% 61.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4799338 11.64% 73.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4679683 11.35% 84.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2682377 6.50% 91.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1950315 4.73% 95.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1335480 3.24% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 423284 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15871640 35.78% 35.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6995929 15.77% 51.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5623158 12.68% 64.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4788485 10.79% 75.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4723434 10.65% 85.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2673880 6.03% 91.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1944632 4.38% 96.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1314765 2.96% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 423390 0.95% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 41243035 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44359313 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 129257 6.79% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 803786 42.23% 49.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 970116 50.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 127127 6.74% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 794266 42.09% 48.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 965741 51.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49746538 55.85% 55.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43785 0.05% 55.90% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121262 0.14% 56.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 122235 0.14% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 55 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38920 0.04% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22991531 25.81% 82.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16010548 17.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49762830 55.83% 55.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43850 0.05% 55.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121597 0.14% 56.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121881 0.14% 56.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 60 0.00% 56.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38947 0.04% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23025644 25.83% 82.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16014206 17.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89074963 # Type of FU issued -system.cpu.iq.rate 2.041129 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1903159 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021366 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 220805862 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102391842 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87007224 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 613289 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 421743 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 298831 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90671357 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 306765 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1448727 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89129103 # Type of FU issued +system.cpu.iq.rate 1.799361 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1887134 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021173 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 224014583 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102585406 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87044839 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 611169 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 425269 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 296604 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90710574 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 305663 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1465776 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3108925 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5719 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 17139 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1780237 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3153552 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5566 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18132 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1796637 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2546 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 373 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2518 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 82425 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1446785 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1296877 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 55540 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 101030605 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 244499 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23385563 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16393614 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5403 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 48652 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 428 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 17139 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 253350 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 173638 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 426988 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88093519 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22720865 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 981444 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1483984 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2836184 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 76819 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 101124099 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 260669 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23430190 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16410014 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5227 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 60088 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 531 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18132 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 252052 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 171036 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 423088 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88146777 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22749364 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 982326 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9542553 # number of nop insts executed -system.cpu.iew.exec_refs 38558406 # number of memory reference insts executed -system.cpu.iew.exec_branches 15140678 # Number of branches executed -system.cpu.iew.exec_stores 15837541 # Number of stores executed -system.cpu.iew.exec_rate 2.018640 # Inst execution rate -system.cpu.iew.wb_sent 87722588 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87306055 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33473930 # num instructions producing a value -system.cpu.iew.wb_consumers 43902488 # num instructions consuming a value +system.cpu.iew.exec_nop 9536672 # number of nop insts executed +system.cpu.iew.exec_refs 38592395 # number of memory reference insts executed +system.cpu.iew.exec_branches 15153499 # Number of branches executed +system.cpu.iew.exec_stores 15843031 # Number of stores executed +system.cpu.iew.exec_rate 1.779530 # Inst execution rate +system.cpu.iew.wb_sent 87753741 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87341443 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33435183 # num instructions producing a value +system.cpu.iew.wb_consumers 43872218 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.000595 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762461 # average fanout of values written-back +system.cpu.iew.wb_rate 1.763272 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762104 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9547814 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9751269 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 369802 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39796250 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.219824 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.827061 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 370067 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42875329 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.060408 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.788298 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16770955 42.14% 42.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7067067 17.76% 59.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3514313 8.83% 68.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2098075 5.27% 74.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2085843 5.24% 79.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1169184 2.94% 82.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1108409 2.79% 84.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 748224 1.88% 86.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5234180 13.15% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19913451 46.45% 46.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7068985 16.49% 62.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3438952 8.02% 70.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2090019 4.87% 75.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2085052 4.86% 80.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1168150 2.72% 83.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1107868 2.58% 86.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 727256 1.70% 87.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5275596 12.30% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39796250 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42875329 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -474,358 +475,358 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5234180 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5275596 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 131133214 # The number of ROB reads -system.cpu.rob.rob_writes 197227324 # The number of ROB writes -system.cpu.timesIdled 14215 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2397008 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 134374332 # The number of ROB reads +system.cpu.rob.rob_writes 197671452 # The number of ROB writes +system.cpu.timesIdled 69954 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5174429 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.548299 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.548299 # CPI: Total CPI of All Threads -system.cpu.ipc 1.823824 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.823824 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116640350 # number of integer regfile reads -system.cpu.int_regfile_writes 57883705 # number of integer regfile writes -system.cpu.fp_regfile_reads 253852 # number of floating regfile reads -system.cpu.fp_regfile_writes 241497 # number of floating regfile writes -system.cpu.misc_regfile_reads 38324 # number of misc regfile reads +system.cpu.cpi 0.622348 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.622348 # CPI: Total CPI of All Threads +system.cpu.ipc 1.606819 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.606819 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116696990 # number of integer regfile reads +system.cpu.int_regfile_writes 57893587 # number of integer regfile writes +system.cpu.fp_regfile_reads 251486 # number of floating regfile reads +system.cpu.fp_regfile_writes 240711 # number of floating regfile writes +system.cpu.misc_regfile_reads 38028 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 93950 # number of replacements -system.cpu.icache.tagsinuse 1932.033344 # Cycle average of tags in use -system.cpu.icache.total_refs 14048966 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 95998 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 146.346445 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 18344988000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1932.033344 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.943376 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.943376 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14048966 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14048966 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14048966 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14048966 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14048966 # number of overall hits -system.cpu.icache.overall_hits::total 14048966 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 99528 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 99528 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 99528 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 99528 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 99528 # number of overall misses -system.cpu.icache.overall_misses::total 99528 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 808544500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 808544500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 808544500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 808544500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 808544500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 808544500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14148494 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14148494 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14148494 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14148494 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14148494 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14148494 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007035 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007035 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007035 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007035 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007035 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007035 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8123.789285 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8123.789285 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8123.789285 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8123.789285 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8123.789285 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8123.789285 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.replacements 92300 # number of replacements +system.cpu.icache.tagsinuse 1931.186939 # Cycle average of tags in use +system.cpu.icache.total_refs 14080520 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 94348 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 149.240259 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 20259707000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1931.186939 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.942962 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.942962 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14080520 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14080520 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14080520 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14080520 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14080520 # number of overall hits +system.cpu.icache.overall_hits::total 14080520 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 107014 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 107014 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 107014 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 107014 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 107014 # number of overall misses +system.cpu.icache.overall_misses::total 107014 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1801616999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1801616999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1801616999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1801616999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1801616999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1801616999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14187534 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14187534 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14187534 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14187534 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14187534 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14187534 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007543 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007543 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007543 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007543 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007543 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007543 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16835.339292 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16835.339292 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16835.339292 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16835.339292 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16835.339292 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16835.339292 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 434 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 48.222222 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3529 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3529 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3529 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3529 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3529 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3529 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 95999 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 95999 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 95999 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 95999 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 95999 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 95999 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 523730500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 523730500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 523730500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 523730500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 523730500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 523730500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006785 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006785 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006785 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006785 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006785 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006785 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5455.582871 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5455.582871 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5455.582871 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 5455.582871 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5455.582871 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 5455.582871 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12665 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 12665 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 12665 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 12665 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 12665 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 12665 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 94349 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 94349 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 94349 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 94349 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 94349 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 94349 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1400064000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1400064000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1400064000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1400064000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1400064000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1400064000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006650 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006650 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006650 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006650 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006650 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006650 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14839.203383 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14839.203383 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14839.203383 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14839.203383 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14839.203383 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14839.203383 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201587 # number of replacements -system.cpu.dcache.tagsinuse 4077.730467 # Cycle average of tags in use -system.cpu.dcache.total_refs 34377845 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205683 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.139944 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 145380000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4077.730467 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995540 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995540 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20796650 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20796650 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13581134 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13581134 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34377784 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34377784 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34377784 # number of overall hits -system.cpu.dcache.overall_hits::total 34377784 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 252404 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 252404 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1032243 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1032243 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1284647 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1284647 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1284647 # number of overall misses -system.cpu.dcache.overall_misses::total 1284647 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7081461500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7081461500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 60841906500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 60841906500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 67923368000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 67923368000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 67923368000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 67923368000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21049054 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21049054 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 201586 # number of replacements +system.cpu.dcache.tagsinuse 4077.128651 # Cycle average of tags in use +system.cpu.dcache.total_refs 34331018 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205682 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 166.913089 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 177489000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4077.128651 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995393 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995393 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20756846 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20756846 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574115 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574115 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34330961 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34330961 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34330961 # number of overall hits +system.cpu.dcache.overall_hits::total 34330961 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 266792 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 266792 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1039262 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1039262 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1306054 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1306054 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1306054 # number of overall misses +system.cpu.dcache.overall_misses::total 1306054 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12393965000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12393965000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 93492268598 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 93492268598 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 105886233598 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 105886233598 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 105886233598 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 105886233598 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21023638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21023638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35662431 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35662431 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35662431 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35662431 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011991 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011991 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070637 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.070637 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036022 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036022 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036022 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036022 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28056.058937 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28056.058937 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58941.457099 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 58941.457099 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52873.176834 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52873.176834 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52873.176834 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52873.176834 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1971 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 36 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 57 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 57 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35637015 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35637015 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35637015 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35637015 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012690 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012690 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071117 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071117 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036649 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036649 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036649 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036649 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46455.534649 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 46455.534649 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89960.249290 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 89960.249290 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 81073.396351 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 81073.396351 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 81073.396351 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 81073.396351 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5474703 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 114 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 112304 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.750000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 40 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.748958 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 114 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 166289 # number of writebacks -system.cpu.dcache.writebacks::total 166289 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 190140 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 190140 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 888824 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 888824 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1078964 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1078964 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1078964 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1078964 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62264 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62264 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 169009 # number of writebacks +system.cpu.dcache.writebacks::total 169009 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204529 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 204529 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895843 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895843 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1100372 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1100372 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1100372 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1100372 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62263 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62263 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143419 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 143419 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205683 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205683 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205683 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205683 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1130234500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1130234500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8280369500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8280369500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9410604000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9410604000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9410604000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9410604000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002958 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 205682 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205682 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205682 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205682 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2025118000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2025118000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14654502991 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14654502991 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16679620991 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16679620991 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16679620991 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16679620991 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002962 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002962 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005767 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005767 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005767 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005767 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18152.295066 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18152.295066 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57735.512728 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57735.512728 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45752.949928 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45752.949928 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45752.949928 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45752.949928 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005772 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005772 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005772 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005772 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32525.223648 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32525.223648 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102179.648380 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102179.648380 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81094.218215 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 81094.218215 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81094.218215 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 81094.218215 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 137215 # number of replacements -system.cpu.l2cache.tagsinuse 29193.790344 # Cycle average of tags in use -system.cpu.l2cache.total_refs 156193 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 168097 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.929184 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 132442 # number of replacements +system.cpu.l2cache.tagsinuse 30854.003971 # Cycle average of tags in use +system.cpu.l2cache.total_refs 160847 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 164507 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.977752 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 25457.491350 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1903.606524 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1832.692470 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.776901 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.058093 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.055929 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.890924 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 87253 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 32348 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 119601 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 166289 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 166289 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12460 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12460 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 87253 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 44808 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 132061 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 87253 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 44808 # number of overall hits -system.cpu.l2cache.overall_hits::total 132061 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 8746 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 29915 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 38661 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 130960 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130960 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 8746 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 160875 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 169621 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 8746 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 160875 # number of overall misses -system.cpu.l2cache.overall_misses::total 169621 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 339345000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1033623500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1372968500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8119728500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8119728500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 339345000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9153352000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9492697000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 339345000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9153352000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9492697000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 95999 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 62263 # 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number of writebacks +system.cpu.l2cache.writebacks::total 114015 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7681 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27866 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 35547 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130802 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130802 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7681 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158668 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166349 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7681 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158668 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166349 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 340900477 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1256603152 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1597503629 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12762940575 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12762940575 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 340900477 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14019543727 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14360444204 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 340900477 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14019543727 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14360444204 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081411 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.447582 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.226981 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912002 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912002 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081411 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771424 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.554439 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081411 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771424 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.554439 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44382.303997 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45094.493361 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 44940.603398 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 97574.506315 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 97574.506315 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44382.303997 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88357.726366 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86327.204876 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44382.303997 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88357.726366 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86327.204876 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 456c7f9d2..43727f4ad 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133756 # Number of seconds simulated -sim_ticks 133756135000 # Number of ticks simulated -final_tick 133756135000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133635 # Number of seconds simulated +sim_ticks 133634727000 # Number of ticks simulated +final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1270571 # Simulator instruction rate (inst/s) -host_op_rate 1270570 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1923763163 # Simulator tick rate (ticks/s) -host_mem_usage 227600 # Number of bytes of host memory used -host_seconds 69.53 # Real time elapsed on the host +host_inst_rate 783809 # Simulator instruction rate (inst/s) +host_op_rate 783809 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1185683886 # Simulator tick rate (ticks/s) +host_mem_usage 225136 # Number of bytes of host memory used +host_seconds 112.71 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 485312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10270528 # Number of bytes read from this memory -system.physmem.bytes_read::total 10755840 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 485312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 485312 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7421120 # Number of bytes written to this memory -system.physmem.bytes_written::total 7421120 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7583 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 160477 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168060 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115955 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115955 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 3628335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 76785472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 80413807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3628335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3628335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 55482464 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 55482464 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 55482464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3628335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 76785472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 135896271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 432896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10136896 # Number of bytes read from this memory +system.physmem.bytes_read::total 10569792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 432896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 432896 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7294848 # Number of bytes written to this memory +system.physmem.bytes_written::total 7294848 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6764 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158389 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165153 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 113982 # Number of write requests responded to by this memory +system.physmem.num_writes::total 113982 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 3239397 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 75855253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 79094650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3239397 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3239397 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54587966 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54587966 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54587966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3239397 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 75855253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 133682617 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 267512270 # number of cpu cycles simulated +system.cpu.numCycles 267269454 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88340673 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 34987415 # nu system.cpu.num_load_insts 20366786 # Number of load instructions system.cpu.num_store_insts 14620629 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 267512270 # Number of busy cycles +system.cpu.num_busy_cycles 267269454 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 74391 # number of replacements -system.cpu.icache.tagsinuse 1871.674409 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1871.686406 # Cycle average of tags in use system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1871.674409 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.913904 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.913904 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1871.686406 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.913909 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 76436 # n system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses system.cpu.icache.overall_misses::total 76436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1312229000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1312229000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1312229000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1312229000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1312229000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1312229000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1278112000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1278112000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1278112000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1278112000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1278112000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1278112000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17167.682767 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17167.682767 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17167.682767 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17167.682767 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17167.682767 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17167.682767 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16721.335496 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16721.335496 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16721.335496 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16721.335496 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16721.335496 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16721.335496 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 76436 system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1159357000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1159357000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1159357000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1159357000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1159357000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1159357000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1125240000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1125240000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1125240000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1125240000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1125240000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1125240000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15167.682767 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15167.682767 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15167.682767 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15167.682767 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15167.682767 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15167.682767 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14721.335496 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14721.335496 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200248 # number of replacements -system.cpu.dcache.tagsinuse 4078.879185 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4078.863631 # Cycle average of tags in use system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 936463000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4078.879185 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995820 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995820 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995816 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 204344 # n system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses system.cpu.dcache.overall_misses::total 204344 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2026896000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2026896000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7369702000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7369702000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9396598000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9396598000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9396598000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9396598000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1945752000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1945752000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363555000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7363555000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9309307000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9309307000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9309307000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9309307000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33355.758154 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33355.758154 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51328.908329 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 51328.908329 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45984.212896 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45984.212896 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45984.212896 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45984.212896 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32020.406148 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32020.406148 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51286.095363 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 51286.095363 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45557.036174 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45557.036174 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 165828 # number of writebacks -system.cpu.dcache.writebacks::total 165828 # number of writebacks +system.cpu.dcache.writebacks::writebacks 168375 # number of writebacks +system.cpu.dcache.writebacks::total 168375 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204344 system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1905364000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1905364000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7082546000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7082546000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8987910000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8987910000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8987910000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8987910000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1824220000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1824220000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7076399000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7076399000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8900619000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8900619000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8900619000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8900619000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -258,68 +258,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31355.758154 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31355.758154 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49328.908329 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49328.908329 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43984.212896 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43984.212896 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43984.212896 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 43984.212896 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30020.406148 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30020.406148 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49286.095363 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49286.095363 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 135625 # number of replacements -system.cpu.l2cache.tagsinuse 29005.267541 # Cycle average of tags in use -system.cpu.l2cache.total_refs 136279 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 166491 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.818537 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 131235 # 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miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099207 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.785328 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.598547 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099207 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.785328 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.598547 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52009.890545 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52002.716561 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52004.185569 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.091583 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.091583 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5235279000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 270916000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6336057000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6606973000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 270916000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6336057000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6606973000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.452687 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.249792 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911567 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911567 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775110 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.588194 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775110 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.588194 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40052.631579 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40016.649702 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40023.751167 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.297981 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.297981 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40052.631579 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40052.631579 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index c4dd2ec41..bbe40238a 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024118 # Number of seconds simulated -sim_ticks 24118236000 # Number of ticks simulated -final_tick 24118236000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026781 # Number of seconds simulated +sim_ticks 26780535000 # Number of ticks simulated +final_tick 26780535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 96109 # Simulator instruction rate (inst/s) -host_op_rate 136382 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32682486 # Simulator tick rate (ticks/s) -host_mem_usage 260548 # Number of bytes of host memory used -host_seconds 737.96 # Real time elapsed on the host -sim_insts 70924474 # Number of instructions simulated -sim_ops 100643721 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 326720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8028032 # Number of bytes read from this memory -system.physmem.bytes_read::total 8354752 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 326720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 326720 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5417408 # Number of bytes written to this memory -system.physmem.bytes_written::total 5417408 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5105 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125438 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130543 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 84647 # Number of write requests responded to by this memory -system.physmem.num_writes::total 84647 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 13546596 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 332861491 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 346408087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 13546596 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 13546596 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 224618749 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 224618749 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 224618749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 13546596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 332861491 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 571026836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 130544 # Total number of read requests seen -system.physmem.writeReqs 84647 # Total number of write requests seen -system.physmem.cpureqs 215212 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 8354752 # Total number of bytes read from memory -system.physmem.bytesWritten 5417408 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8354752 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5417408 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 6 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 21 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 8259 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8120 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 8253 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 7969 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 7982 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8186 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 8215 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 8129 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 8104 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8304 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 8313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 8256 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 8235 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 8061 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 8114 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8038 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5294 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5079 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 5310 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5269 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 5220 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5401 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 5230 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 5186 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5230 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5326 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5458 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5400 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5367 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 5357 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5265 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5255 # Track writes on a per bank basis +host_inst_rate 149394 # Simulator instruction rate (inst/s) +host_op_rate 211994 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56410244 # Simulator tick rate (ticks/s) +host_mem_usage 261852 # Number of bytes of host memory used +host_seconds 474.75 # Real time elapsed on the host +sim_insts 70924159 # Number of instructions simulated +sim_ops 100643406 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 300160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7944448 # Number of bytes read from this memory +system.physmem.bytes_read::total 8244608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 300160 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 300160 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372672 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372672 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4690 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124132 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128822 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83948 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83948 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11208141 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 296650086 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 307858226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11208141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11208141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 200618546 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 200618546 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 200618546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11208141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 296650086 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 508476772 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128823 # Total number of read requests seen +system.physmem.writeReqs 83948 # Total number of write requests seen +system.physmem.cpureqs 213079 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 8244608 # Total number of bytes read from memory +system.physmem.bytesWritten 5372672 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 8244608 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 5372672 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 308 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 8176 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 8046 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 8102 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 7891 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 7930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 8109 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 8032 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 7950 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7992 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 8193 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 8188 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 8163 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 8063 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 8009 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7995 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 7981 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5174 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 5038 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 5232 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5233 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 5165 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 5377 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 5168 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 5136 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5231 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5377 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5465 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 5417 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5374 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 5287 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5126 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5148 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24118216500 # Total gap between requests +system.physmem.totGap 26780515500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 130544 # Categorize read packet sizes +system.physmem.readPktSize::6 128823 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 84647 # categorize write packet sizes +system.physmem.writePktSize::6 83948 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,16 +102,16 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 21 # categorize neither packet sizes +system.physmem.neitherpktsize::6 308 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 69205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 57726 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3491 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 86 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 71083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 55295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -138,31 +138,31 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,27 +171,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2308860118 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4224446118 # Sum of mem lat for all requests -system.physmem.totBusLat 522152000 # Total cycles spent in databus access -system.physmem.totBankLat 1393434000 # Total cycles spent in bank access -system.physmem.avgQLat 17687.26 # Average queueing delay per request -system.physmem.avgBankLat 10674.55 # Average bank access latency per request +system.physmem.totQLat 4847041699 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 6735959699 # Sum of mem lat for all requests +system.physmem.totBusLat 515280000 # Total cycles spent in databus access +system.physmem.totBankLat 1373638000 # Total cycles spent in bank access +system.physmem.avgQLat 37626.47 # Average queueing delay per request +system.physmem.avgBankLat 10663.24 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32361.81 # Average memory access latency -system.physmem.avgRdBW 346.41 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 224.62 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 346.41 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 224.62 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 52289.70 # Average memory access latency +system.physmem.avgRdBW 307.86 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 200.62 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 307.86 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 200.62 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.57 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.18 # Average read queue length over time -system.physmem.avgWrQLen 10.22 # Average write queue length over time -system.physmem.readRowHits 119025 # Number of row buffer hits during reads -system.physmem.writeRowHits 63519 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.18 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.04 # Row buffer hit rate for writes -system.physmem.avgGap 112078.18 # Average gap between requests +system.physmem.busUtil 3.18 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.25 # Average read queue length over time +system.physmem.avgWrQLen 9.64 # Average write queue length over time +system.physmem.readRowHits 118946 # Number of row buffer hits during reads +system.physmem.writeRowHits 27105 # Number of row buffer hits during writes +system.physmem.readRowHitRate 92.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.29 # Row buffer hit rate for writes +system.physmem.avgGap 125865.44 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,576 +235,581 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 48236473 # number of cpu cycles simulated +system.cpu.numCycles 53561071 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16941730 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12971297 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 673506 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11955063 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7993850 # Number of BTB hits +system.cpu.BPredUnit.lookups 16989438 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12991194 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 680202 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11755292 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8009849 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1846956 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 114386 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12578866 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 86846522 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16941730 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9840806 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21621241 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2621679 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 9822158 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 11935876 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 192083 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 45946369 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.646136 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.346825 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1851785 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 114363 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 12914479 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87008149 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16989438 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9861634 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21655288 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2666634 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10515039 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 139 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 571 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11971869 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 198806 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47045662 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.589318 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.332778 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24346810 52.99% 52.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2176798 4.74% 57.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2018114 4.39% 62.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2096656 4.56% 66.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1493050 3.25% 69.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1410144 3.07% 73.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 982338 2.14% 75.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1219252 2.65% 77.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10203207 22.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25412140 54.02% 54.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2169507 4.61% 58.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2024864 4.30% 62.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2094897 4.45% 67.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1497374 3.18% 70.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1417625 3.01% 73.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 986770 2.10% 75.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1225872 2.61% 78.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10216613 21.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 45946369 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.351222 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.800433 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14667970 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8208523 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19889635 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1362773 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1817468 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3410064 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 108805 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118869438 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 371525 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1817468 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16391147 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2180805 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 744758 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19482609 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5329582 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 116713190 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 108 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 9859 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4505903 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 207 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 117071318 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 537479367 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 537472531 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6836 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99159624 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 17911694 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25668 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25645 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12679365 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29945230 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22644975 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3554453 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4308488 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 112817859 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 41708 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 108131794 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 320520 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12061302 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 28451439 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4553 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 45946369 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.353435 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.992555 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 47045662 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.317198 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.624466 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15025286 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8880734 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19918391 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1367786 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1853465 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3434521 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 108932 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 119105730 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 372945 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1853465 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16780714 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2530019 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 932679 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19483180 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5465605 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 116933277 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 184 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 14375 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4623545 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 215 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 117254635 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 538431443 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 538426294 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5149 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99159120 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 18095515 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25625 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25611 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12984960 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29963650 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22702028 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3806099 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4346835 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 113028204 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 41641 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 108286515 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 316116 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12256138 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 28707838 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4549 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47045662 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.301732 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.993875 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10567306 23.00% 23.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8020118 17.46% 40.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7429171 16.17% 56.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7172224 15.61% 72.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5474021 11.91% 84.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3920572 8.53% 92.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1887629 4.11% 96.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 890680 1.94% 98.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 584648 1.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11469393 24.38% 24.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8159881 17.34% 41.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7486298 15.91% 57.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7193710 15.29% 72.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5478307 11.64% 84.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3936871 8.37% 92.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1856294 3.95% 96.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 881703 1.87% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 583205 1.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 45946369 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47045662 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112571 4.42% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1415190 55.57% 59.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1018757 40.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112009 4.47% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1372514 54.80% 59.28% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1019865 40.72% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57176824 52.88% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91588 0.08% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 236 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29115499 26.93% 79.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21747640 20.11% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57275495 52.89% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91732 0.08% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 181 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29138143 26.91% 79.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21780957 20.11% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 108131794 # Type of FU issued -system.cpu.iq.rate 2.241702 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2546520 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023550 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 265076321 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 124946354 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 106228285 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 676 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1064 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 184 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 110677977 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 337 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2176777 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 108286515 # Type of FU issued +system.cpu.iq.rate 2.021739 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2504390 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023127 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 266438684 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 125354112 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 106381358 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 514 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 754 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 110790645 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 260 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2168801 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2634753 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7333 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 27466 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2085868 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2653236 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7465 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30261 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2142984 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 33 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 473 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1817468 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 825568 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 31883 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 112869381 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 345659 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29945230 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22644975 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 25238 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1097 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3023 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 27466 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 452017 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 199338 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 651355 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106955311 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28765738 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1176483 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1853465 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1042007 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 44975 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 113079657 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 348290 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29963650 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22702028 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 25073 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6129 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5511 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30261 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 453510 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 204690 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 658200 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 107104018 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28789803 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1182497 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9814 # number of nop insts executed -system.cpu.iew.exec_refs 50205955 # number of memory reference insts executed -system.cpu.iew.exec_branches 14704580 # Number of branches executed -system.cpu.iew.exec_stores 21440217 # Number of stores executed -system.cpu.iew.exec_rate 2.217312 # Inst execution rate -system.cpu.iew.wb_sent 106472209 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 106228469 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53599142 # num instructions producing a value -system.cpu.iew.wb_consumers 104275439 # num instructions consuming a value +system.cpu.iew.exec_nop 9812 # number of nop insts executed +system.cpu.iew.exec_refs 50259028 # number of memory reference insts executed +system.cpu.iew.exec_branches 14733119 # Number of branches executed +system.cpu.iew.exec_stores 21469225 # Number of stores executed +system.cpu.iew.exec_rate 1.999662 # Inst execution rate +system.cpu.iew.wb_sent 106622925 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 106381514 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53628948 # num instructions producing a value +system.cpu.iew.wb_consumers 104196549 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.202244 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514015 # average fanout of values written-back +system.cpu.iew.wb_rate 1.986172 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514690 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 12220612 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37155 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 567157 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44128902 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.280802 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.756042 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 12431579 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37092 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 573556 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 45192198 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.227131 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.747743 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14889585 33.74% 33.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11723135 26.57% 60.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3525477 7.99% 68.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2911105 6.60% 74.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1898953 4.30% 79.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1983472 4.49% 83.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 685141 1.55% 85.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 578421 1.31% 86.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5933613 13.45% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15976760 35.35% 35.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11724717 25.94% 61.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3516948 7.78% 69.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2892652 6.40% 75.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1888504 4.18% 79.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1974510 4.37% 84.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 692586 1.53% 85.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 573861 1.27% 86.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5951660 13.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44128902 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70930026 # Number of instructions committed -system.cpu.commit.committedOps 100649273 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 45192198 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70929711 # Number of instructions committed +system.cpu.commit.committedOps 100648958 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47869584 # Number of memory references committed -system.cpu.commit.loads 27310477 # Number of loads committed +system.cpu.commit.refs 47869458 # Number of memory references committed +system.cpu.commit.loads 27310414 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13744874 # Number of branches committed +system.cpu.commit.branches 13744811 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91486255 # Number of committed integer instructions. +system.cpu.commit.int_insts 91486003 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5933613 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5951660 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 151039875 # The number of ROB reads -system.cpu.rob.rob_writes 227567987 # The number of ROB writes -system.cpu.timesIdled 41986 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2290104 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70924474 # Number of Instructions Simulated -system.cpu.committedOps 100643721 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70924474 # Number of Instructions Simulated -system.cpu.cpi 0.680110 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.680110 # CPI: Total CPI of All Threads -system.cpu.ipc 1.470350 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.470350 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 514798749 # number of integer regfile reads -system.cpu.int_regfile_writes 104102920 # number of integer regfile writes -system.cpu.fp_regfile_reads 856 # number of floating regfile reads -system.cpu.fp_regfile_writes 720 # number of floating regfile writes -system.cpu.misc_regfile_reads 145263086 # number of misc regfile reads -system.cpu.misc_regfile_writes 38578 # number of misc regfile writes -system.cpu.icache.replacements 29552 # number of replacements -system.cpu.icache.tagsinuse 1826.273597 # Cycle average of tags in use -system.cpu.icache.total_refs 11903209 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 31595 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 376.743440 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 152295776 # The number of ROB reads +system.cpu.rob.rob_writes 228025366 # The number of ROB writes +system.cpu.timesIdled 74466 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6515409 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70924159 # Number of Instructions Simulated +system.cpu.committedOps 100643406 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70924159 # Number of Instructions Simulated +system.cpu.cpi 0.755188 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.755188 # CPI: Total CPI of All Threads +system.cpu.ipc 1.324174 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.324174 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 515451838 # number of integer regfile reads +system.cpu.int_regfile_writes 104231541 # number of integer regfile writes +system.cpu.fp_regfile_reads 698 # number of floating regfile reads +system.cpu.fp_regfile_writes 610 # number of floating regfile writes +system.cpu.misc_regfile_reads 145512549 # number of misc regfile reads +system.cpu.misc_regfile_writes 38452 # number of misc regfile writes +system.cpu.icache.replacements 31300 # number of replacements +system.cpu.icache.tagsinuse 1822.220766 # Cycle average of tags in use +system.cpu.icache.total_refs 11934433 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 33335 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 358.015089 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1826.273597 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.891735 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.891735 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11903210 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11903210 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11903210 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11903210 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11903210 # 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number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 361659000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11935876 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11935876 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11935876 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11935876 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11935876 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11935876 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002737 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002737 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002737 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002737 # 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Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.889756 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11934443 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11934443 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11934443 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11934443 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11934443 # number of overall hits +system.cpu.icache.overall_hits::total 11934443 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 37425 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 37425 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 37425 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 37425 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 37425 # number of overall misses +system.cpu.icache.overall_misses::total 37425 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 718344999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 718344999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 718344999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 718344999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 718344999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 718344999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11971868 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11971868 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11971868 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11971868 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11971868 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11971868 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003126 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003126 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003126 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003126 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003126 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003126 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19194.255150 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19194.255150 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19194.255150 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19194.255150 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19194.255150 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19194.255150 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1048 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55.157895 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1048 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1048 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1048 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1048 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1048 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1048 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31618 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 31618 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 31618 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 31618 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 31618 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 31618 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 265572000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 265572000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 265572000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 265572000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 265572000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 265572000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002649 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002649 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002649 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8399.392751 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8399.392751 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8399.392751 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8399.392751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8399.392751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8399.392751 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3774 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3774 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3774 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 589350499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 589350499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 589350499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002811 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002811 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002811 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002811 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002811 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002811 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17513.610264 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17513.610264 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17513.610264 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17513.610264 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17513.610264 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17513.610264 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158443 # number of replacements -system.cpu.dcache.tagsinuse 4074.275674 # Cycle average of tags in use -system.cpu.dcache.total_refs 44571484 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162539 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 274.220243 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 222430000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4074.275674 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994696 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994696 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26246493 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26246493 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18285066 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18285066 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 20587 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 20587 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 19288 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 19288 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44531559 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44531559 # 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number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 20455 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 20455 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 19225 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 19225 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44523515 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44523515 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44523515 # number of overall hits +system.cpu.dcache.overall_hits::total 44523515 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 125393 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 125393 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1584834 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1584834 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 44 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 44 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1710227 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1710227 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1710227 # number of overall misses +system.cpu.dcache.overall_misses::total 1710227 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4597179000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4597179000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 120104513482 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 120104513482 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 949000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 949000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 124701692482 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 124701692482 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 124701692482 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 124701692482 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26383841 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26383841 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20624 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 20624 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 19288 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 19288 # 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miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036144 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036144 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036144 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24747.305993 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24747.305993 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38468.092802 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38468.092802 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12121.621622 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12121.621622 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37604.953760 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37604.953760 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37604.953760 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37604.953760 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 149 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16.555556 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20499 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20499 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 19225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 19225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46233742 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46233742 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46233742 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46233742 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079841 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079841 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002146 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002146 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036991 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036991 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036991 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036991 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36662.166150 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36662.166150 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75783.655248 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75783.655248 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21568.181818 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21568.181818 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72915.286966 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72915.286966 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72915.286966 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72915.286966 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2506 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 608 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 117 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.418803 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 38 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128088 # number of writebacks -system.cpu.dcache.writebacks::total 128088 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49495 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 49495 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1457827 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1457827 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1507322 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1507322 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1507322 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1507322 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55553 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55553 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107008 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107008 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162561 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162561 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162561 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162561 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1141045500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1141045500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4220015000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4220015000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5361060500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5361060500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5361060500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5361060500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 129149 # number of writebacks +system.cpu.dcache.writebacks::total 129149 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69778 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69778 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477521 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1477521 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 44 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 44 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1547299 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1547299 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1547299 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1547299 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55615 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55615 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107313 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107313 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162928 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162928 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162928 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162928 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2039094000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2039094000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257233993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257233993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10296327993 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10296327993 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10296327993 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10296327993 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002108 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002108 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005391 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005391 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003519 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003519 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003519 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003519 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20539.763829 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20539.763829 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39436.444004 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39436.444004 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32978.761819 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 32978.761819 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32978.761819 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32978.761819 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003524 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003524 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003524 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003524 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36664.461027 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36664.461027 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76945.328087 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76945.328087 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63195.571007 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 63195.571007 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63195.571007 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 63195.571007 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 97971 # number of replacements -system.cpu.l2cache.tagsinuse 28800.701977 # Cycle average of tags in use -system.cpu.l2cache.total_refs 86327 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 128762 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.670438 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 95689 # number of replacements +system.cpu.l2cache.tagsinuse 30139.737825 # Cycle average of tags in use +system.cpu.l2cache.total_refs 90978 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 126809 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.717441 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 25974.611226 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1154.606563 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1671.484188 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.792682 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.035236 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.051010 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.878928 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 26463 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 32338 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 58801 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 128088 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 128088 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4704 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4704 # 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number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 22 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 107020 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107020 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 31593 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 162539 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 194132 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 31593 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 162539 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 194132 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.162378 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.417533 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.324995 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.954545 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.954545 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.956046 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.956046 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.162378 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.772104 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.672877 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.162378 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.772104 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.672877 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 40329.629630 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1383.020531 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1869.742346 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.820525 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.042206 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.057060 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.919792 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 28461 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 33637 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 62098 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 129149 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 129149 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 17 # 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Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 88647a82b..9156fbcd7 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.132746 # Number of seconds simulated -sim_ticks 132746076000 # Number of ticks simulated -final_tick 132746076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.132689 # Number of seconds simulated +sim_ticks 132689045000 # Number of ticks simulated +final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 594787 # Simulator instruction rate (inst/s) -host_op_rate 843423 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1121948184 # Simulator tick rate (ticks/s) -host_mem_usage 240564 # Number of bytes of host memory used -host_seconds 118.32 # Real time elapsed on the host +host_inst_rate 796611 # Simulator instruction rate (inst/s) +host_op_rate 1129615 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1502004709 # Simulator tick rate (ticks/s) +host_mem_usage 239164 # Number of bytes of host memory used +host_seconds 88.34 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated sim_ops 99791654 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 273728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8003456 # Number of bytes read from this memory -system.physmem.bytes_read::total 8277184 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 273728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 273728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5403392 # Number of bytes written to this memory -system.physmem.bytes_written::total 5403392 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4277 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125054 # Number of read requests responded to by this memory -system.physmem.num_reads::total 129331 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 84428 # Number of write requests responded to by this memory -system.physmem.num_writes::total 84428 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2062042 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 60291470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 62353512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2062042 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2062042 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 40704721 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 40704721 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 40704721 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2062042 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 60291470 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 103058233 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7924480 # Number of bytes read from this memory +system.physmem.bytes_read::total 8179968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 255488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 255488 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5370176 # Number of bytes written to this memory +system.physmem.bytes_written::total 5370176 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3992 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123820 # Number of read requests responded to by this memory +system.physmem.num_reads::total 127812 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1925464 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 59722187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 61647651 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1925464 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1925464 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 40471887 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 40471887 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 40471887 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1925464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 59722187 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 102119538 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 265492152 # number of cpu cycles simulated +system.cpu.numCycles 265378090 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70373628 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 47862847 # nu system.cpu.num_load_insts 27307108 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 265492152 # Number of busy cycles +system.cpu.num_busy_cycles 265378090 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 16890 # number of replacements -system.cpu.icache.tagsinuse 1736.430287 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1736.497265 # Cycle average of tags in use system.cpu.icache.total_refs 78126161 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 4131.910355 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1736.430287 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.847866 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.847866 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1736.497265 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.847899 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.847899 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 425522000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 425522000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 425522000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 425522000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 425522000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 425522000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 413722000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 413722000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 413722000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 413722000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 413722000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 413722000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22504.865665 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22504.865665 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22504.865665 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22504.865665 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22504.865665 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22504.865665 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21880.791199 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21880.791199 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21880.791199 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21880.791199 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21880.791199 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21880.791199 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908 system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 387706000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 387706000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 387706000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 387706000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 387706000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 387706000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 375906000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 375906000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 375906000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 375906000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 375906000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 375906000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20504.865665 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20504.865665 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20504.865665 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20504.865665 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20504.865665 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20504.865665 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19880.791199 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19880.791199 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 155902 # number of replacements -system.cpu.dcache.tagsinuse 4076.962537 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4076.954355 # Cycle average of tags in use system.cpu.dcache.total_refs 46862074 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 292.891624 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.962537 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995352 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995352 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995350 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 159998 # n system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 159998 # number of overall misses system.cpu.dcache.overall_misses::total 159998 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1642566000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1642566000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689754000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5689754000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7332320000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7332320000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7332320000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7332320000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1599899000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1599899000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5687190000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5687190000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7287089000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7287089000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7287089000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7287089000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 27140333 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 27140333 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.003405 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31011.705622 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31011.705622 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53159.372898 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53159.372898 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45827.572845 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45827.572845 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45827.572845 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45827.572845 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30206.151116 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30206.151116 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53135.417445 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53135.417445 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45544.875561 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45544.875561 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 127057 # number of writebacks -system.cpu.dcache.writebacks::total 127057 # number of writebacks +system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks +system.cpu.dcache.writebacks::total 128239 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 52966 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 52966 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 159998 system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1536634000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1536634000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475690000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475690000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7012324000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7012324000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7012324000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7012324000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1493967000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1493967000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5473126000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5473126000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6967093000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6967093000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6967093000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6967093000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 system.cpu.dcache.demand_mshr_miss_rate::total 0.003405 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003405 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29011.705622 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29011.705622 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51159.372898 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51159.372898 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43827.572845 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43827.572845 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43827.572845 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 43827.572845 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28206.151116 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28206.151116 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51135.417445 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51135.417445 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 96735 # number of replacements -system.cpu.l2cache.tagsinuse 28875.776749 # Cycle average of tags in use -system.cpu.l2cache.total_refs 71387 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 127516 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.559828 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 94693 # number of replacements +system.cpu.l2cache.tagsinuse 30368.194893 # Cycle average of tags in use +system.cpu.l2cache.total_refs 74295 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 125788 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.590637 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26451.163706 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 950.000997 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1474.612046 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.807225 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.028992 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.045002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.881219 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 14631 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 30253 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 44884 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 127057 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 127057 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4691 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4691 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 14631 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 34944 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 49575 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 14631 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 34944 # number of overall hits -system.cpu.l2cache.overall_hits::total 49575 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 4277 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 22713 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.846737 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.035218 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.044809 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.926764 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 14916 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 31426 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 46342 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 128239 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 128239 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 14916 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 36178 # 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number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses @@ -346,28 +346,28 @@ system.cpu.l2cache.demand_accesses::total 178906 # n system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.226201 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.428822 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.375518 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.956172 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.956172 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.226201 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.781597 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.722899 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.226201 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.781597 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.722899 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52019.639935 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52002.729714 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.409411 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.156340 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.156340 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52019.639935 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52053.908900 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52054.212437 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52063.627255 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52053.908900 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52054.212437 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -376,52 +376,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # 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number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 127812 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3992 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 127812 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 159934000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 868261000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028195000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4091214000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4091214000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 159934000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4959475000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5119409000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 159934000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4959475000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5119409000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.355233 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955602 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955602 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.714409 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.714409 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40063.627255 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40309.238626 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40270.836597 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.136879 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.136879 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40063.627255 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40063.627255 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 1d85fdbdf..ea44c1e9f 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202343 # Number of seconds simulated -sim_ticks 202342809000 # Number of ticks simulated -final_tick 202342809000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202242 # Number of seconds simulated +sim_ticks 202242260000 # Number of ticks simulated +final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1232815 # Simulator instruction rate (inst/s) -host_op_rate 1248778 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1856050290 # Simulator tick rate (ticks/s) -host_mem_usage 230736 # Number of bytes of host memory used -host_seconds 109.02 # Real time elapsed on the host +host_inst_rate 1258181 # Simulator instruction rate (inst/s) +host_op_rate 1274472 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1893298806 # Simulator tick rate (ticks/s) +host_mem_usage 233128 # Number of bytes of host memory used +host_seconds 106.82 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 665664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7906112 # Number of bytes read from this memory -system.physmem.bytes_read::total 8571776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 665664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 665664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5301376 # Number of bytes written to this memory -system.physmem.bytes_written::total 5301376 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10401 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123533 # Number of read requests responded to by this memory -system.physmem.num_reads::total 133934 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 82834 # Number of write requests responded to by this memory -system.physmem.num_writes::total 82834 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 3289783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39072859 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 42362642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3289783 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3289783 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 26199972 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 26199972 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 26199972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3289783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39072859 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 68562614 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 591488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7826624 # Number of bytes read from this memory +system.physmem.bytes_read::total 8418112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 591488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 591488 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5303552 # Number of bytes written to this memory +system.physmem.bytes_written::total 5303552 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 9242 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 122291 # Number of read requests responded to by this memory +system.physmem.num_reads::total 131533 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 82868 # Number of write requests responded to by this memory +system.physmem.num_writes::total 82868 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2924651 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 38699251 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 41623902 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2924651 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2924651 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 26223758 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 26223758 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 26223758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2924651 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 38699251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 67847660 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 404685618 # number of cpu cycles simulated +system.cpu.numCycles 404484520 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 134398962 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 58160248 # nu system.cpu.num_load_insts 37275867 # Number of load instructions system.cpu.num_store_insts 20884381 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 404685618 # Number of busy cycles +system.cpu.num_busy_cycles 404484520 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 184976 # number of replacements -system.cpu.icache.tagsinuse 2004.814192 # Cycle average of tags in use +system.cpu.icache.tagsinuse 2004.815325 # Cycle average of tags in use system.cpu.icache.total_refs 134366547 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 718.445478 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 144074079000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 2004.814192 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.978913 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.978913 # Average percentage of cache occupancy +system.cpu.icache.warmup_cycle 143972294000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 2004.815325 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.978914 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 134366547 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 187024 # n system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses system.cpu.icache.overall_misses::total 187024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2868177000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2868177000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2868177000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2868177000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2868177000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2868177000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2819681000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2819681000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2819681000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2819681000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2819681000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2819681000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15335.876679 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15335.876679 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15335.876679 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15335.876679 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15335.876679 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15335.876679 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15076.573060 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15076.573060 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15076.573060 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15076.573060 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15076.573060 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15076.573060 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187024 system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2494129000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2494129000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2494129000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2494129000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2494129000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2494129000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2445633000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2445633000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2445633000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2445633000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2445633000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2445633000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13335.876679 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13335.876679 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13335.876679 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13335.876679 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13335.876679 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13335.876679 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13076.573060 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13076.573060 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 146582 # number of replacements -system.cpu.dcache.tagsinuse 4087.652500 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4087.648350 # Cycle average of tags in use system.cpu.dcache.total_refs 57960842 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 384.666919 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 769040000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.652500 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997962 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997962 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997961 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits @@ -164,16 +164,16 @@ system.cpu.dcache.demand_misses::cpu.data 150663 # n system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses system.cpu.dcache.overall_misses::total 150663 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1523847000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1523847000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5622992000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5622992000 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475111000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1475111000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5619675000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5619675000 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7146839000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7146839000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7146839000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7146839000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7094786000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7094786000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7094786000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7094786000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) @@ -194,16 +194,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33491.878942 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33491.878942 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53468.791602 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53468.791602 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32420.734522 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32420.734522 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53437.250390 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53437.250390 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47435.926538 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47435.926538 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47435.926538 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47435.926538 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47090.433617 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47090.433617 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47090.433617 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47090.433617 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,8 +212,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 122378 # number of writebacks -system.cpu.dcache.writebacks::total 122378 # number of writebacks +system.cpu.dcache.writebacks::writebacks 123970 # number of writebacks +system.cpu.dcache.writebacks::total 123970 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses @@ -224,16 +224,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 150663 system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1432849000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1432849000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5412664000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5412664000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1384113000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1384113000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5409347000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5409347000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 375000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 375000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6845513000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6845513000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6845513000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6845513000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6793460000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6793460000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6793460000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6793460000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses @@ -244,70 +244,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31491.878942 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31491.878942 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51468.791602 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51468.791602 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30420.734522 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30420.734522 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51437.250390 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51437.250390 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45435.926538 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45435.926538 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45435.926538 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45435.926538 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45090.433617 # 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number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 480789000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1093974000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1574763000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5265313000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5265313000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 480789000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6359287000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6840076000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 480789000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6359287000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6840076000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 187024 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 45499 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 232523 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 122378 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 122378 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 123970 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 123970 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses @@ -316,28 +316,28 @@ system.cpu.l2cache.demand_accesses::total 337702 # n system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 150678 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 337702 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.055613 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.487879 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.140197 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.963453 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.963453 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.055613 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.819848 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.396604 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.055613 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.819848 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.396604 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.211326 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52001.982161 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52002.055278 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52002.211326 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.356180 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.500246 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52002.211326 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.356180 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.500246 # average overall miss latency +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.049416 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.462318 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.130211 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.962702 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.962702 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.049416 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.811605 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.389494 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.049416 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.811605 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.389494 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52022.181346 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52007.321131 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52011.857185 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.009876 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.009876 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52022.181346 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.267469 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52002.736956 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52022.181346 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.267469 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52002.736956 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -346,52 +346,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 82834 # number of writebacks -system.cpu.l2cache.writebacks::total 82834 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10401 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 22198 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 32599 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101335 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 101335 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10401 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 123533 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 133934 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10401 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 123533 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 133934 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 416063000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 887964000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1304027000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4053400000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4053400000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 416063000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4941364000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5357427000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 416063000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4941364000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5357427000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.055613 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.487879 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.140197 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.963453 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.963453 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.055613 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.819848 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.396604 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.055613 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.819848 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.396604 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.211326 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40001.982161 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40002.055278 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.211326 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.356180 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.500246 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.211326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.356180 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.500246 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 82868 # number of writebacks +system.cpu.l2cache.writebacks::total 82868 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9242 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21035 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 30277 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101256 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101256 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 9242 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 122291 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 131533 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 9242 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 122291 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 131533 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 369885000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 841554000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1211439000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4050241000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4050241000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 369885000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4891795000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5261680000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 369885000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4891795000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5261680000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.462318 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.130211 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962702 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962702 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811605 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.389494 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811605 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.389494 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40022.181346 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40007.321131 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40011.857185 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.009876 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.009876 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40022.181346 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.181346 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 77212a74e..9335161f5 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.998096 # Number of seconds simulated -sim_ticks 998095972500 # Number of ticks simulated -final_tick 998095972500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.987579 # Number of seconds simulated +sim_ticks 987579062500 # Number of ticks simulated +final_tick 987579062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135518 # Simulator instruction rate (inst/s) -host_op_rate 135518 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 74327611 # Simulator tick rate (ticks/s) -host_mem_usage 465236 # Number of bytes of host memory used -host_seconds 13428.33 # Real time elapsed on the host +host_inst_rate 79028 # Simulator instruction rate (inst/s) +host_op_rate 79028 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42888030 # Simulator tick rate (ticks/s) +host_mem_usage 458304 # Number of bytes of host memory used +host_seconds 23026.92 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 137579264 # Number of bytes read from this memory -system.physmem.bytes_read::total 137634240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125364928 # Number of bytes read from this memory +system.physmem.bytes_read::total 125419904 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67104640 # Number of bytes written to this memory -system.physmem.bytes_written::total 67104640 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65155520 # Number of bytes written to this memory +system.physmem.bytes_written::total 65155520 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2149676 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2150535 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1048510 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1048510 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 55081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 137841718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 137896799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 55081 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 55081 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 67232653 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 67232653 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 67232653 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 55081 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 137841718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 205129452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2150535 # Total number of read requests seen -system.physmem.writeReqs 1048510 # Total number of write requests seen -system.physmem.cpureqs 3199045 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 137634240 # Total number of bytes read from memory -system.physmem.bytesWritten 67104640 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 137634240 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 67104640 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 1104 # Number of read reqs serviced by write Q +system.physmem.num_reads::cpu.data 1958827 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1959686 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018055 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018055 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 55667 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 126941662 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 126997330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 55667 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 55667 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 65974991 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 65974991 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 65974991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 55667 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 126941662 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 192972321 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1959686 # Total number of read requests seen +system.physmem.writeReqs 1018055 # Total number of write requests seen +system.physmem.cpureqs 2977741 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125419904 # Total number of bytes read from memory +system.physmem.bytesWritten 65155520 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125419904 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65155520 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 577 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 134750 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 134519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 135461 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 133443 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 134821 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 134519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 135107 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 134152 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 133438 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 134313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 134956 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 130690 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 131784 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 134689 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 137104 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 135685 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 65615 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 65313 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 65943 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 64961 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 65149 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 64711 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 65179 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 65010 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 64600 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 65119 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 65708 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 64486 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 65220 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 66941 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 67682 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 66873 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 122432 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 123238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 122861 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 121276 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 122601 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 122224 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 124477 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 123481 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 121547 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 122168 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 122611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 120103 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 120483 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 121941 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 124488 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 123178 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 63120 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 63437 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 63830 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 63407 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 63139 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 62716 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 63395 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 63432 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 62525 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 63278 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 63961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 63327 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 63976 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64713 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 65307 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64492 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 998095934500 # Total gap between requests +system.physmem.totGap 987579010500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2150535 # Categorize read packet sizes +system.physmem.readPktSize::6 1959686 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1048510 # categorize write packet sizes +system.physmem.writePktSize::6 1018055 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1835130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 153641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 61976 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 38042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 24246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 14808 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8848 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2824 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1651837 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 192315 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 82006 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32950 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -138,80 +138,80 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 43501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 45260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 45551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 45580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 45588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 45587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 19730119710 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 92821713710 # Sum of mem lat for all requests -system.physmem.totBusLat 8597724000 # Total cycles spent in databus access -system.physmem.totBankLat 64493870000 # Total cycles spent in bank access -system.physmem.avgQLat 9179.23 # Average queueing delay per request -system.physmem.avgBankLat 30005.09 # Average bank access latency per request +system.physmem.totQLat 19599583947 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 85189869947 # Sum of mem lat for all requests +system.physmem.totBusLat 7836436000 # Total cycles spent in databus access +system.physmem.totBankLat 57753850000 # Total cycles spent in bank access +system.physmem.avgQLat 10004.34 # Average queueing delay per request +system.physmem.avgBankLat 29479.65 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 43184.32 # Average memory access latency -system.physmem.avgRdBW 137.90 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 67.23 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 137.90 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 67.23 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 43483.99 # Average memory access latency +system.physmem.avgRdBW 127.00 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 65.97 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 127.00 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 65.97 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 1.28 # Data bus utilization in percentage +system.physmem.busUtil 1.21 # Data bus utilization in percentage system.physmem.avgRdQLen 0.09 # Average read queue length over time -system.physmem.avgWrQLen 11.29 # Average write queue length over time -system.physmem.readRowHits 884898 # Number of row buffer hits during reads -system.physmem.writeRowHits 338451 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.28 # Row buffer hit rate for writes -system.physmem.avgGap 311998.09 # Average gap between requests +system.physmem.avgWrQLen 10.28 # Average write queue length over time +system.physmem.readRowHits 834542 # Number of row buffer hits during reads +system.physmem.writeRowHits 194109 # Number of row buffer hits during writes +system.physmem.readRowHitRate 42.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 19.07 # Row buffer hit rate for writes +system.physmem.avgGap 331653.76 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444628016 # DTB read hits +system.cpu.dtb.read_hits 444784364 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449525094 # DTB read accesses -system.cpu.dtb.write_hits 160917908 # DTB write hits +system.cpu.dtb.read_accesses 449681442 # DTB read accesses +system.cpu.dtb.write_hits 160833165 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162619212 # DTB write accesses -system.cpu.dtb.data_hits 605545924 # DTB hits +system.cpu.dtb.write_accesses 162534469 # DTB write accesses +system.cpu.dtb.data_hits 605617529 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612144306 # DTB accesses -system.cpu.itb.fetch_hits 232077768 # ITB hits +system.cpu.dtb.data_accesses 612215911 # DTB accesses +system.cpu.itb.fetch_hits 232120860 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 232077790 # ITB accesses +system.cpu.itb.fetch_accesses 232120882 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1996191946 # number of cpu cycles simulated +system.cpu.numCycles 1975158126 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 328934492 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 253834142 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 140072594 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 232648931 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 138176846 # Number of BTB hits +system.cpu.branch_predictor.lookups 328916009 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 253846257 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 140045817 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 232481413 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 138136467 # Number of BTB hits system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 59.392857 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 175181145 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 153753347 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1669765696 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 59.418284 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 175138589 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 153777420 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1669811898 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3045968313 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 235 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3046014515 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 237 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 580 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651043890 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617989866 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 121337623 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 12136513 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 133474136 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 81726090 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 62.023232 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139616626 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 582 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 650984890 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617988746 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 121313944 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 12133415 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 133447359 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 81752917 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 62.010775 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139622793 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1746553256 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1746581569 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7548952 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 419177402 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1577014544 # Number of cycles cpu stages are processed. -system.cpu.activity 79.001148 # Percentage of cycles cpu is active +system.cpu.timesIdled 7474420 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 398305853 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1576852273 # Number of cycles cpu stages are processed. +system.cpu.activity 79.834230 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -272,144 +272,144 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.096941 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.085383 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.096941 # CPI: Total CPI of All Threads -system.cpu.ipc 0.911626 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.085383 # CPI: Total CPI of All Threads +system.cpu.ipc 0.921334 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.911626 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 805412484 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1190779462 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 59.652553 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1063871870 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 932320076 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 46.704931 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1022192992 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 973998954 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 48.792851 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1586493403 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409698543 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.524005 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 973220385 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1022971561 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 51.246152 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.921334 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 784384186 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1190773940 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.287525 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1042820423 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 932337703 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 47.203193 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1001198544 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 973959582 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.310461 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1565492748 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409665378 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.740890 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 952315389 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1022842737 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 51.785360 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 667.791202 # Cycle average of tags in use -system.cpu.icache.total_refs 232076694 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 667.497042 # Cycle average of tags in use +system.cpu.icache.total_refs 232119756 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 270170.772992 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 270220.903376 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 667.791202 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.326070 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.326070 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 232076694 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 232076694 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 232076694 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 232076694 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 232076694 # number of overall hits -system.cpu.icache.overall_hits::total 232076694 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1072 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1072 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1072 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1072 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1072 # number of overall misses -system.cpu.icache.overall_misses::total 1072 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 56100000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 56100000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 56100000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 56100000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 56100000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 56100000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 232077766 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 232077766 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 232077766 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 232077766 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 232077766 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 232077766 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 667.497042 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.325926 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.325926 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 232119756 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 232119756 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 232119756 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 232119756 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 232119756 # number of overall hits +system.cpu.icache.overall_hits::total 232119756 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1104 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1104 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1104 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1104 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1104 # number of overall misses +system.cpu.icache.overall_misses::total 1104 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 58767000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 58767000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 58767000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 58767000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 58767000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 58767000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 232120860 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 232120860 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 232120860 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 232120860 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 232120860 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53230.978261 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53230.978261 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53230.978261 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 213 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54706.635623 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54706.635623 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107316 # number of replacements -system.cpu.dcache.tagsinuse 4082.375203 # Cycle average of tags in use -system.cpu.dcache.total_refs 595069266 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111412 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.310324 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12653266000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.375203 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996674 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996674 # 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average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21880.047149 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43804.822361 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43804.822361 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30173.980182 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30173.980182 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30173.980182 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30173.980182 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9234267 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4818811 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 358092 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65601 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1958827 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1959686 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35264420 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 61190782598 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 61226047018 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44920930070 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44920930070 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35264420 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 106111712668 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 106146977088 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35264420 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 106111712668 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 106146977088 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188436 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188532 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417460 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417460 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163151 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413463 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413463 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.236004 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.215059 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.236004 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39493.521537 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51377.836812 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51370.339900 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58698.152751 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58698.152751 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39493.521537 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54064.028080 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54058.208103 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39493.521537 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54064.028080 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54058.208103 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41052.875437 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51965.326261 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51957.371514 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57495.405160 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57495.405160 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41052.875437 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54171.048627 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54165.298465 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41052.875437 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54171.048627 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54165.298465 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 4dd96e908..4dfb5e529 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.622687 # Number of seconds simulated -sim_ticks 622686686500 # Number of ticks simulated -final_tick 622686686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.676099 # Number of seconds simulated +sim_ticks 676099363500 # Number of ticks simulated +final_tick 676099363500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 130099 # Simulator instruction rate (inst/s) -host_op_rate 130099 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46664017 # Simulator tick rate (ticks/s) -host_mem_usage 466244 # Number of bytes of host memory used -host_seconds 13344.04 # Real time elapsed on the host +host_inst_rate 178127 # Simulator instruction rate (inst/s) +host_op_rate 178127 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69371375 # Simulator tick rate (ticks/s) +host_mem_usage 459324 # Number of bytes of host memory used +host_seconds 9746.09 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138173120 # Number of bytes read from this memory -system.physmem.bytes_read::total 138234624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61504 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67206720 # Number of bytes written to this memory -system.physmem.bytes_written::total 67206720 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 961 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2158955 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2159916 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050105 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050105 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 98772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 221898305 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 221997077 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 98772 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 98772 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 107930234 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 107930234 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 107930234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 98772 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 221898305 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 329927311 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2159916 # Total number of read requests seen -system.physmem.writeReqs 1050105 # Total number of write requests seen -system.physmem.cpureqs 3210021 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 138234624 # Total number of bytes read from memory -system.physmem.bytesWritten 67206720 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 138234624 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 67206720 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 1101 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 61568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125805120 # Number of bytes read from this memory +system.physmem.bytes_read::total 125866688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61568 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65265216 # Number of bytes written to this memory +system.physmem.bytes_written::total 65265216 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 962 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965705 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966667 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019769 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019769 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 91064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 186074898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 186165961 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 91064 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 91064 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 96531989 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 96531989 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 96531989 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 91064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 186074898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 282697950 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966667 # Total number of read requests seen +system.physmem.writeReqs 1019769 # Total number of write requests seen +system.physmem.cpureqs 2986436 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125866688 # Total number of bytes read from memory +system.physmem.bytesWritten 65265216 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125866688 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65265216 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 625 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 135516 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 134944 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 135958 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 133984 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 135382 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 135012 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 135645 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 134678 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 134063 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 135260 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 135483 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 131205 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 132348 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 135290 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 137712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 136335 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 65727 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 65366 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 66027 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 65044 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 65255 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 64804 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 65281 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 65090 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 64712 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 65264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 65787 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 64601 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 65333 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 67038 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 67805 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 66971 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 123034 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 123551 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 123227 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 121682 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 123042 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 122572 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 124906 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 123907 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 121965 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 122878 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 123012 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 120476 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 120832 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 122358 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 124956 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 123644 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 63285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 63494 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 63931 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 63515 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 63255 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 62796 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 63501 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 63537 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 62612 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 63480 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 64069 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 63419 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64057 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64815 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 65441 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64562 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 622686634000 # Total gap between requests +system.physmem.totGap 676099295000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2159916 # Categorize read packet sizes +system.physmem.readPktSize::6 1966667 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1050105 # categorize write packet sizes +system.physmem.writePktSize::6 1019769 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1715217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 265103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 85338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 37466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 21744 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 13852 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 9060 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 6661 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1623 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1634338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 235140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 70255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 26277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -138,80 +138,80 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 45367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 45641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 45652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 45656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 45657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 45656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 45656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 45656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 45656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 45656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 45656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 43276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 44338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 22793561782 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 94682781782 # Sum of mem lat for all requests -system.physmem.totBusLat 8635260000 # Total cycles spent in databus access -system.physmem.totBankLat 63253960000 # Total cycles spent in bank access -system.physmem.avgQLat 10558.37 # Average queueing delay per request -system.physmem.avgBankLat 29300.32 # Average bank access latency per request +system.physmem.totQLat 20663639504 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 85829737504 # Sum of mem lat for all requests +system.physmem.totBusLat 7864168000 # Total cycles spent in databus access +system.physmem.totBankLat 57301930000 # Total cycles spent in bank access +system.physmem.avgQLat 10510.27 # Average queueing delay per request +system.physmem.avgBankLat 29145.83 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 43858.68 # Average memory access latency -system.physmem.avgRdBW 222.00 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 107.93 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 222.00 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 107.93 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 43656.11 # Average memory access latency +system.physmem.avgRdBW 186.17 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 96.53 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 186.17 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 96.53 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.06 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 10.91 # Average write queue length over time -system.physmem.readRowHits 893342 # Number of row buffer hits during reads -system.physmem.writeRowHits 340237 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.40 # Row buffer hit rate for writes -system.physmem.avgGap 193982.11 # Average gap between requests +system.physmem.busUtil 1.77 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.13 # Average read queue length over time +system.physmem.avgWrQLen 11.69 # Average write queue length over time +system.physmem.readRowHits 840809 # Number of row buffer hits during reads +system.physmem.writeRowHits 193935 # Number of row buffer hits during writes +system.physmem.readRowHitRate 42.77 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 19.02 # Row buffer hit rate for writes +system.physmem.avgGap 226390.02 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 610476386 # DTB read hits -system.cpu.dtb.read_misses 10761875 # DTB read misses +system.cpu.dtb.read_hits 623300287 # DTB read hits +system.cpu.dtb.read_misses 11248161 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 621238261 # DTB read accesses -system.cpu.dtb.write_hits 207269464 # DTB write hits -system.cpu.dtb.write_misses 6561537 # DTB write misses +system.cpu.dtb.read_accesses 634548448 # DTB read accesses +system.cpu.dtb.write_hits 212126260 # DTB write hits +system.cpu.dtb.write_misses 7156273 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 213831001 # DTB write accesses -system.cpu.dtb.data_hits 817745850 # DTB hits -system.cpu.dtb.data_misses 17323412 # DTB misses +system.cpu.dtb.write_accesses 219282533 # DTB write accesses +system.cpu.dtb.data_hits 835426547 # DTB hits +system.cpu.dtb.data_misses 18404434 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 835069262 # DTB accesses -system.cpu.itb.fetch_hits 398378101 # ITB hits -system.cpu.itb.fetch_misses 55 # ITB misses +system.cpu.dtb.data_accesses 853830981 # DTB accesses +system.cpu.itb.fetch_hits 409165317 # ITB hits +system.cpu.itb.fetch_misses 53 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 398378156 # ITB accesses +system.cpu.itb.fetch_accesses 409165370 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,245 +225,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1245373374 # number of cpu cycles simulated +system.cpu.numCycles 1352198728 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 378146140 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 290510585 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18737073 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 264395160 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 259999350 # Number of BTB hits +system.cpu.BPredUnit.lookups 392126599 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 302845458 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 19199722 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 274650283 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 270818962 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 25131917 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 6182 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 409812987 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3135210650 # Number of instructions fetch has processed -system.cpu.fetch.Branches 378146140 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 285131267 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 571966611 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 132239561 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 126137605 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1394 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 398378101 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10155921 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1214707352 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.581042 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.162326 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 25776268 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6145 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 421462775 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3238747115 # Number of instructions fetch has processed +system.cpu.fetch.Branches 392126599 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 296595230 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 591261083 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 148936596 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 163448952 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 730 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1316 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 409165317 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10196267 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1298229870 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.494741 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.143526 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 642740741 52.91% 52.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42508733 3.50% 56.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22198972 1.83% 58.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 40683898 3.35% 61.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 126205169 10.39% 71.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 63532228 5.23% 77.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40428272 3.33% 80.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30073881 2.48% 83.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 206335458 16.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 706968787 54.46% 54.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 44358932 3.42% 57.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22743833 1.75% 59.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 41944085 3.23% 62.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 132056857 10.17% 73.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 64435006 4.96% 77.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41239075 3.18% 81.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30635006 2.36% 83.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 213848289 16.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1214707352 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.303641 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.517486 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 437634335 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 113109865 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542282236 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 14893078 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 106787838 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 60009942 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1008 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3056719356 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2151 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 106787838 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 458205445 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 68879857 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5925 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535635557 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 45192730 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2974950452 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 455085 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1725044 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 40939895 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2225174239 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3842201349 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3840803931 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1397418 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1298229870 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.289992 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.395171 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 455239490 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 145264666 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 557656082 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18015537 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 122054095 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 61382914 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1012 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3154733525 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2110 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 122054095 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 478678718 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 92924622 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7988 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 549590922 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 54973525 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3070816575 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 560752 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1743859 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 49056518 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2295520192 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3973370931 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3971968228 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1402703 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 848971276 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 208 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 208 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 94220163 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 674209051 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 250003668 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 60248313 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 34574137 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2672716058 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 181 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2475684354 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3185220 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 926051369 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 394490469 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 152 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1214707352 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.038091 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.971432 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 919317229 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 211 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 209 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 118384405 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 691487195 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 258255800 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68719353 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 37210437 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2756294295 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 187 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2536632821 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3950694 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1007358741 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 432150244 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 158 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1298229870 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.953917 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.961710 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 391612222 32.24% 32.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 190116739 15.65% 47.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 180710183 14.88% 62.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153608021 12.65% 75.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 136709031 11.25% 86.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80377873 6.62% 93.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 61799975 5.09% 98.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14388617 1.18% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5384691 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 442263739 34.07% 34.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 208903385 16.09% 50.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 191557841 14.76% 64.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 152463661 11.74% 76.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 137672348 10.60% 87.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 81203098 6.25% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 63863451 4.92% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15081593 1.16% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5220754 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1214707352 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1298229870 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2236018 11.81% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12183595 64.36% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4510642 23.83% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2156518 11.37% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12254343 64.62% 76.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4551680 24.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1615926808 65.27% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 102 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 284 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 171 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 30 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 638812583 25.80% 91.08% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 220944337 8.92% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1658475044 65.38% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 107 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 273 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 163 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 34 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 652209568 25.71% 91.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 225947593 8.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2475684354 # Type of FU issued -system.cpu.iq.rate 1.987905 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18930255 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007646 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6186206687 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3597520072 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2374361589 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1984848 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1351695 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 870010 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2493639169 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 975440 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 56324993 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2536632821 # Type of FU issued +system.cpu.iq.rate 1.875932 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18962541 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007475 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6392425036 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3762406457 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2431792022 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1983711 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1351957 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 870252 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2554620629 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 974733 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62690136 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 229613388 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 251555 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 105716 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 89275166 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 246891532 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 263108 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 106999 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 97527298 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 232 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 90239 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 177 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1449625 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 106787838 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30509174 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1004696 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2814392916 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 16951249 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 674209051 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 250003668 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 181 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 211284 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14280 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 105716 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 13148912 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8849149 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 21998061 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2424970447 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 621239857 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 50713907 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 122054095 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 42236040 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1169448 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2901607263 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 18449890 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 691487195 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 258255800 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 187 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 295034 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 19978 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 106999 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 13433299 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8961049 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 22394348 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2485079596 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 634549945 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 51553225 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 141676677 # number of nop insts executed -system.cpu.iew.exec_refs 835070896 # number of memory reference insts executed -system.cpu.iew.exec_branches 296780799 # Number of branches executed -system.cpu.iew.exec_stores 213831039 # Number of stores executed -system.cpu.iew.exec_rate 1.947183 # Inst execution rate -system.cpu.iew.wb_sent 2403689836 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2375231599 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1360982490 # num instructions producing a value -system.cpu.iew.wb_consumers 1724379175 # num instructions consuming a value +system.cpu.iew.exec_nop 145312781 # number of nop insts executed +system.cpu.iew.exec_refs 853832523 # number of memory reference insts executed +system.cpu.iew.exec_branches 304694140 # Number of branches executed +system.cpu.iew.exec_stores 219282578 # Number of stores executed +system.cpu.iew.exec_rate 1.837806 # Inst execution rate +system.cpu.iew.wb_sent 2461943508 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2432662274 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1394848463 # num instructions producing a value +system.cpu.iew.wb_consumers 1766930878 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.907245 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.789259 # average fanout of values written-back +system.cpu.iew.wb_rate 1.799042 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.789419 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 754743358 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 860868467 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 18736187 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1107919514 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.642520 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.504559 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 19198826 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1176175775 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.547201 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.484504 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 582245438 52.55% 52.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 181606604 16.39% 68.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 90875132 8.20% 77.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53034266 4.79% 81.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36917610 3.33% 85.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 29689254 2.68% 87.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22142026 2.00% 89.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22921878 2.07% 92.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 88487306 7.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 658247718 55.97% 55.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 175915600 14.96% 70.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 90578875 7.70% 78.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53177308 4.52% 83.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 35329719 3.00% 86.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23851430 2.03% 88.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 23326017 1.98% 90.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23350140 1.99% 92.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 92398968 7.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1107919514 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1176175775 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -474,373 +475,371 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 88487306 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 92398968 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3508176492 # The number of ROB reads -system.cpu.rob.rob_writes 5255937619 # The number of ROB writes -system.cpu.timesIdled 768601 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30666022 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3678646200 # The number of ROB reads +system.cpu.rob.rob_writes 5483460601 # The number of ROB writes +system.cpu.timesIdled 829567 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 53968858 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.717363 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.717363 # CPI: Total CPI of All Threads -system.cpu.ipc 1.393995 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.393995 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3260141632 # number of integer regfile reads -system.cpu.int_regfile_writes 1905484731 # number of integer regfile writes -system.cpu.fp_regfile_reads 51179 # number of floating regfile reads -system.cpu.fp_regfile_writes 563 # number of floating regfile writes +system.cpu.cpi 0.778897 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.778897 # CPI: Total CPI of All Threads +system.cpu.ipc 1.283867 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.283867 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3341460388 # number of integer regfile reads +system.cpu.int_regfile_writes 1950187380 # number of integer regfile writes +system.cpu.fp_regfile_reads 51936 # number of floating regfile reads +system.cpu.fp_regfile_writes 538 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 770.400860 # Cycle average of tags in use -system.cpu.icache.total_refs 398376643 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 961 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 414543.853278 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 771.801258 # Cycle average of tags in use +system.cpu.icache.total_refs 409163812 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 962 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 425326.207900 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 770.400860 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.376172 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.376172 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 398376643 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 398376643 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 398376643 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 398376643 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 398376643 # number of overall hits -system.cpu.icache.overall_hits::total 398376643 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1458 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1458 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1458 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1458 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1458 # number of overall misses -system.cpu.icache.overall_misses::total 1458 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 53978500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 53978500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 53978500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 53978500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 53978500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 53978500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 398378101 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 398378101 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 398378101 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 398378101 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 398378101 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 398378101 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 771.801258 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.376856 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.376856 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 409163812 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 409163812 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 409163812 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 409163812 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 409163812 # number of overall hits +system.cpu.icache.overall_hits::total 409163812 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1504 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1504 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1504 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1504 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1504 # number of overall misses +system.cpu.icache.overall_misses::total 1504 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 80548999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 80548999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 80548999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 80548999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 80548999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 80548999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 409165316 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 409165316 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 409165316 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 409165316 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 409165316 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 409165316 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37022.290809 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 37022.290809 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 37022.290809 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 37022.290809 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 37022.290809 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 37022.290809 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53556.515293 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53556.515293 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53556.515293 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53556.515293 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53556.515293 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53556.515293 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1029 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 147 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 497 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 497 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 497 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 497 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 497 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 497 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 961 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 961 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 961 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 961 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 961 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 961 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37991000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 37991000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37991000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 37991000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37991000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 37991000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 542 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 542 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 542 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 542 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 542 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 542 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 962 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 962 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 962 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 962 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 962 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 962 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 57069999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 57069999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 57069999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 57069999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 57069999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 57069999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39532.778356 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39532.778356 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39532.778356 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39532.778356 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39532.778356 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39532.778356 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59324.323285 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59324.323285 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59324.323285 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 59324.323285 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59324.323285 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 59324.323285 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9176449 # number of replacements -system.cpu.dcache.tagsinuse 4086.538678 # Cycle average of tags in use -system.cpu.dcache.total_refs 700391806 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9180545 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 76.290874 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5478544000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.538678 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997690 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997690 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 544376569 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 544376569 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 156015231 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 156015231 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 700391800 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 700391800 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 700391800 # number of overall hits -system.cpu.dcache.overall_hits::total 700391800 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9752930 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9752930 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4713271 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4713271 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 14466201 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 14466201 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 14466201 # number of overall misses -system.cpu.dcache.overall_misses::total 14466201 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 164485394500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 164485394500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 131300824319 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 131300824319 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 62500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 62500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 295786218819 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 295786218819 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 295786218819 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 295786218819 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 554129499 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 554129499 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 9177397 # number of replacements +system.cpu.dcache.tagsinuse 4086.580271 # Cycle average of tags in use +system.cpu.dcache.total_refs 703801568 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9181493 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 76.654371 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5761373000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4086.580271 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997700 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997700 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 548148518 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 548148518 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155653046 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155653046 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 703801564 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 703801564 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 703801564 # number of overall hits +system.cpu.dcache.overall_hits::total 703801564 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11295128 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11295128 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5075456 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5075456 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 16370584 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16370584 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 16370584 # number of overall misses +system.cpu.dcache.overall_misses::total 16370584 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 280321207500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 280321207500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 216815235389 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 216815235389 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 51500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 51500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 497136442889 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 497136442889 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 497136442889 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 497136442889 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 559443646 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 559443646 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 8 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 8 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 714858001 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 714858001 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 714858001 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 714858001 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017600 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.017600 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029324 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029324 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.020236 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.020236 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.020236 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.020236 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16865.228654 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16865.228654 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27857.686163 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27857.686163 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20446.710150 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20446.710150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20446.710150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20446.710150 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 200506 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3116753 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 10498 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65116 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.099448 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 47.864626 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 720172148 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 720172148 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 720172148 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 720172148 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020190 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020190 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031578 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.031578 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.022731 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.022731 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.022731 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.022731 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24817.886747 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24817.886747 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42718.375529 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42718.375529 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30367.666962 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30367.666962 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30367.666962 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30367.666962 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10443209 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5645556 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 732857 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65131 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.249996 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 86.680014 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3416510 # number of writebacks -system.cpu.dcache.writebacks::total 3416510 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2456183 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2456183 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2829474 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2829474 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 5285657 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 5285657 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 5285657 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 5285657 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296747 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296747 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883797 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883797 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3725010 # number of writebacks +system.cpu.dcache.writebacks::total 3725010 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3997316 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3997316 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3191776 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3191776 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7189092 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7189092 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7189092 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7189092 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7297812 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7297812 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883680 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883680 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180544 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180544 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180544 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180544 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 83795715500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 83795715500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 42424545344 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 42424545344 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 28500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 28500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126220260844 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 126220260844 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126220260844 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 126220260844 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013168 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013168 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 9181492 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9181492 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9181492 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9181492 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 149509028500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 149509028500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65361082800 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 65361082800 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 49500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 49500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214870111300 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 214870111300 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214870111300 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 214870111300 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013045 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013045 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011720 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011720 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.125000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.125000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012842 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012842 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11483.982588 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11483.982588 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22520.762770 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22520.762770 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 28500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 28500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13748.669016 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13748.669016 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13748.669016 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13748.669016 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012749 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012749 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012749 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012749 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20486.829272 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20486.829272 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34698.612716 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34698.612716 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 49500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 49500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23402.526659 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23402.526659 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23402.526659 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23402.526659 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2143493 # number of replacements -system.cpu.l2cache.tagsinuse 30938.495436 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8540491 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2173189 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.929935 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 108738439000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14386.053768 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 29.461670 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16522.979998 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.439028 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000899 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.504241 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.944168 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5920330 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5920330 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3416510 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3416510 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1101260 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1101260 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7021590 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7021590 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7021590 # number of overall hits -system.cpu.l2cache.overall_hits::total 7021590 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 961 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1376412 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1377373 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 782543 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 782543 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 961 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2158955 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2159916 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 961 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2158955 # number of overall misses -system.cpu.l2cache.overall_misses::total 2159916 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37023500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 69752519000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 69789542500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 38825223000 # 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number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3416510 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883803 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1883803 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 961 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9180545 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9181506 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 961 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9180545 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9181506 # number of overall (read+write) accesses +system.cpu.l2cache.replacements 1933961 # number of replacements +system.cpu.l2cache.tagsinuse 31328.043846 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50291.804137 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 50286.569246 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 138175 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214094 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214177 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 58314.449064 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67499.766079 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67492.350197 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67011.047781 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67011.047781 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 58314.449064 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67307.050651 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67302.651898 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 58314.449064 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67307.050651 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67302.651898 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 4214 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 32.789511 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # 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number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 962 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1965705 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1966667 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 962 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1965705 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1966667 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 43990994 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 65246294234 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 65290285228 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 42161089674 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 42161089674 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43990994 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107407383908 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 107451374902 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43990994 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107407383908 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 107451374902 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188634 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188741 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415406 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415406 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163141 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163251 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411497 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411497 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235166 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.235246 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214094 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214177 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235166 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.235246 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34927.113424 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47010.516786 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 47002.086136 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46023.406962 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46023.406962 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34927.113424 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46652.725224 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 46647.508209 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34927.113424 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46652.725224 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 46647.508209 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214094 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214177 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45728.683992 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54802.476653 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54795.150812 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54392.071650 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54392.071650 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 45728.683992 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54640.642369 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54636.283063 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45728.683992 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54640.642369 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54636.283063 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 78e7b43f1..3a71ce0c3 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.631385 # Number of seconds simulated -sim_ticks 2631384990000 # Number of ticks simulated -final_tick 2631384990000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.623386 # Number of seconds simulated +sim_ticks 2623386226000 # Number of ticks simulated +final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1011793 # Simulator instruction rate (inst/s) -host_op_rate 1011793 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1463043658 # Simulator tick rate (ticks/s) -host_mem_usage 219388 # Number of bytes of host memory used -host_seconds 1798.57 # Real time elapsed on the host +host_inst_rate 1789114 # Simulator instruction rate (inst/s) +host_op_rate 1789114 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2579177735 # Simulator tick rate (ticks/s) +host_mem_usage 217052 # Number of bytes of host memory used +host_seconds 1017.14 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 137580288 # Number of bytes read from this memory -system.physmem.bytes_read::total 137631616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125367104 # Number of bytes read from this memory +system.physmem.bytes_read::total 125418432 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67105600 # Number of bytes written to this memory -system.physmem.bytes_written::total 67105600 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65156928 # Number of bytes written to this memory +system.physmem.bytes_written::total 65156928 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2149692 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2150494 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1048525 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1048525 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19506 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 52284363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52303869 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19506 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19506 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 25502008 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 25502008 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 25502008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19506 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 52284363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 77805877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 1958861 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1959663 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018077 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018077 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47788276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47807841 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19566 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19566 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 24836956 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 24836956 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 24836956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47788276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 72644797 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 5262769980 # number of cpu cycles simulated +system.cpu.numCycles 5246772452 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1819780127 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 611922547 # nu system.cpu.num_load_insts 449492741 # Number of load instructions system.cpu.num_store_insts 162429806 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5262769980 # Number of busy cycles +system.cpu.num_busy_cycles 5246772452 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 612.470356 # Cycle average of tags in use +system.cpu.icache.tagsinuse 612.458646 # Cycle average of tags in use system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 612.470356 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.299058 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.299058 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.299052 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 802 # n system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44120000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44120000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44120000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44120000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44120000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44120000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44182000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44182000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44182000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44182000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44182000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44182000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55012.468828 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55012.468828 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55012.468828 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55012.468828 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55012.468828 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55012.468828 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55089.775561 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55089.775561 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55089.775561 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55089.775561 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55089.775561 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55089.775561 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802 system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42516000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42516000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42516000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42516000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42516000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42516000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42578000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42578000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42578000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42578000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42578000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42578000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53012.468828 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53012.468828 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53012.468828 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53012.468828 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53012.468828 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53012.468828 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53089.775561 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53089.775561 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107638 # number of replacements -system.cpu.dcache.tagsinuse 4079.313701 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4079.262869 # Cycle average of tags in use system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 40977019000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4079.313701 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995926 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995926 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995914 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 9111734 # n system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses system.cpu.dcache.overall_misses::total 9111734 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 151059345000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 151059345000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57691387000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57691387000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 208750732000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 208750732000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 208750732000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 208750732000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143374726000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143374726000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57377180000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57377180000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200751906000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200751906000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200751906000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200751906000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20915.353925 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20915.353925 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30535.529714 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30535.529714 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22910.099439 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22910.099439 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22910.099439 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22910.099439 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19851.358009 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19851.358009 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30369.222789 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30369.222789 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22032.239528 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22032.239528 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22032.239528 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22032.239528 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3389919 # number of writebacks -system.cpu.dcache.writebacks::total 3389919 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3693497 # number of writebacks +system.cpu.dcache.writebacks::total 3693497 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 136614517000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 136614517000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53912747000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53912747000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 190527264000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 190527264000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 190527264000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 190527264000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128929898000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 128929898000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53598540000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53598540000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182528438000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 182528438000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182528438000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 182528438000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses @@ -258,65 +258,65 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18915.353925 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18915.353925 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28535.529714 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28535.529714 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20910.099439 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20910.099439 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20910.099439 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20910.099439 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17851.358009 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17851.358009 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28369.222789 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28369.222789 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2133721 # number of replacements -system.cpu.l2cache.tagsinuse 30159.988647 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8449191 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2163414 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.905490 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 496965874000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14375.657027 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 37.778500 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15746.553119 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.438710 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001153 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.480547 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.920410 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5861531 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5861531 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3389919 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3389919 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1100511 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1100511 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 6962042 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6962042 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 6962042 # number of overall hits -system.cpu.l2cache.overall_hits::total 6962042 # number of overall hits +system.cpu.l2cache.replacements 1926937 # number of replacements +system.cpu.l2cache.tagsinuse 30535.257456 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8959453 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1956729 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.578791 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 15221.890655 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.464535 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.931862 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 6044854 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6044854 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3693497 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3693497 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108019 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1108019 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7152873 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7152873 # 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number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2150494 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1958861 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1959663 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 802 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2149692 # number of overall misses -system.cpu.l2cache.overall_misses::total 2150494 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41714000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70776793000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 70818507000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41018317000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41018317000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 41714000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 111795110000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 111836824000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 41714000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 111795110000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 111836824000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 1958861 # number of overall misses +system.cpu.l2cache.overall_misses::total 1959663 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41776000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61258944000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 61300720000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40629030000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 40629030000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 41776000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 101887974000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 101929750000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 41776000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 101887974000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 101929750000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 802 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7222414 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7223216 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3389919 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3389919 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3693497 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3693497 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889320 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889320 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses @@ -326,27 +326,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 802 system.cpu.l2cache.overall_accesses::cpu.data 9111734 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9112536 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188425 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.188515 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417509 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.417509 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163042 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163135 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413536 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.413536 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.235926 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.235993 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214982 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.215051 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.235926 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.235993 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52012.468828 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52007.992605 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52007.995241 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.315666 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.315666 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52012.468828 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52005.175625 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52005.178345 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52012.468828 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52005.175625 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52005.178345 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214982 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.215051 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52089.775561 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52021.930093 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52021.976269 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.763725 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.763725 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52089.775561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52013.886641 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52013.917699 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52089.775561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52013.886641 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52013.917699 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -355,52 +355,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1048525 # number of writebacks -system.cpu.l2cache.writebacks::total 1048525 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1018077 # number of writebacks +system.cpu.l2cache.writebacks::total 1018077 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1360883 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1361685 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 788809 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 788809 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177560 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1178362 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781301 # 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number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1959663 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32152000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47128224000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47160376000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31253418000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31253418000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32152000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78381642000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 78413794000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32152000 # 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mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235926 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.235993 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214982 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.215051 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235926 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.235993 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40012.468828 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40007.992605 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40007.995241 # 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mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40089.775561 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.930093 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40021.976269 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.763725 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.763725 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40089.775561 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40089.775561 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index a3e0cc680..21ff71fb2 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.473434 # Number of seconds simulated -sim_ticks 473433799500 # Number of ticks simulated -final_tick 473433799500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.515058 # Number of seconds simulated +sim_ticks 515058060000 # Number of ticks simulated +final_tick 515058060000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169995 # Simulator instruction rate (inst/s) -host_op_rate 189642 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52106394 # Simulator tick rate (ticks/s) -host_mem_usage 499160 # Number of bytes of host memory used -host_seconds 9085.91 # Real time elapsed on the host -sim_insts 1544563083 # Number of instructions simulated -sim_ops 1723073895 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 156296704 # Number of bytes read from this memory -system.physmem.bytes_read::total 156345088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48384 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 71931712 # Number of bytes written to this memory -system.physmem.bytes_written::total 71931712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 756 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2442136 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2442892 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1123933 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1123933 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 102198 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 330134232 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 330236430 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 102198 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 102198 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 151936157 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 151936157 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 151936157 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 102198 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 330134232 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 482172587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2442892 # Total number of read requests seen -system.physmem.writeReqs 1123933 # Total number of write requests seen -system.physmem.cpureqs 3566825 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 156345088 # Total number of bytes read from memory -system.physmem.bytesWritten 71931712 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 156345088 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 71931712 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 1286 # Number of read reqs serviced by write Q +host_inst_rate 166099 # Simulator instruction rate (inst/s) +host_op_rate 185296 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55388247 # Simulator tick rate (ticks/s) +host_mem_usage 494292 # Number of bytes of host memory used +host_seconds 9299.05 # Real time elapsed on the host +sim_insts 1544563078 # Number of instructions simulated +sim_ops 1723073890 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 48320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 144392128 # Number of bytes read from this memory +system.physmem.bytes_read::total 144440448 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48320 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70617600 # Number of bytes written to this memory +system.physmem.bytes_written::total 70617600 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 755 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2256127 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2256882 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1103400 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1103400 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 93815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 280341459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 280435274 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 93815 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 93815 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 137106096 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 137106096 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 137106096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 93815 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 280341459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 417541370 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2256882 # Total number of read requests seen +system.physmem.writeReqs 1103400 # Total number of write requests seen +system.physmem.cpureqs 3360282 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 144440448 # Total number of bytes read from memory +system.physmem.bytesWritten 70617600 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 144440448 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 70617600 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 637 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 151934 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 156031 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 154856 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 153024 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 150249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 152372 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 153472 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 154746 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 153379 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 151879 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 152199 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 152305 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 150118 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 153271 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 150713 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 151058 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 70393 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 72288 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 71658 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 69978 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 69490 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 69799 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 70024 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 70449 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 69754 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 69615 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 69971 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 69698 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 68976 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 71736 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 70217 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 69887 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 140407 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 144367 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 142491 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 141453 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 138510 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 140931 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 142120 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 141749 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 141832 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 140373 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 140948 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 141413 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 137790 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 141680 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 139536 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 140645 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 69366 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 70506 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 69820 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 68968 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 67927 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 68673 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 68853 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 68680 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 68439 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 68530 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 68800 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 68663 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 67351 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 70531 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 69216 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 69077 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 473433771000 # Total gap between requests +system.physmem.totGap 515058007000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2442892 # Categorize read packet sizes +system.physmem.readPktSize::6 2256882 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1123933 # categorize write packet sizes +system.physmem.writePktSize::6 1103400 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1613567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 411043 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 122672 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 76227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 63723 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 50754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 36534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 28949 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 23035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 15102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1580398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 450395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 158442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 66982 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -138,60 +138,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 43358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 46512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 48422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 48759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 48833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 48858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 48865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 48867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 48867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 48867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 48867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 48867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 48867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 48866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 45630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 47618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 47968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 47973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 47974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 47973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 39045821973 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 121584903973 # Sum of mem lat for all requests -system.physmem.totBusLat 9766424000 # Total cycles spent in databus access -system.physmem.totBankLat 72772658000 # Total cycles spent in bank access -system.physmem.avgQLat 15991.86 # Average queueing delay per request -system.physmem.avgBankLat 29805.24 # Average bank access latency per request +system.physmem.totQLat 27231628654 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 103251704654 # Sum of mem lat for all requests +system.physmem.totBusLat 9024980000 # Total cycles spent in databus access +system.physmem.totBankLat 66995096000 # Total cycles spent in bank access +system.physmem.avgQLat 12069.45 # Average queueing delay per request +system.physmem.avgBankLat 29693.18 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 49797.10 # Average memory access latency -system.physmem.avgRdBW 330.24 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 151.94 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 330.24 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 151.94 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 45762.63 # Average memory access latency +system.physmem.avgRdBW 280.44 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 137.11 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 280.44 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 137.11 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.01 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.26 # Average read queue length over time -system.physmem.avgWrQLen 10.90 # Average write queue length over time -system.physmem.readRowHits 966664 # Number of row buffer hits during reads -system.physmem.writeRowHits 336338 # Number of row buffer hits during writes -system.physmem.readRowHitRate 39.59 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 29.93 # Row buffer hit rate for writes -system.physmem.avgGap 132732.55 # Average gap between requests +system.physmem.busUtil 2.61 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.20 # Average read queue length over time +system.physmem.avgWrQLen 11.32 # Average write queue length over time +system.physmem.readRowHits 919391 # Number of row buffer hits during reads +system.physmem.writeRowHits 189315 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.75 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 17.16 # Row buffer hit rate for writes +system.physmem.avgGap 153278.21 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,140 +235,142 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 946867600 # number of cpu cycles simulated +system.cpu.numCycles 1030116121 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 299593765 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 245452602 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16045022 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 170764551 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 155662191 # Number of BTB hits +system.cpu.BPredUnit.lookups 307748972 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 253170818 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16168830 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 178836343 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 162524431 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 18346296 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 201 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 291830558 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2150759454 # Number of instructions fetch has processed -system.cpu.fetch.Branches 299593765 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 174008487 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 427702866 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 82463506 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 122599229 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 88 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 282801731 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5377782 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 908156186 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.634401 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.243337 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 18394581 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 234 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 302711500 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2208582342 # Number of instructions fetch has processed +system.cpu.fetch.Branches 307748972 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 180919012 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 439713036 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 91477277 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 153604124 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 69 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 292882660 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6106896 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 969047070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.529561 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.216174 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 480453401 52.90% 52.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 22859151 2.52% 55.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38736937 4.27% 59.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 47688218 5.25% 64.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 40498646 4.46% 69.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46746329 5.15% 74.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38999717 4.29% 78.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18064778 1.99% 80.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174109009 19.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 529334144 54.62% 54.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25043926 2.58% 57.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39264186 4.05% 61.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48337631 4.99% 66.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43062270 4.44% 70.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 47882627 4.94% 75.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 39313310 4.06% 79.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19335068 2.00% 81.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 177473908 18.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 908156186 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316405 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.271447 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 320351849 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 103310609 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 403372314 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 15098642 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 66022772 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46034722 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 704 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2339352792 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2529 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 66022772 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 341796573 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 48717971 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14906 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 395855837 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 55748127 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2282794185 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 39847 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4611517 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 42695661 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2257537981 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10537280026 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10537275559 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4467 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706320026 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 551217955 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 838 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 835 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 129599333 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 622569059 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 218142237 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 84983278 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 64739003 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2182778805 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 865 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2010794421 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4810108 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 455220170 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1060725588 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 683 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 908156186 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.214150 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.929063 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 969047070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.298752 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.144013 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 334775915 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 131820236 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 409429631 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20003640 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 73017648 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46459880 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 721 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2395467722 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2521 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 73017648 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 358478616 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61310545 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17059 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 404218624 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 72004578 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2331266224 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 128849 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5208113 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 58805545 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2308002536 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10761064902 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10761060796 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4106 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1706320018 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 601682518 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1074 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1071 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 160130696 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 634128265 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 221560674 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 87711423 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 69100091 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2223438682 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1093 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2032725138 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5162970 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 495697928 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1172411676 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 912 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 969047070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.097654 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906175 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 247277493 27.23% 27.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 133932127 14.75% 41.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 156228000 17.20% 59.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 116195915 12.79% 71.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 125706835 13.84% 85.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 75923793 8.36% 94.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 39533015 4.35% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10697910 1.18% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2661098 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 282916763 29.20% 29.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 152378116 15.72% 44.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 162831122 16.80% 61.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119917560 12.37% 74.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 126106053 13.01% 87.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 74105592 7.65% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38169342 3.94% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10016302 1.03% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2606220 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 908156186 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 969047070 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 703286 2.81% 2.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4771 0.02% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19012865 76.06% 78.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5274676 21.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 856823 3.47% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4485 0.02% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18914760 76.65% 80.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4900553 19.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1230823853 61.21% 61.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 930532 0.05% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1244244744 61.21% 61.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 933049 0.05% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued @@ -390,475 +392,475 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.26% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 72 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 30 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 31 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 15 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 585374477 29.11% 90.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193665439 9.63% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 593617066 29.20% 90.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193930151 9.54% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2010794421 # Type of FU issued -system.cpu.iq.rate 2.123628 # Inst issue rate -system.cpu.iq.fu_busy_cnt 24995598 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012431 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4959550302 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2638184259 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1953078988 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 432 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 858 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 164 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2035789802 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 217 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63764603 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2032725138 # Type of FU issued +system.cpu.iq.rate 1.973297 # Inst issue rate +system.cpu.iq.fu_busy_cnt 24676621 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012140 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5064336479 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2719325477 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1969225475 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 458 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 784 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 183 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2057401528 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 231 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63678179 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 136642278 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 284566 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 187935 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 43295180 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 148201485 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 301622 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 191452 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 46713618 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 386993 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3827005 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 66022772 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23145640 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1044628 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2182779773 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 5713944 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 622569059 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 218142237 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 798 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 173655 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 44651 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 187935 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8601247 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 10177350 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18778597 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1981378382 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 570935022 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29416039 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 73017648 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27244100 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1491546 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2223439933 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6134188 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 634128265 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 221560674 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1025 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 470403 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 82153 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 191452 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8679785 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 10261943 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18941728 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2001081478 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 578449212 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 31643660 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 103 # number of nop insts executed -system.cpu.iew.exec_refs 761630934 # number of memory reference insts executed -system.cpu.iew.exec_branches 237544754 # Number of branches executed -system.cpu.iew.exec_stores 190695912 # Number of stores executed -system.cpu.iew.exec_rate 2.092561 # Inst execution rate -system.cpu.iew.wb_sent 1962075581 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1953079152 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1293757962 # num instructions producing a value -system.cpu.iew.wb_consumers 2065123050 # num instructions consuming a value +system.cpu.iew.exec_nop 158 # number of nop insts executed +system.cpu.iew.exec_refs 769422153 # number of memory reference insts executed +system.cpu.iew.exec_branches 239265351 # Number of branches executed +system.cpu.iew.exec_stores 190972941 # Number of stores executed +system.cpu.iew.exec_rate 1.942579 # Inst execution rate +system.cpu.iew.wb_sent 1978131551 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1969225658 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1302526017 # num instructions producing a value +system.cpu.iew.wb_consumers 2074719324 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.062674 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.626480 # average fanout of values written-back +system.cpu.iew.wb_rate 1.911654 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.627808 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 459769347 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 182 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16044351 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 842133415 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.046082 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.757625 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 500462812 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 181 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 16168149 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 896029423 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.923010 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.718948 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 351966566 41.79% 41.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 194208080 23.06% 64.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73932281 8.78% 73.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35396184 4.20% 77.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18675547 2.22% 80.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 31087553 3.69% 83.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19760319 2.35% 86.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10744228 1.28% 87.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106362657 12.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 406862083 45.41% 45.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193059933 21.55% 66.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73977423 8.26% 75.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35390708 3.95% 79.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18895903 2.11% 81.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30453376 3.40% 84.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19841212 2.21% 86.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11401039 1.27% 88.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106147746 11.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 842133415 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563101 # Number of instructions committed -system.cpu.commit.committedOps 1723073913 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 896029423 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1544563096 # Number of instructions committed +system.cpu.commit.committedOps 1723073908 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773838 # Number of memory references committed -system.cpu.commit.loads 485926781 # Number of loads committed +system.cpu.commit.refs 660773836 # Number of memory references committed +system.cpu.commit.loads 485926780 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462438 # Number of branches committed +system.cpu.commit.branches 213462437 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941889 # Number of committed integer instructions. +system.cpu.commit.int_insts 1536941885 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106362657 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106147746 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2918613419 # The number of ROB reads -system.cpu.rob.rob_writes 4431868415 # The number of ROB writes -system.cpu.timesIdled 795856 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 38711414 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563083 # Number of Instructions Simulated -system.cpu.committedOps 1723073895 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1544563083 # Number of Instructions Simulated -system.cpu.cpi 0.613033 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.613033 # CPI: Total CPI of All Threads -system.cpu.ipc 1.631234 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.631234 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9926647662 # number of integer regfile reads -system.cpu.int_regfile_writes 1933066427 # number of integer regfile writes -system.cpu.fp_regfile_reads 168 # number of floating regfile reads -system.cpu.fp_regfile_writes 190 # number of floating regfile writes -system.cpu.misc_regfile_reads 2888912367 # number of misc regfile reads -system.cpu.misc_regfile_writes 148 # number of misc regfile writes -system.cpu.icache.replacements 20 # number of replacements -system.cpu.icache.tagsinuse 632.636403 # Cycle average of tags in use -system.cpu.icache.total_refs 282800594 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 786 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 359797.193384 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 3013417798 # The number of ROB reads +system.cpu.rob.rob_writes 4520246386 # The number of ROB writes +system.cpu.timesIdled 1016810 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 61069051 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1544563078 # Number of Instructions Simulated +system.cpu.committedOps 1723073890 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1544563078 # Number of Instructions Simulated +system.cpu.cpi 0.666930 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.666930 # CPI: Total CPI of All Threads +system.cpu.ipc 1.499407 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.499407 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10019536016 # number of integer regfile reads +system.cpu.int_regfile_writes 1949927429 # number of integer regfile writes +system.cpu.fp_regfile_reads 198 # number of floating regfile reads +system.cpu.fp_regfile_writes 204 # number of floating regfile writes +system.cpu.misc_regfile_reads 2950890294 # number of misc regfile reads +system.cpu.misc_regfile_writes 146 # number of misc regfile writes +system.cpu.icache.replacements 21 # number of replacements +system.cpu.icache.tagsinuse 635.874030 # Cycle average of tags in use +system.cpu.icache.total_refs 292881421 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 787 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 372149.200762 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 632.636403 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.308904 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.308904 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 282800594 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 282800594 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 282800594 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 282800594 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 282800594 # number of overall hits -system.cpu.icache.overall_hits::total 282800594 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1137 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1137 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1137 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1137 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1137 # number of overall misses -system.cpu.icache.overall_misses::total 1137 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39598000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39598000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39598000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39598000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39598000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39598000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 282801731 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 282801731 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 282801731 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 282801731 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 282801731 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 282801731 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 635.874030 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.310485 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.310485 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 292881421 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 292881421 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 292881421 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 292881421 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 292881421 # number of overall hits +system.cpu.icache.overall_hits::total 292881421 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1239 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1239 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1239 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1239 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1239 # number of overall misses +system.cpu.icache.overall_misses::total 1239 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62929999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62929999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62929999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62929999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62929999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62929999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 292882660 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 292882660 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 292882660 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 292882660 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 292882660 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 292882660 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34826.737027 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34826.737027 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34826.737027 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34826.737027 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34826.737027 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34826.737027 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50790.959645 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 50790.959645 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 50790.959645 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 50790.959645 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 50790.959645 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 50790.959645 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 213 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 351 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 351 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 351 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 351 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 351 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 786 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 786 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 786 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 786 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 786 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 786 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28796000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28796000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28796000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28796000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28796000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28796000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 452 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 452 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 452 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 452 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 452 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 452 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 787 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 787 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 787 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 787 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 787 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 787 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42672499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42672499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42672499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42672499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42672499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42672499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36636.132316 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36636.132316 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36636.132316 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36636.132316 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36636.132316 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36636.132316 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54221.726811 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54221.726811 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54221.726811 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54221.726811 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54221.726811 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54221.726811 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9616903 # number of replacements -system.cpu.dcache.tagsinuse 4087.861296 # Cycle average of tags in use -system.cpu.dcache.total_refs 660505517 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9620999 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.652488 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3324501000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.861296 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998013 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998013 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 492433938 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 492433938 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168071407 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168071407 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 99 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 99 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 73 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 73 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 660505345 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 660505345 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 660505345 # number of overall hits -system.cpu.dcache.overall_hits::total 660505345 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 10054191 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 10054191 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4514640 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4514640 # number of WriteReq misses +system.cpu.dcache.replacements 9616996 # number of replacements +system.cpu.dcache.tagsinuse 4088.070177 # Cycle average of tags in use +system.cpu.dcache.total_refs 662383558 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9621092 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.847025 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3431633000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4088.070177 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998064 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998064 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 495328808 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 495328808 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167054576 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167054576 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 102 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 102 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 72 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 72 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 662383384 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 662383384 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 662383384 # number of overall hits +system.cpu.dcache.overall_hits::total 662383384 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11493898 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11493898 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5531471 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5531471 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 14568831 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 14568831 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 14568831 # number of overall misses -system.cpu.dcache.overall_misses::total 14568831 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 192605585000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 192605585000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 133759941491 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 133759941491 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 146500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 146500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 326365526491 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 326365526491 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 326365526491 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 326365526491 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 502488129 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 502488129 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17025369 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17025369 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17025369 # number of overall misses +system.cpu.dcache.overall_misses::total 17025369 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 300469698500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 300469698500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 217116494201 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 217116494201 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 190500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 190500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 517586192701 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 517586192701 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 517586192701 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 517586192701 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 506822706 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 506822706 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 102 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 102 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 73 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 73 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 675074176 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 675074176 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 675074176 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 675074176 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020009 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020009 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026159 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.026159 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.029412 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.029412 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021581 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.021581 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021581 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.021581 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19156.746177 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19156.746177 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29628.041547 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29628.041547 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22401.627591 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22401.627591 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22401.627591 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22401.627591 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1880438 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 248831 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 88187 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1969 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.323302 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 126.374302 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 105 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 105 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 72 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 72 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 679408753 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 679408753 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 679408753 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 679408753 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022678 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022678 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032051 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032051 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.028571 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.028571 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025059 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025059 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025059 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025059 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26141.670867 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26141.670867 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39251.131245 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39251.131245 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30400.879576 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30400.879576 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30400.879576 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30400.879576 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 19937535 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 989836 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1174592 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 64547 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.974009 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15.335120 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3473899 # number of writebacks -system.cpu.dcache.writebacks::total 3473899 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2327206 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2327206 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2620625 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2620625 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3785750 # number of writebacks +system.cpu.dcache.writebacks::total 3785750 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3766794 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3766794 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3637483 # 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number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 159547869012 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015377 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015377 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7404277 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7404277 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7404277 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7404277 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7727104 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7727104 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893988 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893988 # 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average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13028.655032 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31085.100705 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31085.100705 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16583.293734 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16583.293734 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16583.293734 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16583.293734 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014161 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014161 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014161 # 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miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.438763 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963104 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.253835 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.253893 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963104 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.253835 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.253893 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36901.585205 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52729.678448 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52722.244970 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66435.459067 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66435.459067 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36901.585205 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57393.537034 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 57387.187042 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36901.585205 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57393.537034 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 57387.187042 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 1390172 # number of cycles access was blocked +system.cpu.l2cache.overall_misses::cpu.data 2256133 # number of overall misses +system.cpu.l2cache.overall_misses::total 2256890 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41571500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98780136000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 98821707500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58846759000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 58846759000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 41571500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 157626895000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 157668466500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 41571500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 157626895000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 157668466500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 787 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7727104 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7727891 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3785750 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3785750 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893988 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1893988 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 787 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9621092 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9621879 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 787 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9621092 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9621879 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.961881 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184789 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.184869 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437303 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.437303 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961881 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.234499 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.234558 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961881 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.234499 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.234558 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54916.116248 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69179.238973 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69171.681329 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71049.855961 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71049.855961 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54916.116248 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69865.958700 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69860.944264 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54916.116248 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69865.958700 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69860.944264 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 31316 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 44.391749 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1123933 # number of writebacks -system.cpu.l2cache.writebacks::total 1123933 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 756 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1611113 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1611869 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 831023 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 831023 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 756 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2442136 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2442892 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 756 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2442136 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2442892 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25190143 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 79130491462 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 79155681605 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 52276530586 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 52276530586 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25190143 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131407022048 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 131432212191 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25190143 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131407022048 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 131432212191 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961832 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208505 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208581 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438763 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438763 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961832 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253834 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.253892 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961832 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253834 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.253892 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33320.294974 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49115.419876 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 49108.011634 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62906.237957 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62906.237957 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33320.294974 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53808.232649 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53801.892262 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33320.294974 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53808.232649 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53801.892262 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 1103400 # number of writebacks +system.cpu.l2cache.writebacks::total 1103400 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 755 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1427881 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1428636 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 828246 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 828246 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 755 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2256127 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2256882 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 755 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2256127 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2256882 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31971694 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 80731453067 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80763424761 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48402066091 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48402066091 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31971694 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 129133519158 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 129165490852 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31971694 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 129133519158 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 129165490852 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959339 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184789 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184868 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437303 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437303 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959339 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.234498 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.234557 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959339 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.234498 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.234557 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42346.614570 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56539.342611 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56531.842093 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58439.239177 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58439.239177 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42346.614570 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57236.812980 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57231.831727 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42346.614570 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57236.812980 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57231.831727 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 49ea5f586..6ff1664e3 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.399400 # Number of seconds simulated -sim_ticks 2399400439000 # Number of ticks simulated -final_tick 2399400439000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.391205 # Number of seconds simulated +sim_ticks 2391205115000 # Number of ticks simulated +final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 994913 # Simulator instruction rate (inst/s) -host_op_rate 1110332 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1551375376 # Simulator tick rate (ticks/s) -host_mem_usage 233816 # Number of bytes of host memory used -host_seconds 1546.63 # Real time elapsed on the host +host_inst_rate 1213159 # Simulator instruction rate (inst/s) +host_op_rate 1353897 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1885227488 # Simulator tick rate (ticks/s) +host_mem_usage 231376 # Number of bytes of host memory used +host_seconds 1268.39 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1717270334 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 137819840 # Number of bytes read from this memory -system.physmem.bytes_read::total 137859264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125322112 # Number of bytes read from this memory +system.physmem.bytes_read::total 125361536 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67221184 # Number of bytes written to this memory -system.physmem.bytes_written::total 67221184 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65100672 # Number of bytes written to this memory +system.physmem.bytes_written::total 65100672 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2153435 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2154051 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050331 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050331 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 16431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 57439283 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 57455713 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 16431 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 16431 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 28015825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 28015825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 28015825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16431 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 57439283 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 85471539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 1958158 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1958774 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 16487 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 52409604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52426091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 16487 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 16487 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 27225047 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27225047 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27225047 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16487 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 52409604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 79651138 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 4798800878 # number of cpu cycles simulated +system.cpu.numCycles 4782410230 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1538759601 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 660773815 # nu system.cpu.num_load_insts 485926769 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4798800878 # Number of busy cycles +system.cpu.num_busy_cycles 4782410230 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 7 # number of replacements -system.cpu.icache.tagsinuse 514.980115 # Cycle average of tags in use +system.cpu.icache.tagsinuse 514.976015 # Cycle average of tags in use system.cpu.icache.total_refs 1544564952 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 2420948.200627 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 514.980115 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.251455 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.251455 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.251453 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses system.cpu.icache.overall_misses::total 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34189000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34189000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34189000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34189000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34189000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34189000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34233000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34233000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34233000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34233000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34233000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34233000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53587.774295 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53587.774295 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53587.774295 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53587.774295 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53587.774295 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53587.774295 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53656.739812 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53656.739812 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53656.739812 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53656.739812 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638 system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32913000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 32913000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32913000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 32913000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32913000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 32913000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32957000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 32957000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32957000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 32957000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32957000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 32957000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51587.774295 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51587.774295 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51587.774295 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51587.774295 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51587.774295 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51587.774295 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51656.739812 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51656.739812 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9111140 # number of replacements -system.cpu.dcache.tagsinuse 4083.564925 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4083.522356 # Cycle average of tags in use system.cpu.dcache.total_refs 645855059 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 25914432000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4083.564925 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996964 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996964 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996954 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115236 # n system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 151247261000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 151247261000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57698979000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57698979000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 208946240000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 208946240000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 208946240000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 208946240000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143391866000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143391866000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359006000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57359006000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200750872000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200750872000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200750872000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200750872000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20930.727931 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20930.727931 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30542.312438 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30542.312438 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22922.746048 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22922.746048 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22922.746048 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22922.746048 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.639580 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.639580 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.351514 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.351514 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22023.661483 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22023.661483 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3385547 # number of writebacks -system.cpu.dcache.writebacks::total 3385547 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks +system.cpu.dcache.writebacks::total 3697418 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 136795087000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 136795087000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53920681000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53920681000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 190715768000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 190715768000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 190715768000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 190715768000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128939692000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 128939692000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580708000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580708000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182520400000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 182520400000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182520400000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 182520400000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses @@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # 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number of replacements -system.cpu.l2cache.tagsinuse 30623.782374 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8443619 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2168151 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.894387 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 435858689000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14787.769987 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 15.768959 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15820.243429 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.451287 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000481 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.482796 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.934564 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 1926075 # number of replacements +system.cpu.l2cache.tagsinuse 30987.094489 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8967572 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1955843 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.585016 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 15648.493745 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.477554 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.945651 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 5861680 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5861702 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3385547 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3385547 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1100121 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1100121 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6048805 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6048827 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3697418 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3697418 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108273 # 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number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2153435 # number of overall misses -system.cpu.l2cache.overall_misses::total 2154051 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32055000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70952200000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 70984255000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41030322000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41030322000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 32055000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 111982522000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 112014577000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 32055000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 111982522000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 112014577000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 1958158 # number of overall misses +system.cpu.l2cache.overall_misses::total 1958774 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32099000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61225555000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 61257654000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608829000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 40608829000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 32099000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 101834384000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 101866483000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 32099000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 101834384000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 101866483000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3385547 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3385547 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3697418 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3697418 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses @@ -347,27 +347,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 638 system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188817 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.188885 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417663 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.417663 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.162992 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413348 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.413348 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.236246 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.236297 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214823 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214875 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.236246 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.236297 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52037.337662 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52002.225142 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52002.240988 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.097553 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.097553 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52037.337662 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.811989 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52001.822148 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52037.337662 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.811989 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52001.822148 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214823 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214875 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52108.766234 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52005.853313 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.907133 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.196569 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.196569 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52005.225207 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52005.225207 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -376,52 +376,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1050331 # number of writebacks -system.cpu.l2cache.writebacks::total 1050331 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1017198 # number of writebacks +system.cpu.l2cache.writebacks::total 1017198 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1364407 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1365023 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 789028 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 789028 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177282 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1177898 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780876 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 780876 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2153435 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2154051 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1958158 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1958774 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2153435 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2154051 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24663000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54579316000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54603979000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31561986000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31561986000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24663000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86141302000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 86165965000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24663000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86141302000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 86165965000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1958158 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1958774 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24707000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098171000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122878000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24707000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336488000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 78361195000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24707000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336488000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 78361195000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188817 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188885 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417663 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417663 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413348 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413348 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.236246 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.236297 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.236246 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.236297 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40037.337662 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40002.225142 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40002.240988 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.097553 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.097553 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40037.337662 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40001.811989 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.822148 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40037.337662 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40001.811989 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.822148 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40108.766234 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.853313 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.907133 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 04d920eee..21fe18ab3 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.891582 # Number of seconds simulated -sim_ticks 5891581948000 # Number of ticks simulated -final_tick 5891581948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.882581 # Number of seconds simulated +sim_ticks 5882580524000 # Number of ticks simulated +final_tick 5882580524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 701685 # Simulator instruction rate (inst/s) -host_op_rate 1093289 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1374310212 # Simulator tick rate (ticks/s) -host_mem_usage 228764 # Number of bytes of host memory used -host_seconds 4286.94 # Real time elapsed on the host +host_inst_rate 472403 # Simulator instruction rate (inst/s) +host_op_rate 736047 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 923827707 # Simulator tick rate (ticks/s) +host_mem_usage 227772 # Number of bytes of host memory used +host_seconds 6367.62 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862594 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 139043584 # Number of bytes read from this memory -system.physmem.bytes_read::total 139086784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125326976 # Number of bytes read from this memory +system.physmem.bytes_read::total 125370176 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67393856 # Number of bytes written to this memory -system.physmem.bytes_written::total 67393856 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65178944 # Number of bytes written to this memory +system.physmem.bytes_written::total 65178944 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2172556 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2173231 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1053029 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1053029 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7332 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 23600382 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 23607714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7332 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7332 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11439009 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11439009 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11439009 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 23600382 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 35046723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 1958234 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1958909 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018421 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018421 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 21304762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 21312105 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 11079992 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11079992 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11079992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 11783163896 # number of cpu cycles simulated +system.cpu.numCycles 11765161048 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 3008081022 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 1677713082 # nu system.cpu.num_load_insts 1239184745 # Number of load instructions system.cpu.num_store_insts 438528337 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 11783163896 # Number of busy cycles +system.cpu.num_busy_cycles 11765161048 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 10 # number of replacements -system.cpu.icache.tagsinuse 555.725129 # Cycle average of tags in use +system.cpu.icache.tagsinuse 555.705054 # Cycle average of tags in use system.cpu.icache.total_refs 4013232208 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5945529.197037 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 555.725129 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.271350 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.271350 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.271340 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 675 # n system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses system.cpu.icache.overall_misses::total 675 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 37130000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 37130000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 37130000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 37130000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 37130000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 37130000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 37156000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 37156000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 37156000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 37156000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 37156000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 37156000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4013232883 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4013232883 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4013232883 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55007.407407 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55007.407407 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55007.407407 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55007.407407 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55007.407407 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55007.407407 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55045.925926 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55045.925926 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55045.925926 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55045.925926 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 675 system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35780000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 35780000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35780000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 35780000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35780000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 35780000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35806000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 35806000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35806000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 35806000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35806000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 35806000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53007.407407 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53007.407407 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53007.407407 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53007.407407 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53007.407407 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53007.407407 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53045.925926 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53045.925926 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9108581 # number of replacements -system.cpu.dcache.tagsinuse 4084.604436 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4084.587031 # Cycle average of tags in use system.cpu.dcache.total_refs 1668600405 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 58853994000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4084.604436 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997218 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997218 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 58853920000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4084.587031 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997214 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 436638510 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 9112677 # n system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses system.cpu.dcache.overall_misses::total 9112677 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 151971083000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 151971083000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57741123000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57741123000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 209712206000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 209712206000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 209712206000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 209712206000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143328541000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143328541000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57382215000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57382215000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200710756000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200710756000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200710756000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200710756000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1239184745 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1239184745 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 438528337 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21040.321064 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21040.321064 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30553.655440 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30553.655440 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23013.238152 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23013.238152 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23013.238152 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23013.238152 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.765411 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.765411 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30363.739644 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30363.739644 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22025.443895 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22025.443895 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3375759 # number of writebacks -system.cpu.dcache.writebacks::total 3375759 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3697956 # number of writebacks +system.cpu.dcache.writebacks::total 3697956 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137525383000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 137525383000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53961469000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53961469000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191486852000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 191486852000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191486852000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 191486852000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128882841000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 128882841000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53602561000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53602561000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182485402000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 182485402000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182485402000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 182485402000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses @@ -226,65 +226,65 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.321064 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.321064 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.655440 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.655440 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.238152 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.238152 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.238152 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.238152 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.765411 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.765411 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28363.739644 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28363.739644 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2158210 # number of replacements -system.cpu.l2cache.tagsinuse 30849.854795 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8410861 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2187939 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.844194 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 1315499445000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14663.466685 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 21.611649 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16164.776461 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.447493 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000660 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.493310 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.941463 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5840135 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5840135 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3375759 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3375759 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1099986 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1099986 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 6940121 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6940121 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 6940121 # number of overall hits -system.cpu.l2cache.overall_hits::total 6940121 # number of overall hits +system.cpu.l2cache.replacements 1926197 # number of replacements +system.cpu.l2cache.tagsinuse 31136.249390 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8965026 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1955980 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.583393 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 340768633000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 15396.795539 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15713.812836 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.950203 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 6045911 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6045911 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3697956 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3697956 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108532 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1108532 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7154443 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7154443 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7154443 # number of overall hits +system.cpu.l2cache.overall_hits::total 7154443 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1382715 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1383390 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 789841 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 789841 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1176939 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1177614 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 781295 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 781295 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2172556 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2173231 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1958234 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1958909 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2172556 # number of overall misses -system.cpu.l2cache.overall_misses::total 2173231 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35105000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71901183000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 71936288000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41071782000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41071782000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 35105000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 112972965000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 113008070000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 35105000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 112972965000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 113008070000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 1958234 # number of overall misses +system.cpu.l2cache.overall_misses::total 1958909 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35131000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61200881000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 61236012000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40627414000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 40627414000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 35131000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 101828295000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 101863426000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 35131000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 101828295000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 101863426000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 675 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7222850 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7223525 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3375759 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3375759 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3697956 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3697956 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses @@ -294,27 +294,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 675 system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.191436 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.191512 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417944 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.417944 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162947 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163025 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413421 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.413421 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.238410 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.238467 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214891 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214949 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.238410 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.238467 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52007.407407 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.002170 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.005783 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.063304 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.063304 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52007.407407 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.024395 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.026688 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52007.407407 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.024395 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.026688 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214891 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214949 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52045.925926 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.045032 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.071331 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.094715 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.094715 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52045.925926 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.064854 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.080657 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52045.925926 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.064854 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.080657 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -323,52 +323,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1053029 # number of writebacks -system.cpu.l2cache.writebacks::total 1053029 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1018421 # number of writebacks +system.cpu.l2cache.writebacks::total 1018421 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1382715 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1383390 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 789841 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 789841 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1176939 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1177614 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781295 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 781295 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2172556 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2173231 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1958234 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1958909 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2172556 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2173231 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27005000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55308603000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55335608000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31593690000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31593690000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27005000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86902293000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 86929298000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27005000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86902293000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 86929298000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1958234 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1958909 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27031000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47077613000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47104644000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31251874000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31251874000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27031000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78329487000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 78356518000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27031000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78329487000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 78356518000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.191436 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191512 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417944 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417944 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162947 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163025 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413421 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413421 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.238410 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.238467 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214949 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.238410 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.238467 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40007.407407 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.002170 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.005783 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.063304 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.063304 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40007.407407 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.024395 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.026688 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40007.407407 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.024395 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.026688 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214949 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.925926 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.045032 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.071331 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.094715 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.094715 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index a6fa2a523..ba13ea976 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041975 # Number of seconds simulated -sim_ticks 41974805000 # Number of ticks simulated -final_tick 41974805000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.041949 # Number of seconds simulated +sim_ticks 41948719000 # Number of ticks simulated +final_tick 41948719000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 82989 # Simulator instruction rate (inst/s) -host_op_rate 82989 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37903288 # Simulator tick rate (ticks/s) -host_mem_usage 220440 # Number of bytes of host memory used -host_seconds 1107.42 # Real time elapsed on the host +host_inst_rate 82495 # Simulator instruction rate (inst/s) +host_op_rate 82495 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37654494 # Simulator tick rate (ticks/s) +host_mem_usage 221732 # Number of bytes of host memory used +host_seconds 1114.04 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4260079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3269009 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7529088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4260079 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4260079 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4260079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3269009 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7529088 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4262728 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3271041 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7533770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4262728 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4262728 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4262728 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3271041 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7533770 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 4938 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 41974753000 # Total gap between requests +system.physmem.totGap 41948681000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,13 +98,13 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 3879 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 789 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3467 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 991 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -164,14 +164,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 15273921 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 109715921 # Sum of mem lat for all requests +system.physmem.totQLat 18563928 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 107349928 # Sum of mem lat for all requests system.physmem.totBusLat 19752000 # Total cycles spent in databus access -system.physmem.totBankLat 74690000 # Total cycles spent in bank access -system.physmem.avgQLat 3093.14 # Average queueing delay per request -system.physmem.avgBankLat 15125.56 # Average bank access latency per request +system.physmem.totBankLat 69034000 # Total cycles spent in bank access +system.physmem.avgQLat 3759.40 # Average queueing delay per request +system.physmem.avgBankLat 13980.15 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22218.70 # Average memory access latency +system.physmem.avgMemAccLat 21739.56 # Average memory access latency system.physmem.avgRdBW 7.53 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 7.53 # Average consumed read bandwidth in MB/s @@ -184,27 +184,27 @@ system.physmem.readRowHits 4458 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.28 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8500355.00 # Average gap between requests +system.physmem.avgGap 8495075.13 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996215 # DTB read hits +system.cpu.dtb.read_hits 19996251 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996225 # DTB read accesses -system.cpu.dtb.write_hits 6501907 # DTB write hits +system.cpu.dtb.read_accesses 19996261 # DTB read accesses +system.cpu.dtb.write_hits 6501863 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501930 # DTB write accesses -system.cpu.dtb.data_hits 26498122 # DTB hits +system.cpu.dtb.write_accesses 6501886 # DTB write accesses +system.cpu.dtb.data_hits 26498114 # DTB hits system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26498155 # DTB accesses -system.cpu.itb.fetch_hits 10035744 # ITB hits +system.cpu.dtb.data_accesses 26498147 # DTB accesses +system.cpu.itb.fetch_hits 10035746 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 10035793 # ITB accesses +system.cpu.itb.fetch_accesses 10035795 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,26 +218,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83949611 # number of cpu cycles simulated +system.cpu.numCycles 83897439 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 13564912 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 9782242 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 13564910 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 9782241 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 4497823 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 7992579 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 3850502 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 7992573 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 3850501 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 122 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 48.175964 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 5999728 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.BTBHitPct 48.175988 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 5999726 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 7565184 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73745301 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 73745307 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136320773 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 2206799 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 136320779 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 2206802 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 8058687 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38528717 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.floatRegFileAccesses 8058690 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 38528710 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 26769089 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 3520477 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 976488 # Number of Branches Incorrectly Predicted As Not Taken). @@ -248,12 +248,12 @@ system.cpu.execution_unit.executions 57470360 # Nu system.cpu.mult_div_unit.multiplies 458258 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 83639616 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 83635742 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 11375 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7667023 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 76282588 # Number of cycles cpu stages are processed. -system.cpu.activity 90.867113 # Percentage of cycles cpu is active +system.cpu.timesIdled 10897 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7614848 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 76282591 # Number of cycles cpu stages are processed. +system.cpu.activity 90.923623 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -265,144 +265,144 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.913458 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.912891 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.913458 # CPI: Total CPI of All Threads -system.cpu.ipc 1.094741 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.912891 # CPI: Total CPI of All Threads +system.cpu.ipc 1.095421 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.094741 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27728071 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 56221540 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.970578 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34502106 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49447505 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 58.901411 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33971546 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49978065 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.533409 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65920043 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18029568 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.476655 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 30005535 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53944076 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.257684 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.095421 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27675918 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 56221521 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 67.012202 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34449958 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49447481 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 58.938010 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33919397 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49978042 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.570402 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65867839 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18029600 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.490048 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29953374 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53944065 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.297630 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 8127 # number of replacements -system.cpu.icache.tagsinuse 1492.468291 # Cycle average of tags in use -system.cpu.icache.total_refs 10023999 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1492.667941 # Cycle average of tags in use +system.cpu.icache.total_refs 10023995 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 10012 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1001.198462 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1001.198062 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1492.468291 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.728744 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.728744 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10023999 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10023999 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10023999 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10023999 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10023999 # number of overall hits -system.cpu.icache.overall_hits::total 10023999 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11743 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11743 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11743 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11743 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11743 # number of overall misses -system.cpu.icache.overall_misses::total 11743 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 259067500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 259067500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 259067500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 259067500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 259067500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 259067500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 10035742 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 10035742 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 10035742 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 10035742 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 10035742 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 10035742 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001170 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001170 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001170 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001170 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001170 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001170 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22061.440858 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22061.440858 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22061.440858 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22061.440858 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22061.440858 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22061.440858 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 67 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 16.750000 # average number of cycles each access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1492.667941 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.728842 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.728842 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10023995 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10023995 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10023995 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10023995 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10023995 # number of overall hits +system.cpu.icache.overall_hits::total 10023995 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11751 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11751 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11751 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11751 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11751 # number of overall misses +system.cpu.icache.overall_misses::total 11751 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 259062500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 259062500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 259062500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 259062500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 259062500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 259062500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 10035746 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 10035746 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 10035746 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 10035746 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 10035746 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 10035746 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001171 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001171 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001171 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001171 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001171 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001171 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22045.996085 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22045.996085 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22045.996085 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22045.996085 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22045.996085 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22045.996085 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1731 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1731 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1731 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1731 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1731 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1731 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1739 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1739 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1739 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1739 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1739 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1739 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10012 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 10012 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 10012 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 10012 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10012 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10012 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 210374500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 210374500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 210374500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 210374500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 210374500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 210374500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 209799500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 209799500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 209799500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 209799500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 209799500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 209799500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000998 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000998 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21012.235318 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21012.235318 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21012.235318 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21012.235318 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21012.235318 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21012.235318 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20954.804235 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20954.804235 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20954.804235 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20954.804235 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20954.804235 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20954.804235 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.629591 # Cycle average of tags in use -system.cpu.dcache.total_refs 26491183 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1441.862848 # Cycle average of tags in use +system.cpu.dcache.total_refs 26488630 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11916.861448 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11915.713000 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.629591 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.351960 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.351960 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 19995637 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995637 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6495546 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6495546 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26491183 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26491183 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26491183 # number of overall hits -system.cpu.dcache.overall_hits::total 26491183 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 561 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 561 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5557 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5557 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 6118 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6118 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6118 # number of overall misses -system.cpu.dcache.overall_misses::total 6118 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28389500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 28389500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 249397000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 249397000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 277786500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 277786500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 277786500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 277786500 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 1441.862848 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.352017 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.352017 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995623 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995623 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493007 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493007 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26488630 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26488630 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26488630 # number of overall hits +system.cpu.dcache.overall_hits::total 26488630 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 575 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 575 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8096 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8096 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 8671 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8671 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8671 # number of overall misses +system.cpu.dcache.overall_misses::total 8671 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28479000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28479000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 330607000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 330607000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 359086000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 359086000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 359086000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 359086000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -411,40 +411,40 @@ system.cpu.dcache.demand_accesses::cpu.data 26497301 # system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000855 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000855 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000231 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000231 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000231 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000231 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50605.169340 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50605.169340 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44879.791254 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44879.791254 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45404.789147 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45404.789147 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45404.789147 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45404.789147 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 63919 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 827 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 77.290206 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001245 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001245 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49528.695652 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49528.695652 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40835.844862 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40835.844862 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41412.293853 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41412.293853 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41412.293853 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41412.293853 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 11966 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 828 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.451691 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 86 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3809 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3809 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3895 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3895 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3895 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3895 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 100 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6348 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6348 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6448 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6448 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6448 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6448 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -453,14 +453,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23282500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23282500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80468500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 80468500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 103751000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 103751000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 103751000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 103751000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22783000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22783000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 82274500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 82274500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 105057500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 105057500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 105057500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 105057500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -469,28 +469,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49015.789474 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49015.789474 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46034.610984 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46034.610984 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46671.614935 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 46671.614935 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46671.614935 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 46671.614935 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47964.210526 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47964.210526 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47067.791762 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47067.791762 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47259.334233 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 47259.334233 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47259.334233 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 47259.334233 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2189.948520 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2190.279989 # Cycle average of tags in use system.cpu.l2cache.total_refs 7285 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.219683 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.843388 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1821.063413 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.041719 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.844336 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1821.341583 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.094069 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055574 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010713 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.066832 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.055583 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010715 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.066842 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 7218 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 7271 # number of ReadReq hits @@ -515,17 +515,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 127870000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22259000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 150129000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78446500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 78446500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 127870000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 100705500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 228575500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 127870000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 100705500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 228575500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 127295000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21759500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 149054500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 80257000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 80257000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 127295000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 102016500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 229311500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 127295000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 102016500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 229311500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 10012 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 10487 # number of ReadReq accesses(hits+misses) @@ -550,17 +550,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.403596 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279065 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.403596 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 45765.926986 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52746.445498 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 46681.902985 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45555.458769 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45555.458769 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 45765.926986 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46970.848881 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 46289.084650 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 45765.926986 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46970.848881 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 46289.084650 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 45560.128848 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51562.796209 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 46347.792289 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46606.852497 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46606.852497 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 45560.128848 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47582.322761 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 46438.132847 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 45560.128848 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47582.322761 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 46438.132847 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -580,17 +580,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 92500808 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16940683 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 109441491 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 57047489 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 57047489 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 92500808 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 73988172 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 166488980 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 92500808 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 73988172 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 166488980 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 91926812 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16443678 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 108370490 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 59040867 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 59040867 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91926812 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75484545 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 167411357 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91926812 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75484545 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 167411357 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.306665 # mshr miss rate for ReadReq accesses @@ -602,17 +602,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.403596 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.403596 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33106.946314 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40143.798578 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34030.314366 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33128.623113 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33128.623113 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33106.946314 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34509.408582 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33715.872823 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33106.946314 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34509.408582 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33715.872823 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32901.507516 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38966.061611 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33697.291667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34286.217770 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34286.217770 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32901.507516 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35207.343750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33902.664439 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32901.507516 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35207.343750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33902.664439 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index ca5f0ff42..ef2eb2fe7 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023631 # Number of seconds simulated -sim_ticks 23630830000 # Number of ticks simulated -final_tick 23630830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023714 # Number of seconds simulated +sim_ticks 23713623000 # Number of ticks simulated +final_tick 23713623000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120910 # Simulator instruction rate (inst/s) -host_op_rate 120910 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33941778 # Simulator tick rate (ticks/s) -host_mem_usage 221472 # Number of bytes of host memory used -host_seconds 696.22 # Real time elapsed on the host +host_inst_rate 202255 # Simulator instruction rate (inst/s) +host_op_rate 202255 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56975613 # Simulator tick rate (ticks/s) +host_mem_usage 222752 # Number of bytes of host memory used +host_seconds 416.21 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 197248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138368 # Number of bytes read from this memory -system.physmem.bytes_read::total 335616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 197248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 197248 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3082 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2162 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5244 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8347062 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5855402 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14202463 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8347062 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8347062 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8347062 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5855402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14202463 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5244 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 196928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory +system.physmem.bytes_read::total 335488 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 196928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 196928 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3077 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5242 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8304425 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5843055 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14147480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8304425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8304425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8304425 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5843055 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14147480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5242 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5244 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 335616 # Total number of bytes read from memory +system.physmem.cpureqs 5242 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 335488 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 335616 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 335488 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 369 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 342 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 252 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 255 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 370 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 340 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 254 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 319 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 254 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 295 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 377 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 403 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 324 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 376 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 404 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 323 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 298 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 279 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 287 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 325 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 386 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 288 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 326 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 385 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 380 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 354 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 353 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23630742000 # Total gap between requests +system.physmem.totGap 23713517000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5244 # Categorize read packet sizes +system.physmem.readPktSize::6 5242 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,16 +98,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 3183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 583 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1550 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 23669737 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 116101737 # Sum of mem lat for all requests -system.physmem.totBusLat 20976000 # Total cycles spent in databus access -system.physmem.totBankLat 71456000 # Total cycles spent in bank access -system.physmem.avgQLat 4513.68 # Average queueing delay per request -system.physmem.avgBankLat 13626.24 # Average bank access latency per request +system.physmem.totQLat 21552231 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 116524231 # Sum of mem lat for all requests +system.physmem.totBusLat 20968000 # Total cycles spent in databus access +system.physmem.totBankLat 74004000 # Total cycles spent in bank access +system.physmem.avgQLat 4111.45 # Average queueing delay per request +system.physmem.avgBankLat 14117.51 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22139.92 # Average memory access latency -system.physmem.avgRdBW 14.20 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22228.96 # Average memory access latency +system.physmem.avgRdBW 14.15 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.20 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.15 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.09 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4702 # Number of row buffer hits during reads +system.physmem.readRowHits 4692 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.66 # Row buffer hit rate for reads +system.physmem.readRowHitRate 89.51 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4506243.71 # Average gap between requests +system.physmem.avgGap 4523753.72 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23223355 # DTB read hits -system.cpu.dtb.read_misses 199967 # DTB read misses -system.cpu.dtb.read_acv 4 # DTB read access violations -system.cpu.dtb.read_accesses 23423322 # DTB read accesses -system.cpu.dtb.write_hits 7080030 # DTB write hits -system.cpu.dtb.write_misses 1356 # DTB write misses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 7081386 # DTB write accesses -system.cpu.dtb.data_hits 30303385 # DTB hits -system.cpu.dtb.data_misses 201323 # DTB misses -system.cpu.dtb.data_acv 6 # DTB access violations -system.cpu.dtb.data_accesses 30504708 # DTB accesses -system.cpu.itb.fetch_hits 14954333 # ITB hits -system.cpu.itb.fetch_misses 120 # ITB misses +system.cpu.dtb.read_hits 23220961 # DTB read hits +system.cpu.dtb.read_misses 199829 # DTB read misses +system.cpu.dtb.read_acv 2 # DTB read access violations +system.cpu.dtb.read_accesses 23420790 # DTB read accesses +system.cpu.dtb.write_hits 7077526 # DTB write hits +system.cpu.dtb.write_misses 1364 # DTB write misses +system.cpu.dtb.write_acv 6 # DTB write access violations +system.cpu.dtb.write_accesses 7078890 # DTB write accesses +system.cpu.dtb.data_hits 30298487 # DTB hits +system.cpu.dtb.data_misses 201193 # DTB misses +system.cpu.dtb.data_acv 8 # DTB access violations +system.cpu.dtb.data_accesses 30499680 # DTB accesses +system.cpu.itb.fetch_hits 14949647 # ITB hits +system.cpu.itb.fetch_misses 105 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14954453 # ITB accesses +system.cpu.itb.fetch_accesses 14949752 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,112 +218,113 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 47261661 # number of cpu cycles simulated +system.cpu.numCycles 47427247 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15031497 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10899201 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 964727 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 8732701 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7076597 # Number of BTB hits +system.cpu.BPredUnit.lookups 15025642 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10894363 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 964786 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 8694430 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7072700 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1487345 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 3368 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15614500 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 128263242 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15031497 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8563942 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22389896 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4636452 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5551739 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2133 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14954333 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 338853 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47196510 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.717643 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.372831 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1485982 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 3318 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15702309 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 128217574 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15025642 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8558682 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22383156 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4634796 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5563262 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 84 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2124 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 19 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 14949647 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 339712 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47286808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.711487 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.371391 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24806614 52.56% 52.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2389980 5.06% 57.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1210958 2.57% 60.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1776777 3.76% 63.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2802179 5.94% 69.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1172690 2.48% 72.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1230204 2.61% 74.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 789239 1.67% 76.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11017869 23.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24903652 52.67% 52.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2390695 5.06% 57.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1208579 2.56% 60.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1776118 3.76% 64.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2803213 5.93% 69.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1173314 2.48% 72.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1230561 2.60% 75.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 786829 1.66% 76.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11013847 23.29% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47196510 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.318048 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.713896 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17460604 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4250656 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20766421 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1092488 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3626341 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2544445 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12397 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 125174951 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32088 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3626341 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18627234 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 962190 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8129 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20670858 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3301758 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 122185352 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 402329 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2427096 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 89707747 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 158670699 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 148931458 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9739241 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 47286808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.316815 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.703458 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17546675 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4261865 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20763738 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1090514 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3624016 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2545492 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12249 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 125138336 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32050 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3624016 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18714540 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 973231 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8290 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20663986 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3302745 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 122153228 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 68 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 400521 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2428440 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89689212 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 158636809 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 148888433 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9748376 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 21280386 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1002 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1014 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8742077 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25560713 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8304198 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2649829 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 949216 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 106168633 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2274 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96984807 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 186233 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21527282 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16158700 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1885 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47196510 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.054915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.875207 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 21261851 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 999 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1008 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8748966 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25553670 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8298282 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2624329 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 917691 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 106148372 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2425 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96973982 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 186832 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21507239 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16151719 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2036 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47286808 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.050762 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.875057 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12446961 26.37% 26.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9431395 19.98% 46.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8468096 17.94% 64.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6320682 13.39% 77.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4944837 10.48% 88.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2848295 6.03% 94.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1728522 3.66% 97.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 798557 1.69% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 209165 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12523872 26.48% 26.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9450826 19.99% 46.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8468072 17.91% 64.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6321623 13.37% 77.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4941695 10.45% 88.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2845109 6.02% 94.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1728871 3.66% 97.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 797328 1.69% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 209412 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47196510 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47286808 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 189157 12.05% 12.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 237 0.02% 12.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7151 0.46% 12.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5547 0.35% 12.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 843237 53.72% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 189731 12.08% 12.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 196 0.01% 12.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7230 0.46% 12.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5874 0.37% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 843349 53.68% 66.60% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.60% # attempts to use FU when none available @@ -345,19 +346,19 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.60% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 445222 28.36% 94.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 79100 5.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 445490 28.35% 94.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 79325 5.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58989351 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 480619 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58981330 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 480636 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2802202 2.89% 64.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115471 0.12% 64.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2386536 2.46% 66.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311369 0.32% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 759928 0.78% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2802326 2.89% 64.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115452 0.12% 64.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2386635 2.46% 66.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311394 0.32% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 759833 0.78% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.89% # Type of FU issued @@ -379,84 +380,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.89% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23967188 24.71% 92.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7171817 7.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23966232 24.71% 92.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7169818 7.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96984807 # Type of FU issued -system.cpu.iq.rate 2.052082 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1569651 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016185 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 227791870 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 118912637 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87370988 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15130138 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8820177 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7068200 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90559677 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7994774 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1518774 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96973982 # Type of FU issued +system.cpu.iq.rate 2.044689 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1571195 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016202 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 227861218 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 118862045 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87356059 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15131581 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8830751 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7068549 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90549768 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7995402 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1518620 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5564515 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 19809 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34734 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1803095 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5557472 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 19450 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34891 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1797179 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10505 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10488 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1489 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3626341 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 131070 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17619 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 116470742 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 396615 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25560713 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8304198 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2274 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3005 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 33 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34734 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 570082 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 507540 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1077622 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95693120 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23424012 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1291687 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3624016 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 135468 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17609 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 116444859 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 396288 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25553670 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8298282 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2425 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3185 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 28 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34891 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 568741 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 508698 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1077439 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95679677 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23421457 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1294305 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10299835 # number of nop insts executed -system.cpu.iew.exec_refs 30505591 # number of memory reference insts executed -system.cpu.iew.exec_branches 12076727 # Number of branches executed -system.cpu.iew.exec_stores 7081579 # Number of stores executed -system.cpu.iew.exec_rate 2.024752 # Inst execution rate -system.cpu.iew.wb_sent 94981894 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94439188 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64622529 # num instructions producing a value -system.cpu.iew.wb_consumers 90009959 # num instructions consuming a value +system.cpu.iew.exec_nop 10294062 # number of nop insts executed +system.cpu.iew.exec_refs 30500537 # number of memory reference insts executed +system.cpu.iew.exec_branches 12076025 # Number of branches executed +system.cpu.iew.exec_stores 7079080 # Number of stores executed +system.cpu.iew.exec_rate 2.017399 # Inst execution rate +system.cpu.iew.wb_sent 94965900 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94424608 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64613443 # num instructions producing a value +system.cpu.iew.wb_consumers 89987902 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.998220 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717949 # average fanout of values written-back +system.cpu.iew.wb_rate 1.990936 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.718024 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24568706 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 24543105 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 952874 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43570169 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.109311 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.735421 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 952948 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43662792 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.104837 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.733240 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17034200 39.10% 39.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9970297 22.88% 61.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4508116 10.35% 72.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2285317 5.25% 77.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1618875 3.72% 81.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1127711 2.59% 83.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 720325 1.65% 85.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 818054 1.88% 87.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5487274 12.59% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17112386 39.19% 39.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9977533 22.85% 62.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4511330 10.33% 72.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2294197 5.25% 77.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1617378 3.70% 81.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1129034 2.59% 83.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 721116 1.65% 85.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 819651 1.88% 87.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5480167 12.55% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43570169 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43662792 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -467,372 +468,372 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5487274 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5480167 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 154553616 # The number of ROB reads -system.cpu.rob.rob_writes 236594431 # The number of ROB writes -system.cpu.timesIdled 1889 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 65151 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 154627745 # The number of ROB reads +system.cpu.rob.rob_writes 236540658 # The number of ROB writes +system.cpu.timesIdled 5097 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 140439 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.561438 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.561438 # CPI: Total CPI of All Threads -system.cpu.ipc 1.781142 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.781142 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129470706 # number of integer regfile reads -system.cpu.int_regfile_writes 70779763 # number of integer regfile writes -system.cpu.fp_regfile_reads 6192026 # number of floating regfile reads -system.cpu.fp_regfile_writes 6049557 # number of floating regfile writes -system.cpu.misc_regfile_reads 714457 # number of misc regfile reads +system.cpu.cpi 0.563405 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.563405 # CPI: Total CPI of All Threads +system.cpu.ipc 1.774923 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.774923 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129451321 # number of integer regfile reads +system.cpu.int_regfile_writes 70766811 # number of integer regfile writes +system.cpu.fp_regfile_reads 6191777 # number of floating regfile reads +system.cpu.fp_regfile_writes 6050030 # number of floating regfile writes +system.cpu.misc_regfile_reads 714415 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 10301 # number of replacements -system.cpu.icache.tagsinuse 1602.585562 # Cycle average of tags in use -system.cpu.icache.total_refs 14940827 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 12238 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1220.855287 # Average number of references to valid blocks. +system.cpu.icache.replacements 10208 # number of replacements +system.cpu.icache.tagsinuse 1605.593166 # Cycle average of tags in use +system.cpu.icache.total_refs 14934718 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 12146 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1229.599704 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1602.585562 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.782512 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.782512 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14940827 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14940827 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14940827 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14940827 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14940827 # number of overall hits -system.cpu.icache.overall_hits::total 14940827 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13506 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13506 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13506 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13506 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13506 # number of overall misses -system.cpu.icache.overall_misses::total 13506 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 154262500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 154262500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 154262500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 154262500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 154262500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 154262500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14954333 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14954333 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14954333 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14954333 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14954333 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14954333 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000903 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000903 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000903 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000903 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000903 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000903 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11421.775507 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 11421.775507 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 11421.775507 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 11421.775507 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 11421.775507 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 11421.775507 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1605.593166 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.783981 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.783981 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14934718 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14934718 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14934718 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14934718 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14934718 # number of overall hits +system.cpu.icache.overall_hits::total 14934718 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14928 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14928 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14928 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14928 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14928 # number of overall misses +system.cpu.icache.overall_misses::total 14928 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 320401000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 320401000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 320401000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 320401000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 320401000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 320401000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14949646 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14949646 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14949646 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14949646 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14949646 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14949646 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000999 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000999 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000999 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000999 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000999 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000999 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21463.089496 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21463.089496 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21463.089496 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21463.089496 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21463.089496 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21463.089496 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 207 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 41.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1268 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1268 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1268 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1268 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1268 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1268 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12238 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12238 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12238 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12238 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12238 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12238 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 106604500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 106604500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 106604500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 106604500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106604500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 106604500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000818 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000818 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000818 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000818 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000818 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000818 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8710.941330 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8710.941330 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8710.941330 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8710.941330 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8710.941330 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8710.941330 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2782 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2782 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2782 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 242268500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 242268500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 242268500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000812 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000812 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000812 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000812 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000812 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000812 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19946.360942 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19946.360942 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19946.360942 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19946.360942 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19946.360942 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19946.360942 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1457.159640 # Cycle average of tags in use -system.cpu.dcache.total_refs 28186155 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2241 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12577.489960 # Average number of references to valid blocks. +system.cpu.dcache.replacements 158 # number of replacements +system.cpu.dcache.tagsinuse 1458.435251 # Cycle average of tags in use +system.cpu.dcache.total_refs 28182735 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2245 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12553.556793 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1457.159640 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.355752 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.355752 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 21692653 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21692653 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6493028 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6493028 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 474 # 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number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21689327 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492999 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492999 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 409 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 409 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28182326 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28182326 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28182326 # number of overall hits +system.cpu.dcache.overall_hits::total 28182326 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1019 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1019 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8104 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8104 # 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number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 261079000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 261079000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 261079000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 261079000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21693589 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21693589 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9123 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9123 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9123 # number of overall misses +system.cpu.dcache.overall_misses::total 9123 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 44496500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 44496500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 347386146 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 347386146 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 72000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 72000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 391882646 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 391882646 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 391882646 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 391882646 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21690346 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21690346 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 475 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 475 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28194692 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28194692 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28194692 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28194692 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000043 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001242 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001242 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002105 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002105 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000320 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000320 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000320 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000320 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31123.397436 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31123.397436 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28724.148607 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28724.148607 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 54000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 54000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28973.365886 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28973.365886 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28973.365886 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28973.365886 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 59 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 410 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 410 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28191449 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28191449 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28191449 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28191449 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001247 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001247 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002439 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002439 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000324 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000324 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000324 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000324 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43666.830226 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 43666.830226 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42866.010118 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42866.010118 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 42955.458292 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 42955.458292 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 42955.458292 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 42955.458292 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 11029 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 474 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 23.267932 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 107 # number of writebacks -system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 428 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 428 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6343 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6343 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6771 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6771 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6771 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6771 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 508 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 508 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1732 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1732 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 108 # number of writebacks +system.cpu.dcache.writebacks::total 108 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 508 # 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average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48121.751298 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 70000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 70000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48862.074421 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48862.074421 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48862.074421 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48862.074421 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2409.771273 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9224 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 49196.535797 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 46916.444105 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 45312.154696 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 49196.535797 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 46916.444105 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 21.500000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3082 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 455 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3537 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3077 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3535 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1707 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1707 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3082 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2162 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5244 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3082 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2162 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5244 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 74145562 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15695119 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 89840681 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48589265 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48589265 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74145562 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 64284384 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 138429946 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74145562 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 64284384 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 138429946 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.251839 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.893910 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.277477 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985566 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985566 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.251839 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964748 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.362180 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.251839 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964748 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.362180 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 24057.612589 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34494.767033 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 25400.249081 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28464.712947 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28464.712947 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 24057.612589 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29733.757632 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 26397.777651 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 24057.612589 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29733.757632 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 26397.777651 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3077 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5242 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3077 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5242 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 100633163 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19510628 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 120143791 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60209566 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60209566 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 100633163 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79720194 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 180353357 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 100633163 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79720194 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 180353357 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.253334 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894531 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.279270 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984997 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984997 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.253334 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.364255 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.253334 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.364255 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32704.960351 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42599.624454 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33986.928147 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35272.153486 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35272.153486 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32704.960351 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36822.260508 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34405.447730 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32704.960351 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36822.260508 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34405.447730 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 49d6eef8e..3d59bfc93 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.075917 # Number of seconds simulated -sim_ticks 75916922000 # Number of ticks simulated -final_tick 75916922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.075963 # Number of seconds simulated +sim_ticks 75962996000 # Number of ticks simulated +final_tick 75962996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139176 # Simulator instruction rate (inst/s) -host_op_rate 152383 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61310301 # Simulator tick rate (ticks/s) -host_mem_usage 236468 # Number of bytes of host memory used -host_seconds 1238.24 # Real time elapsed on the host -sim_insts 172333316 # Number of instructions simulated -sim_ops 188686798 # Number of ops (including micro ops) simulated +host_inst_rate 82470 # Simulator instruction rate (inst/s) +host_op_rate 90296 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36352186 # Simulator tick rate (ticks/s) +host_mem_usage 236740 # Number of bytes of host memory used +host_seconds 2089.64 # Real time elapsed on the host +sim_insts 172333241 # Number of instructions simulated +sim_ops 188686723 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 132736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112320 # Number of bytes read from this memory -system.physmem.bytes_read::total 245056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory +system.physmem.bytes_read::total 244928 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 132736 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 132736 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 2074 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1755 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3829 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1748438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1479512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3227950 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1748438 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1748438 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1748438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1479512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3227950 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3829 # Total number of read requests seen +system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3827 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1747377 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1476930 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3224307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1747377 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1747377 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1747377 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1476930 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3224307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3828 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 3829 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 245056 # Total number of bytes read from memory +system.physmem.bytesRead 244928 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 245056 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 244928 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed system.physmem.perBankRdReqs::0 320 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 234 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 192 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 239 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 240 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 228 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 195 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 194 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 224 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 283 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 245 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 284 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 247 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 249 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 248 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 265 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 250 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 263 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 249 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 236 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 181 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 182 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 238 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 75916775000 # Total gap between requests +system.physmem.totGap 75962976500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 3829 # Categorize read packet sizes +system.physmem.readPktSize::6 3828 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -95,16 +95,16 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 1 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 2774 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 838 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 44 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2829 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 799 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 12309321 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 87055321 # Sum of mem lat for all requests -system.physmem.totBusLat 15316000 # Total cycles spent in databus access -system.physmem.totBankLat 59430000 # Total cycles spent in bank access -system.physmem.avgQLat 3214.76 # Average queueing delay per request -system.physmem.avgBankLat 15521.02 # Average bank access latency per request +system.physmem.totQLat 15909310 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 90413310 # Sum of mem lat for all requests +system.physmem.totBusLat 15312000 # Total cycles spent in databus access +system.physmem.totBankLat 59192000 # Total cycles spent in bank access +system.physmem.avgQLat 4156.04 # Average queueing delay per request +system.physmem.avgBankLat 15462.90 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22735.79 # Average memory access latency -system.physmem.avgRdBW 3.23 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 23618.94 # Average memory access latency +system.physmem.avgRdBW 3.22 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.23 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.22 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 3315 # Number of row buffer hits during reads +system.physmem.readRowHits 3324 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.58 # Row buffer hit rate for reads +system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19826788.98 # Average gap between requests +system.physmem.avgGap 19844037.75 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -228,141 +228,143 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 151833845 # number of cpu cycles simulated +system.cpu.numCycles 151925993 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 96840599 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 76060531 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 6557597 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 46497854 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 44230275 # Number of BTB hits +system.cpu.BPredUnit.lookups 96812188 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 76032236 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 6553809 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 46446152 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 44209779 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4471070 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 89483 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 40605581 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 388281645 # Number of instructions fetch has processed -system.cpu.fetch.Branches 96840599 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48701345 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 82243787 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 28438511 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7066827 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8646 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4476893 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 89558 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 40612935 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 388214882 # Number of instructions fetch has processed +system.cpu.fetch.Branches 96812188 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48686672 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 82228989 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 28431080 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7111966 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9226 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 37664937 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1885880 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 151789722 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.799994 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.153176 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 37654254 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1887415 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 151824267 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.799061 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.153208 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 69716020 45.93% 45.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5494868 3.62% 49.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10713361 7.06% 56.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10448438 6.88% 63.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8787039 5.79% 69.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6829673 4.50% 73.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6296859 4.15% 77.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8361926 5.51% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 25141538 16.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 69765849 45.95% 45.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5500538 3.62% 49.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10700560 7.05% 56.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10437997 6.88% 63.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8786758 5.79% 69.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6834684 4.50% 73.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6296298 4.15% 77.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8361211 5.51% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 25140372 16.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151789722 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.637806 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.557280 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 46630303 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5777884 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76557243 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1112705 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 21711587 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14823931 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 162890 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401294311 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 730539 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 21711587 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 52135013 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 698137 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 692737 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 72105161 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4447087 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 379004822 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 318070 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3558685 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 642471315 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1614529203 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1596934770 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17594433 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298092611 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 344378704 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 33379 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 33376 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12572106 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43979277 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16887724 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5767479 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3738298 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 334855562 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 55454 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 252836764 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 889769 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 145001031 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 373941866 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4179 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151789722 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.665704 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.759623 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151824267 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.637233 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.555289 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 46639472 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5819765 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76543741 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1113557 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 21707732 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14816289 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 162918 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401266810 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 729123 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 21707732 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 52145776 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 716376 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 699385 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 72090483 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4464515 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 378976726 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 316631 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3575950 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 15 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 642441440 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1614452334 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1596874036 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17578298 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298092491 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 344348949 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 33473 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 33471 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12628265 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43987484 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16888261 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5791013 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3746055 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 334831031 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 55567 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 252811108 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 890392 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 144974552 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 373956822 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4307 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151824267 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.665156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.759693 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 58337035 38.43% 38.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22987248 15.14% 53.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25139726 16.56% 70.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20501728 13.51% 83.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12883464 8.49% 92.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6586273 4.34% 96.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4061259 2.68% 99.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1111807 0.73% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 181182 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 58367016 38.44% 38.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23007793 15.15% 53.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25146514 16.56% 70.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20482198 13.49% 83.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12879503 8.48% 92.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6581643 4.34% 96.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4062886 2.68% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1113562 0.73% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 183152 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151789722 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151824267 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 964155 37.62% 37.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5594 0.22% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 94 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 1 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 24 0.00% 37.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1191140 46.48% 84.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 401719 15.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 966665 37.55% 37.55% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5596 0.22% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 94 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 27 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1198357 46.55% 84.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 403391 15.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 197361954 78.06% 78.06% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 995375 0.39% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 197328873 78.05% 78.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 995382 0.39% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued @@ -381,419 +383,423 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33153 0.01% 78.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164117 0.06% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 255226 0.10% 78.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76451 0.03% 78.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 467799 0.19% 78.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206454 0.08% 78.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71861 0.03% 78.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 78.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 39017631 15.43% 94.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 14186422 5.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33194 0.01% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 163810 0.06% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 255234 0.10% 78.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76440 0.03% 78.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 467356 0.18% 78.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206283 0.08% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71857 0.03% 78.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 39021114 15.43% 94.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 14191245 5.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 252836764 # Type of FU issued -system.cpu.iq.rate 1.665220 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2562727 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010136 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 657141484 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 477682512 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 240592268 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3774262 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2248392 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1852132 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 253504217 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1895274 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2034571 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 252811108 # Type of FU issued +system.cpu.iq.rate 1.664041 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2574130 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010182 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 657138452 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 477635375 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 240576408 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3772553 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2244745 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1851453 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 253490963 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1894275 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2028433 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14123734 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 16793 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19636 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4237031 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14131956 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 16953 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19730 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4237583 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 84 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 21711587 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4884 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 553 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 334928786 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 838607 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43979277 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16887724 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 32914 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 218 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19636 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4106046 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3927041 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8033087 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 245835770 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 37393574 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7000994 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 21707732 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16237 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 835 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 334904365 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 834808 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43987484 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16888261 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 33011 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 182 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 269 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19730 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4101344 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3925912 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8027256 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 245818022 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 37400003 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6993086 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17770 # number of nop insts executed -system.cpu.iew.exec_refs 51200144 # number of memory reference insts executed -system.cpu.iew.exec_branches 54041718 # Number of branches executed -system.cpu.iew.exec_stores 13806570 # Number of stores executed -system.cpu.iew.exec_rate 1.619110 # Inst execution rate -system.cpu.iew.wb_sent 243578722 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 242444400 # cumulative count of insts written-back -system.cpu.iew.wb_producers 150079170 # num instructions producing a value -system.cpu.iew.wb_consumers 269183647 # num instructions consuming a value +system.cpu.iew.exec_nop 17767 # number of nop insts executed +system.cpu.iew.exec_refs 51208402 # number of memory reference insts executed +system.cpu.iew.exec_branches 54033495 # Number of branches executed +system.cpu.iew.exec_stores 13808399 # Number of stores executed +system.cpu.iew.exec_rate 1.618012 # Inst execution rate +system.cpu.iew.wb_sent 243559168 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 242427861 # cumulative count of insts written-back +system.cpu.iew.wb_producers 150062323 # num instructions producing a value +system.cpu.iew.wb_consumers 269174598 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.596774 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557534 # average fanout of values written-back +system.cpu.iew.wb_rate 1.595697 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.557491 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 146227575 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 51275 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6404316 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 130078136 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.450676 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.162324 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 146203238 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 51260 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 6400494 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 130116536 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.450247 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.162155 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59851320 46.01% 46.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 32072665 24.66% 70.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13982527 10.75% 81.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7658050 5.89% 87.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4412794 3.39% 90.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1335206 1.03% 91.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1737015 1.34% 93.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1288451 0.99% 94.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7740108 5.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59888298 46.03% 46.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 32076129 24.65% 70.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13982572 10.75% 81.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7654340 5.88% 87.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4412681 3.39% 90.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1335897 1.03% 91.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1741211 1.34% 93.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1283921 0.99% 94.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7741487 5.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 130078136 # Number of insts commited each cycle -system.cpu.commit.committedInsts 172347704 # Number of instructions committed -system.cpu.commit.committedOps 188701186 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 130116536 # Number of insts commited each cycle +system.cpu.commit.committedInsts 172347629 # Number of instructions committed +system.cpu.commit.committedOps 188701111 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42506236 # Number of memory references committed -system.cpu.commit.loads 29855543 # Number of loads committed +system.cpu.commit.refs 42506206 # Number of memory references committed +system.cpu.commit.loads 29855528 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40306370 # Number of branches committed +system.cpu.commit.branches 40306355 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150130453 # Number of committed integer instructions. +system.cpu.commit.int_insts 150130393 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7740108 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7741487 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 457261588 # The number of ROB reads -system.cpu.rob.rob_writes 691688263 # The number of ROB writes -system.cpu.timesIdled 1182 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 44123 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 172333316 # Number of Instructions Simulated -system.cpu.committedOps 188686798 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 172333316 # Number of Instructions Simulated -system.cpu.cpi 0.881048 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.881048 # CPI: Total CPI of All Threads -system.cpu.ipc 1.135013 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.135013 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1091959933 # number of integer regfile reads -system.cpu.int_regfile_writes 388658885 # number of integer regfile writes -system.cpu.fp_regfile_reads 2913610 # number of floating regfile reads -system.cpu.fp_regfile_writes 2511674 # number of floating regfile writes -system.cpu.misc_regfile_reads 474503072 # number of misc regfile reads -system.cpu.misc_regfile_writes 832154 # number of misc regfile writes -system.cpu.icache.replacements 2619 # number of replacements -system.cpu.icache.tagsinuse 1372.300046 # Cycle average of tags in use -system.cpu.icache.total_refs 37659845 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4361 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8635.598487 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 457274197 # The number of ROB reads +system.cpu.rob.rob_writes 691635591 # The number of ROB writes +system.cpu.timesIdled 2582 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 101726 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 172333241 # Number of Instructions Simulated +system.cpu.committedOps 188686723 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 172333241 # Number of Instructions Simulated +system.cpu.cpi 0.881583 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.881583 # CPI: Total CPI of All Threads +system.cpu.ipc 1.134324 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.134324 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1091906245 # number of integer regfile reads +system.cpu.int_regfile_writes 388600616 # number of integer regfile writes +system.cpu.fp_regfile_reads 2911397 # number of floating regfile reads +system.cpu.fp_regfile_writes 2511024 # number of floating regfile writes +system.cpu.misc_regfile_reads 474438629 # number of misc regfile reads +system.cpu.misc_regfile_writes 832124 # number of misc regfile writes +system.cpu.icache.replacements 2644 # number of replacements +system.cpu.icache.tagsinuse 1367.286315 # Cycle average of tags in use +system.cpu.icache.total_refs 37648759 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4386 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8583.848381 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1372.300046 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.670068 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.670068 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37659851 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37659851 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37659851 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37659851 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37659851 # number of overall hits -system.cpu.icache.overall_hits::total 37659851 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5086 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5086 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5086 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5086 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5086 # number of overall misses -system.cpu.icache.overall_misses::total 5086 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 90441000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 90441000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 90441000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 90441000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 90441000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 90441000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37664937 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37664937 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37664937 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37664937 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37664937 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37664937 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000135 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000135 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000135 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000135 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000135 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000135 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17782.343689 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17782.343689 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17782.343689 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17782.343689 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17782.343689 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17782.343689 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1367.286315 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.667620 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.667620 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37648759 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37648759 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37648759 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37648759 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37648759 # number of overall hits +system.cpu.icache.overall_hits::total 37648759 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5495 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5495 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5495 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5495 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5495 # number of overall misses +system.cpu.icache.overall_misses::total 5495 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 164010000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 164010000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 164010000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 164010000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 164010000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 164010000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37654254 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37654254 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37654254 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37654254 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29847.133758 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29847.133758 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29847.133758 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 669 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 37.166667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # 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Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25318.497859 # Average number of references to valid blocks. +system.cpu.dcache.replacements 57 # number of replacements +system.cpu.dcache.tagsinuse 1416.459985 # Cycle average of tags in use +system.cpu.dcache.total_refs 47307506 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1862 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 25406.823845 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1419.994069 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.346678 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.346678 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34879202 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34879202 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356978 # 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number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 47258495 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 47258495 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 47258495 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 47258495 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000057 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000057 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000196 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000196 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000196 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000196 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27894.790603 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27894.790603 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21625.324942 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21625.324942 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22949.983814 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22949.983814 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22949.983814 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22949.983814 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000205 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000205 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000205 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000205 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45479.462475 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 45479.462475 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38644.436869 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38644.436869 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40033.704082 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40033.704082 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40033.704082 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40033.704082 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 45 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.363636 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 18 # number of writebacks system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1172 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1172 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6221 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6221 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1197 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1197 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6641 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6641 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7393 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7393 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7393 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7393 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 786 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 786 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 51545500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51545500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 51545500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7838 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7838 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7838 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7838 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 775 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 775 # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1448.115408 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 540.474425 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.044193 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016494 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.060839 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 2281 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 92 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2373 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 3.999610 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1449.117125 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 535.607885 # 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number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1083 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4363 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1868 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 6231 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4363 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1868 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 6231 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.477195 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.882803 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.539044 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992613 # 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miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991736 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.991736 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.473900 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.947905 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.615138 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.473900 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.947905 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.615138 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47495.189995 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53024.817518 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 48865.593343 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43983.796296 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43983.796296 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47495.189995 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47492.634561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 47494.016649 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47495.189995 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47492.634561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 47494.016649 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -802,59 +808,67 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 13 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 21 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2074 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 680 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2754 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1075 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1075 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2074 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1755 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3829 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2074 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1755 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3829 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53338835 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19774493 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 73113328 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 23276655 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 23276655 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53338835 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 43051148 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 96389983 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53338835 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 43051148 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 96389983 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.475361 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.866242 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.534965 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992613 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992613 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.475361 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.939507 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.614508 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.475361 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.939507 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.614508 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 25717.856798 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 29080.136765 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 26548.049383 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 21652.702326 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 21652.702326 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 25717.856798 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 24530.568661 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 25173.670149 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 25717.856798 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 24530.568661 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 25173.670149 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2075 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 673 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2748 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1080 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1080 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2075 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1753 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3828 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2075 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1753 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3828 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 72306456 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27405972 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 99712428 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33965187 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33965187 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 72306456 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 61371159 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 133677615 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 72306456 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 61371159 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 133677615 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.472988 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870634 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.532558 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991736 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991736 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.472988 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941461 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.612578 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.472988 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941461 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.612578 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34846.484819 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40722.098068 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36285.454148 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31449.247222 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31449.247222 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34846.484819 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35009.217912 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34921.007053 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34846.484819 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35009.217912 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34921.007053 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 17b1f3559..e84462d08 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.084594 # Number of seconds simulated -sim_ticks 84594088000 # Number of ticks simulated -final_tick 84594088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.084675 # Number of seconds simulated +sim_ticks 84674525000 # Number of ticks simulated +final_tick 84674525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94248 # Simulator instruction rate (inst/s) -host_op_rate 157968 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60367706 # Simulator tick rate (ticks/s) -host_mem_usage 238096 # Number of bytes of host memory used -host_seconds 1401.31 # Real time elapsed on the host +host_inst_rate 95140 # Simulator instruction rate (inst/s) +host_op_rate 159463 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60996786 # Simulator tick rate (ticks/s) +host_mem_usage 238356 # Number of bytes of host memory used +host_seconds 1388.18 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362960 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 220544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124864 # Number of bytes read from this memory -system.physmem.bytes_read::total 345408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220544 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3446 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1951 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5397 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2607085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1476037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4083122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2607085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2607085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2607085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1476037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4083122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5399 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 219904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124736 # Number of bytes read from this memory +system.physmem.bytes_read::total 344640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219904 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3436 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1949 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5385 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2597050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1473123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4070173 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2597050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2597050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2597050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1473123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4070173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5387 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5664 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 345408 # Total number of bytes read from memory +system.physmem.cpureqs 5559 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 344640 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 345408 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 344640 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 265 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 309 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 318 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 172 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 307 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 316 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 319 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 318 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 319 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 372 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 333 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 312 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 261 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 280 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 363 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 438 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 373 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 330 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 309 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 260 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 279 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 362 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 435 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 441 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 357 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 367 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 298 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 355 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 370 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 299 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 84594067000 # Total gap between requests +system.physmem.totGap 84674494000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5399 # Categorize read packet sizes +system.physmem.readPktSize::6 5387 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -95,16 +95,16 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 265 # categorize neither packet sizes +system.physmem.neitherpktsize::6 172 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 943 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 188 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -164,265 +164,266 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 16379877 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 123109877 # Sum of mem lat for all requests -system.physmem.totBusLat 21596000 # Total cycles spent in databus access +system.physmem.totQLat 14711866 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 121393866 # Sum of mem lat for all requests +system.physmem.totBusLat 21548000 # Total cycles spent in databus access system.physmem.totBankLat 85134000 # Total cycles spent in bank access -system.physmem.avgQLat 3033.87 # Average queueing delay per request -system.physmem.avgBankLat 15768.48 # Average bank access latency per request +system.physmem.avgQLat 2730.99 # Average queueing delay per request +system.physmem.avgBankLat 15803.60 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22802.35 # Average memory access latency -system.physmem.avgRdBW 4.08 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22534.60 # Average memory access latency +system.physmem.avgRdBW 4.07 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 4.08 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 4.07 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4777 # Number of row buffer hits during reads +system.physmem.readRowHits 4765 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.48 # Row buffer hit rate for reads +system.physmem.readRowHitRate 88.45 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15668469.53 # Average gap between requests +system.physmem.avgGap 15718302.21 # Average gap between requests system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 169188177 # number of cpu cycles simulated +system.cpu.numCycles 169349051 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 20680258 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 20680258 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2246160 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15085015 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 13721428 # Number of BTB hits +system.cpu.BPredUnit.lookups 20696936 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 20696936 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2256292 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15133236 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 13734962 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27164568 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 227213982 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20680258 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13721428 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59660749 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 19257155 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 65568957 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 236 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1768 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 25653013 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 474244 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169131808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.211225 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.333765 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27265023 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 227328092 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20696936 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13734962 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59711428 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 19294366 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 65485440 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 310 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1823 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 77 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 25705537 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 473097 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169231475 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.210885 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.333405 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 111136116 65.71% 65.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3216747 1.90% 67.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2468197 1.46% 69.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3082745 1.82% 70.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3525528 2.08% 72.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3731818 2.21% 75.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4565922 2.70% 77.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2807540 1.66% 79.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 34597195 20.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 111185486 65.70% 65.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3235568 1.91% 67.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2477028 1.46% 69.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3104255 1.83% 70.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3512943 2.08% 72.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3722385 2.20% 75.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4581451 2.71% 77.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2802404 1.66% 79.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34609955 20.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169131808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122232 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.342966 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 40083092 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 55790408 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46646195 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9876583 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16735530 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 364948187 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 16735530 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 47642140 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14699446 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23267 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 48304644 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 41726781 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355757826 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 35 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17417112 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22198638 # Number of times rename has blocked due to LSQ full +system.cpu.fetch.rateDist::total 169231475 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122215 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.342364 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40175646 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 55730709 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46717910 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9839836 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16767374 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 365014393 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16767374 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 47729605 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14672331 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23050 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 48352284 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 41686831 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355859336 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 104 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17343697 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22236120 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 51 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 410011414 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 986948203 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 977030227 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9917976 # Number of floating rename lookups +system.cpu.rename.RenamedOperands 410085130 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 987094969 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 977133981 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9960988 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259428603 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 150582811 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1844 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1841 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 90083407 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89641616 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 32814586 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 59002795 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 19228439 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 342836678 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4827 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 271794183 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 309279 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 120959244 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 246380396 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3581 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169131808 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.606996 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.512238 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 150656527 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1756 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1746 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 90004350 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89661097 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 32850020 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59013027 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 19193820 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 342911318 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4601 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 271901324 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 302838 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 121030414 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 246288577 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3355 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169231475 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.606683 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.513723 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 47364329 28.00% 28.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46969212 27.77% 55.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33133132 19.59% 75.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20170100 11.93% 87.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 13409099 7.93% 95.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4965437 2.94% 98.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2407480 1.42% 99.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 564206 0.33% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 148813 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 47472289 28.05% 28.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 47010231 27.78% 55.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33048937 19.53% 75.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20116720 11.89% 87.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 13476087 7.96% 95.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4976431 2.94% 98.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2409834 1.42% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 570016 0.34% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 150930 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169131808 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169231475 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 133221 5.02% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2254463 85.01% 90.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 264273 9.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 133953 5.05% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.05% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2250624 84.89% 89.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 266784 10.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212759 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 177009113 65.13% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212972 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 177077896 65.13% 65.57% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.57% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1584136 0.58% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 68507132 25.21% 91.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23481043 8.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1583975 0.58% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 68517375 25.20% 91.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23509106 8.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 271794183 # Type of FU issued -system.cpu.iq.rate 1.606461 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2651957 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009757 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 710390564 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 459507075 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 264054683 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5290846 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4594594 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2539782 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 270581714 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2651667 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19012084 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 271901324 # Type of FU issued +system.cpu.iq.rate 1.605567 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2651361 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009751 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 710689981 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 459620232 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 264156330 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5298341 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4622160 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2541189 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 270684077 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2655636 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19034495 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 32992030 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 32876 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 306652 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12298870 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 33011511 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 33645 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 301635 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12334304 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49471 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 49870 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 57 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16735530 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 583808 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 272322 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 342841505 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 257255 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89641616 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 32814586 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1824 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 184475 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 30365 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 306652 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1330858 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1021453 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2352311 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 268621044 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 67379328 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3173139 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16767374 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 579251 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 261764 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 342915919 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 264352 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89661097 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 32850020 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1726 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 174105 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29972 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 301635 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1337300 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1023491 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2360791 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 268724619 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 67385634 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3176705 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 90456785 # number of memory reference insts executed -system.cpu.iew.exec_branches 14766526 # Number of branches executed -system.cpu.iew.exec_stores 23077457 # Number of stores executed -system.cpu.iew.exec_rate 1.587706 # Inst execution rate -system.cpu.iew.wb_sent 267534302 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 266594465 # cumulative count of insts written-back -system.cpu.iew.wb_producers 215217179 # num instructions producing a value -system.cpu.iew.wb_consumers 378376353 # num instructions consuming a value +system.cpu.iew.exec_refs 90490308 # number of memory reference insts executed +system.cpu.iew.exec_branches 14777839 # Number of branches executed +system.cpu.iew.exec_stores 23104674 # Number of stores executed +system.cpu.iew.exec_rate 1.586809 # Inst execution rate +system.cpu.iew.wb_sent 267641874 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 266697519 # cumulative count of insts written-back +system.cpu.iew.wb_producers 215269478 # num instructions producing a value +system.cpu.iew.wb_consumers 378445061 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.575728 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.568791 # average fanout of values written-back +system.cpu.iew.wb_rate 1.574839 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.568826 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 121559121 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 121635359 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2246323 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 152396278 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.452548 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.926116 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2256476 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 152464101 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.451902 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.927405 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 52678390 34.57% 34.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57577424 37.78% 72.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14059718 9.23% 81.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11956991 7.85% 89.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4305123 2.82% 92.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2949818 1.94% 94.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1066386 0.70% 94.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 992195 0.65% 95.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6810233 4.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 52775060 34.61% 34.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57579919 37.77% 72.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14057130 9.22% 81.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11929298 7.82% 89.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4294184 2.82% 92.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2937870 1.93% 94.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1056484 0.69% 94.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 997351 0.65% 95.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6836805 4.48% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 152396278 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 152464101 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221362960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -433,306 +434,306 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339549 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6810233 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6836805 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 488508126 # The number of ROB reads -system.cpu.rob.rob_writes 702620216 # The number of ROB writes -system.cpu.timesIdled 1506 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 56369 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 488625615 # The number of ROB reads +system.cpu.rob.rob_writes 702805180 # The number of ROB writes +system.cpu.timesIdled 3014 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 117576 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221362960 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 1.281038 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.281038 # CPI: Total CPI of All Threads -system.cpu.ipc 0.780617 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.780617 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 567639196 # number of integer regfile reads -system.cpu.int_regfile_writes 302703765 # number of integer regfile writes -system.cpu.fp_regfile_reads 3495797 # number of floating regfile reads -system.cpu.fp_regfile_writes 2211250 # number of floating regfile writes -system.cpu.misc_regfile_reads 139399302 # number of misc regfile reads +system.cpu.cpi 1.282256 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.282256 # CPI: Total CPI of All Threads +system.cpu.ipc 0.779876 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.779876 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 567778401 # number of integer regfile reads +system.cpu.int_regfile_writes 302773713 # number of integer regfile writes +system.cpu.fp_regfile_reads 3495333 # number of floating regfile reads +system.cpu.fp_regfile_writes 2213146 # number of floating regfile writes +system.cpu.misc_regfile_reads 139456752 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 5641 # number of replacements -system.cpu.icache.tagsinuse 1641.401127 # Cycle average of tags in use -system.cpu.icache.total_refs 25643925 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7612 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3368.881372 # Average number of references to valid blocks. +system.cpu.icache.replacements 5349 # number of replacements +system.cpu.icache.tagsinuse 1642.940012 # Cycle average of tags in use +system.cpu.icache.total_refs 25695767 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7318 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3511.310057 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1641.401127 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.801465 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.801465 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25643925 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25643925 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25643925 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25643925 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25643925 # number of overall hits -system.cpu.icache.overall_hits::total 25643925 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9088 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9088 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9088 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9088 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9088 # number of overall misses -system.cpu.icache.overall_misses::total 9088 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 147639500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 147639500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 147639500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 147639500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 147639500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 147639500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25653013 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25653013 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25653013 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25653013 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25653013 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25653013 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000354 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000354 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000354 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000354 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000354 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000354 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16245.543574 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16245.543574 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16245.543574 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16245.543574 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16245.543574 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16245.543574 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1642.940012 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.802217 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.802217 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25695767 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25695767 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25695767 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25695767 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25695767 # number of overall hits +system.cpu.icache.overall_hits::total 25695767 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9770 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9770 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9770 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9770 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9770 # number of overall misses +system.cpu.icache.overall_misses::total 9770 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 270457998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 270457998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 270457998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 270457998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 270457998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 270457998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25705537 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25705537 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25705537 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25705537 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25705537 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25705537 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000380 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000380 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000380 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000380 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000380 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000380 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27682.497236 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27682.497236 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27682.497236 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27682.497236 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27682.497236 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27682.497236 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 937 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 36.038462 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1211 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1211 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1211 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1211 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1211 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1211 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7877 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7877 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7877 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7877 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7877 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7877 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 110101000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 110101000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 110101000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 110101000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 110101000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 110101000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000307 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000307 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000307 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13977.529516 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13977.529516 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13977.529516 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13977.529516 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13977.529516 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13977.529516 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2279 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2279 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2279 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2279 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2279 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2279 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7491 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7491 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7491 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7491 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7491 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7491 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 205062498 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 205062498 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 205062498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 205062498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 205062498 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 205062498 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000291 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000291 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000291 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000291 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000291 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000291 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27374.515819 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27374.515819 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27374.515819 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27374.515819 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27374.515819 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27374.515819 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # 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number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 48199007 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 48199007 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 1425.106127 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.347926 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.347926 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 48181413 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 48181413 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513994 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513994 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68695407 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68695407 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68695407 # 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miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000085 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000085 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37048.979592 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37048.979592 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24669.857768 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24669.857768 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28219.859540 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28219.859540 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28219.859540 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28219.859540 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46282.129743 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 46282.129743 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44225.806452 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44225.806452 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 44883.862123 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 44883.862123 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 44883.862123 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 44883.862123 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 262 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 15 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 28319.252432 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 28354.880533 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994882 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994882 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.469463 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.979910 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.578625 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.469463 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.979910 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.578625 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46150.320140 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55232.323232 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 47088.856994 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43543.729904 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43543.729904 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46150.320140 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 45916.196822 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 46065.528123 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46150.320140 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 45916.196822 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 46065.528123 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -741,58 +742,58 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3446 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 401 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3847 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 265 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 265 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1552 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115214557 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 64882583 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 180097140 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115214557 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 64882583 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 180097140 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.469463 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.925234 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.494643 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994872 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994872 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.452706 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980422 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.562162 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.452706 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980422 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.562162 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 24764.514510 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38259.628429 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 26171.205615 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 1001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 1001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 21214.230670 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 21214.230670 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 24764.514510 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 24714.079365 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 24746.270420 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 24764.514510 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 24714.079365 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 24746.270420 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994882 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994882 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.469463 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.979910 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.578625 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.469463 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.979910 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.578625 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33531.594005 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42723.724747 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34481.511482 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30845.008360 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30845.008360 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33531.594005 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33256.065095 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33431.806200 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33531.594005 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33256.065095 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33431.806200 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |