diff options
| author | Gabe Black <gabeblack@google.com> | 2017-03-29 21:40:35 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-04-05 18:37:50 +0000 |
| commit | a01c13293ad4ad7e4f6ddf67a999479fd6550404 (patch) | |
| tree | b7fdec25d1b7fe973a99deb81fb4e980249f3ee5 /tests/long | |
| parent | 4ca8314077deb31ab184805f4ef8aab37fe68f01 (diff) | |
| download | gem5-a01c13293ad4ad7e4f6ddf67a999479fd6550404.tar.xz | |
stats: Update 01.hello-2T-smt and 40.perlbmks stats on ARM/Alpha o3-timing.
The following change removed a write to an integer register when completing
a system call. This changed the reference statistics slightly.
commit 073cb266079edddec64ea8cd5169dd2cbef8f812
Author: Brandon Potter <brandon.potter@amd.com>
Date: Mon Feb 27 14:10:02 2017 -0500
syscall_emul: [patch 14/22] adds identifier system calls
Change-Id: I3bee42ab826dd9cbc49aab34340da57caf4f045d
Reviewed-on: https://gem5-review.googlesource.com/2650
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/long')
4 files changed, 1345 insertions, 1313 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 155d03811..5d9ef8c4a 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -65,7 +65,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -141,6 +141,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -176,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 @@ -193,6 +194,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=8 write_buffers=16 @@ -205,15 +207,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -316,38 +319,52 @@ pipelined=true [system.cpu.fuPool.FUList2] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 -[system.cpu.fuPool.FUList2.opList] +[system.cpu.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=2 pipelined=true +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList3] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 -[system.cpu.fuPool.FUList3.opList] +[system.cpu.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=2 pipelined=true +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList4] type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 +opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27 [system.cpu.fuPool.FUList4.opList00] type=OpDesc @@ -479,7 +496,7 @@ pipelined=true type=OpDesc eventq_index=0 opClass=SimdFloatMultAcc -opLat=1 +opLat=5 pipelined=true [system.cpu.fuPool.FUList4.opList19] @@ -531,6 +548,20 @@ opClass=FloatMult opLat=4 pipelined=true +[system.cpu.fuPool.FUList4.opList26] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList4.opList27] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + [system.cpu.icache] type=Cache children=tags @@ -538,10 +569,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=1 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 @@ -555,6 +586,7 @@ response_latency=1 sequential_access=false size=32768 system=system +tag_latency=1 tags=system.cpu.icache.tags tgts_per_mshr=8 write_buffers=8 @@ -567,15 +599,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=1 default_p_state=UNDEFINED eventq_index=0 -hit_latency=1 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=1 [system.cpu.interrupts] type=ArmInterrupts @@ -594,8 +627,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -606,8 +637,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -670,10 +699,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +data_latency=12 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 @@ -687,6 +716,7 @@ response_latency=12 sequential_access=false size=1048576 system=system +tag_latency=12 tags=system.cpu.l2cache.tags tgts_per_mshr=8 write_buffers=8 @@ -729,15 +759,16 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=12 default_p_state=UNDEFINED eventq_index=0 -hit_latency=12 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=1048576 +tag_latency=12 [system.cpu.toL2Bus] type=CoherentXBar @@ -773,7 +804,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=perlbmk -I. -I lib mdred.makerand.pl cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing drivers= @@ -782,14 +813,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin kvmInSE=false max_stack_size=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr index c1f3592f9..a0d2c5ece 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr @@ -1,4 +1,7 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: fcntl64(3, 2) passed through to host +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 4ad08cdbb..fb1e27e73 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -3,15 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:55:26 -gem5 executing on e108600-lin, pid 17505 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/o3-timing +gem5 compiled Apr 2 2017 11:48:43 +gem5 started Apr 2 2017 11:49:00 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87253 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. 637000: 2581848540 636000: 4117852332 635000: 329081094 @@ -650,4 +647,4 @@ info: Increasing stack size by one page. 2000: 2845746745 1000: 2068042552 0: 290958364 -Exiting @ tick 339012932000 because target called exit() +Exiting @ tick 339069355000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 1f99db17b..e757c5929 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,1286 +1,1286 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.339069 # Number of seconds simulated -sim_ticks 339069355000 # Number of ticks simulated -final_tick 339069355000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 212003 # Simulator instruction rate (inst/s) -host_op_rate 261004 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 112204360 # Simulator tick rate (ticks/s) -host_mem_usage 277184 # Number of bytes of host memory used -host_seconds 3021.89 # Real time elapsed on the host -sim_insts 640649299 # Number of instructions simulated -sim_ops 788724958 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 272000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 48065856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12979392 # Number of bytes read from this memory -system.physmem.bytes_read::total 61317248 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 272000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 272000 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4246400 # Number of bytes written to this memory -system.physmem.bytes_written::total 4246400 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4250 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 751029 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 202803 # Number of read requests responded to by this memory -system.physmem.num_reads::total 958082 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66350 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66350 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 802196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 141758184 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 38279461 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 180839840 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 802196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 802196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 12523692 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 12523692 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 12523692 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 802196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 141758184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 38279461 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 193363532 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 958083 # Number of read requests accepted -system.physmem.writeReqs 66350 # Number of write requests accepted -system.physmem.readBursts 958083 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66350 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61296960 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20352 # Total number of bytes read from write queue -system.physmem.bytesWritten 4240000 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61317312 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4246400 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 318 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 71 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19910 # Per bank write bursts -system.physmem.perBankRdBursts::1 19573 # Per bank write bursts -system.physmem.perBankRdBursts::2 657828 # Per bank write bursts -system.physmem.perBankRdBursts::3 21032 # Per bank write bursts -system.physmem.perBankRdBursts::4 19718 # Per bank write bursts -system.physmem.perBankRdBursts::5 21045 # Per bank write bursts -system.physmem.perBankRdBursts::6 19700 # Per bank write bursts -system.physmem.perBankRdBursts::7 20038 # Per bank write bursts -system.physmem.perBankRdBursts::8 19491 # Per bank write bursts -system.physmem.perBankRdBursts::9 20101 # Per bank write bursts -system.physmem.perBankRdBursts::10 19540 # Per bank write bursts -system.physmem.perBankRdBursts::11 19692 # Per bank write bursts -system.physmem.perBankRdBursts::12 19618 # Per bank write bursts -system.physmem.perBankRdBursts::13 21105 # Per bank write bursts -system.physmem.perBankRdBursts::14 19493 # Per bank write bursts -system.physmem.perBankRdBursts::15 19881 # Per bank write bursts -system.physmem.perBankWrBursts::0 4272 # Per bank write bursts -system.physmem.perBankWrBursts::1 4107 # Per bank write bursts -system.physmem.perBankWrBursts::2 4147 # Per bank write bursts -system.physmem.perBankWrBursts::3 4153 # Per bank write bursts -system.physmem.perBankWrBursts::4 4251 # Per bank write bursts -system.physmem.perBankWrBursts::5 4229 # Per bank write bursts -system.physmem.perBankWrBursts::6 4174 # Per bank write bursts -system.physmem.perBankWrBursts::7 4096 # Per bank write bursts -system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4095 # Per bank write bursts -system.physmem.perBankWrBursts::10 4095 # Per bank write bursts -system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4094 # Per bank write bursts -system.physmem.perBankWrBursts::14 4095 # Per bank write bursts -system.physmem.perBankWrBursts::15 4151 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 339069344500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 958083 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66350 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 765133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120601 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7738 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 9158 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 10207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 6741 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3672 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1581 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 666 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 196319 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 333.816859 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 191.183939 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 355.380336 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 65406 33.32% 33.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 61086 31.12% 64.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15476 7.88% 72.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3179 1.62% 73.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3479 1.77% 75.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2336 1.19% 76.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2511 1.28% 78.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 34323 17.48% 95.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8523 4.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 196319 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4003 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 214.941294 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 35.155298 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2727.024521 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 3978 99.38% 99.38% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 12 0.30% 99.68% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-12287 3 0.07% 99.75% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-16383 4 0.10% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-20479 1 0.02% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32768-36863 1 0.02% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::36864-40959 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::69632-73727 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::126976-131071 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4003 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4003 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.550087 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.475287 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.816460 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3400 84.94% 84.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 19 0.47% 85.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 373 9.32% 94.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 54 1.35% 96.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 20 0.50% 96.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 27 0.67% 97.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 15 0.37% 97.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 21 0.52% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 14 0.35% 98.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 14 0.35% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 14 0.35% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 6 0.15% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 7 0.17% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 6 0.15% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.02% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 3 0.07% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 4 0.10% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 2 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4003 # Writes before turning the bus around for reads -system.physmem.totQLat 27518767878 # Total ticks spent queuing -system.physmem.totMemAccLat 45476861628 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4788825000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28732.28 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47482.28 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 180.78 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 12.50 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 180.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 12.52 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.51 # Data bus utilization in percentage -system.physmem.busUtilRead 1.41 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.37 # Average write queue length when enqueuing -system.physmem.readRowHits 804881 # Number of row buffer hits during reads -system.physmem.writeRowHits 22802 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 34.40 # Row buffer hit rate for writes -system.physmem.avgGap 330982.45 # Average gap between requests -system.physmem.pageHitRate 80.82 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 901474980 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 479122545 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5703739020 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 174499380 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 27325665120.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 14491103160 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 673386240 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 138371323560 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 679220160 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 661319340.000000 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 189506984115 # Total energy per rank (pJ) -system.physmem_0.averagePower 558.903308 # Core power per rank (mW) -system.physmem_0.totalIdleTime 305432505529 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 523884278 # Time in different power states -system.physmem_0.memoryStateTime::REF 11566244000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 219111500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 1768844578 # Time in different power states -system.physmem_0.memoryStateTime::ACT 21546721193 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 303444549451 # Time in different power states -system.physmem_1.actEnergy 500335500 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 265908060 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1134695940 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 171325620 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 25432573920.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6980276430 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1364879040 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 70621447890 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 30989177760 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 25472740305 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 162933984825 # Total energy per rank (pJ) -system.physmem_1.averagePower 480.532913 # Core power per rank (mW) -system.physmem_1.totalIdleTime 320205691246 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 2610959521 # Time in different power states -system.physmem_1.memoryStateTime::REF 10814464000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 84633345250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 80700935022 # Time in different power states -system.physmem_1.memoryStateTime::ACT 5438217483 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 154871433724 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 175312537 # Number of BP lookups -system.cpu.branchPred.condPredicted 119126010 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4023429 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 95987051 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67762694 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.595662 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18784914 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1299715 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 16714738 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 16702890 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 11848 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 1279488 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 339069355000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 678138711 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 35026134 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 824295259 # Number of instructions fetch has processed -system.cpu.fetch.Branches 175312537 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 103250498 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 638595633 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8083491 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2728 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3109 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 247757876 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 12590 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 677669366 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.498301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.263018 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 215620652 31.82% 31.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 148930568 21.98% 53.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72932404 10.76% 64.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 240185742 35.44% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 677669366 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258520 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.215526 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 75794919 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 258105460 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 277738151 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 62003234 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4027602 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 64856939 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 14426 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 924580293 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 10545635 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4027602 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 118744370 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 157469679 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 209680 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 295125429 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 102092606 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 906546743 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6881182 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 27980774 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2218296 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 49244088 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 491152 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 980952632 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4318034270 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1001843328 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34457465 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 106174402 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6852 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6837 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 138250974 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 271864033 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 160594184 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 6150346 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 12039275 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 899826395 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12582 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 860048195 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 9222152 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 111114019 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 244270336 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 428 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 677669366 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.269127 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.103925 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 215576710 31.81% 31.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 182398349 26.92% 58.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 173866168 25.66% 84.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 93397486 13.78% 98.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12428213 1.83% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2440 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 677669366 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 66592795 23.99% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18143 0.01% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 636888 0.23% 24.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 132895197 47.87% 72.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 66486163 23.95% 96.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 5670687 2.04% 98.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 5308776 1.91% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413112342 48.03% 48.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5187450 0.60% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.37% 49.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 2550158 0.30% 49.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478201 1.33% 50.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 259635092 30.19% 80.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 153408617 17.84% 98.74% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 7019173 0.82% 99.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 3831959 0.45% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 860048195 # Type of FU issued -system.cpu.iq.rate 1.268248 # Inst issue rate -system.cpu.iq.fu_busy_cnt 277608649 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.322783 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2621941266 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 980329396 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 820105906 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 62655291 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 30642249 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 24878687 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1100523479 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 37133365 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 13978556 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 19623095 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 150 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18653 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 31613688 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1918749 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 18225 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4027602 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10592950 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5943 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 899848973 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 271864033 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 160594184 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6842 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 932 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3107 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18653 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3297561 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3294434 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6591995 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 850188945 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 263367686 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9859250 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9996 # number of nop insts executed -system.cpu.iew.exec_refs 416059985 # number of memory reference insts executed -system.cpu.iew.exec_branches 143387028 # Number of branches executed -system.cpu.iew.exec_stores 152692299 # Number of stores executed -system.cpu.iew.exec_rate 1.253710 # Inst execution rate -system.cpu.iew.wb_sent 846316526 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 844984593 # cumulative count of insts written-back -system.cpu.iew.wb_producers 486213090 # num instructions producing a value -system.cpu.iew.wb_consumers 804713496 # num instructions consuming a value -system.cpu.iew.wb_rate 1.246035 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.604206 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 103170323 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4009286 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 663080037 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.189495 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.047357 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 372743600 56.21% 56.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 137229465 20.70% 76.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51343947 7.74% 84.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 28225650 4.26% 88.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 14387181 2.17% 91.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14772519 2.23% 93.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7871150 1.19% 94.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6554658 0.99% 95.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29951867 4.52% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 663080037 # Number of insts commited each cycle -system.cpu.commit.committedInsts 640654411 # Number of instructions committed -system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 381221434 # Number of memory references committed -system.cpu.commit.loads 252240938 # Number of loads committed -system.cpu.commit.membars 5740 # Number of memory barriers committed -system.cpu.commit.branches 137364860 # Number of branches committed -system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions. -system.cpu.commit.int_insts 682251399 # Number of committed integer instructions. -system.cpu.commit.function_calls 19275340 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 385756794 48.91% 48.91% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 245222568 31.09% 82.76% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 125149822 15.87% 98.62% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 7018370 0.89% 99.51% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 3830674 0.49% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 29951867 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1525019812 # The number of ROB reads -system.cpu.rob.rob_writes 1798395927 # The number of ROB writes -system.cpu.timesIdled 10540 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 469345 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 640649299 # Number of Instructions Simulated -system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.058518 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.058518 # CPI: Total CPI of All Threads -system.cpu.ipc 0.944717 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.944717 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 868485327 # number of integer regfile reads -system.cpu.int_regfile_writes 500716513 # number of integer regfile writes -system.cpu.fp_regfile_reads 30616072 # number of floating regfile reads -system.cpu.fp_regfile_writes 22959512 # number of floating regfile writes -system.cpu.cc_regfile_reads 3322428373 # number of cc regfile reads -system.cpu.cc_regfile_writes 369236255 # number of cc regfile writes -system.cpu.misc_regfile_reads 606835918 # number of misc regfile reads -system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2756526 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.910931 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 371056816 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2757038 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 134.585311 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 286323500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.910931 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999826 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999826 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 176 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 751754868 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 751754868 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 243133490 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 243133490 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127906319 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127906319 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 371039809 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 371039809 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 371042966 # number of overall hits -system.cpu.dcache.overall_hits::total 371042966 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2398664 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2398664 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1045158 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1045158 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3443822 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3443822 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3444469 # number of overall misses -system.cpu.dcache.overall_misses::total 3444469 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 80554008500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80554008500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9982772350 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9982772350 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 140000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 140000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 90536780850 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 90536780850 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 90536780850 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 90536780850 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 245532154 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 245532154 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3804 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 374483631 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 374483631 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 374487435 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 374487435 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009769 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009769 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008105 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008105 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000348 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000348 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009196 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009196 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009198 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009198 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33582.864670 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33582.864670 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9551.448059 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9551.448059 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26289.622649 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26289.622649 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26284.684475 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26284.684475 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 344610 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4869 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 70.776340 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2756526 # number of writebacks -system.cpu.dcache.writebacks::total 2756526 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 363119 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 363119 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323999 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 323999 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 687118 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 687118 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 687118 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 687118 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035545 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2035545 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721159 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 721159 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 642 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 642 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2756704 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2756704 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2757346 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2757346 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75270268500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75270268500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5954605850 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5954605850 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5576500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5576500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 81224874350 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 81224874350 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 81230450850 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 81230450850 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.008290 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008290 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005592 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005592 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168770 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168770 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007361 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.007361 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007363 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.007363 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36977.943745 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36977.943745 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8256.994435 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8256.994435 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8686.137072 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8686.137072 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29464.488879 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29464.488879 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29459.651001 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29459.651001 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1980658 # number of replacements -system.cpu.icache.tags.tagsinuse 510.043873 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 245773558 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1981168 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 124.054880 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 275783500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.043873 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996179 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996179 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 497497160 # Number of tag accesses -system.cpu.icache.tags.data_accesses 497497160 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 245773612 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 245773612 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 245773612 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 245773612 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 245773612 # number of overall hits -system.cpu.icache.overall_hits::total 245773612 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1984230 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1984230 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1984230 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1984230 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1984230 # number of overall misses -system.cpu.icache.overall_misses::total 1984230 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16225163428 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16225163428 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16225163428 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16225163428 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16225163428 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16225163428 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 247757842 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 247757842 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 247757842 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 247757842 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 247757842 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 247757842 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008009 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008009 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008009 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008009 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008009 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8177.057815 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8177.057815 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8177.057815 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8177.057815 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8177.057815 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8177.057815 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 86855 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 219 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3239 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 26.815375 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 31.285714 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1980658 # number of writebacks -system.cpu.icache.writebacks::total 1980658 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2752 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2752 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2752 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2752 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2752 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2752 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1981478 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1981478 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1981478 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1981478 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1981478 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1981478 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15191208442 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15191208442 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15191208442 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15191208442 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15191208442 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15191208442 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007998 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007998 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007998 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.007998 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007998 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.007998 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7666.604647 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7666.604647 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7666.604647 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7666.604647 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7666.604647 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7666.604647 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 1350180 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 1355046 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 4259 # number of redundant prefetches already in prefetch queue -system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4789962 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 297363 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16097.095848 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3953275 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 313560 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.607715 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15676.959856 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 420.135992 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.956846 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.025643 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.982489 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 460 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15737 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 63 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 274 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 116 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 407 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1553 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3714 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 9969 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.028076 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.960510 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 145611380 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 145611380 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 735645 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 735645 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3358020 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3358020 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 718668 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 718668 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1976918 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1976918 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1285460 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1285460 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1976918 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2004128 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3981046 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1976918 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2004128 # number of overall hits -system.cpu.l2cache.overall_hits::total 3981046 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 308 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 308 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 2183 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2183 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4253 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 4253 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 750727 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 750727 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 4253 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 752910 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 757163 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 4253 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 752910 # number of overall misses -system.cpu.l2cache.overall_misses::total 757163 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 189493000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 189493000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 353014500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 353014500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 63858972500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 63858972500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 353014500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 64048465500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 64401480000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 353014500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 64048465500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 64401480000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 735645 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 735645 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 3358020 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3358020 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 308 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 308 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 720851 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 720851 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1981171 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1981171 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036187 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 2036187 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1981171 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2757038 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 4738209 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1981171 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2757038 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 4738209 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003028 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.003028 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.002147 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.002147 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368693 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368693 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.002147 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.273087 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.159799 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.002147 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.273087 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.159799 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86803.939533 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86803.939533 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83003.644486 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83003.644486 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85062.842418 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85062.842418 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83003.644486 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85067.890585 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 85056.295672 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83003.644486 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85067.890585 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 85056.295672 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 3562 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 66350 # number of writebacks -system.cpu.l2cache.writebacks::total 66350 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 796 # number of ReadExReq MSHR hits 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# number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 751029 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 755280 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 4251 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 751029 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202894 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 958174 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 20344447507 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 20344447507 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4667000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4667000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 140070000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 140070000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 327411500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 327411500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59289686000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59289686000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 327411500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59429756000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 59757167500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 327411500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59429756000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 20344447507 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 80101615007 # number of overall MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001924 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001924 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002146 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002146 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.368160 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.368160 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002146 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272404 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.159402 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002146 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272404 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.202223 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100271.311655 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 100271.311655 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15152.597403 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15152.597403 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100987.743331 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100987.743331 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 77019.877676 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 77019.877676 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79090.667279 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79090.667279 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77019.877676 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79131.106788 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79119.223996 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77019.877676 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79131.106788 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100271.311655 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83598.193029 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 9476008 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 4737217 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 644846 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 94 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 93 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 4017663 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 801995 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4001539 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 231013 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 255559 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 308 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 308 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720851 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720851 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1981478 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036187 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5943305 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8271218 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 14214523 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253556928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352868096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 606425024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 553229 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4266048 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5291746 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.121883 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.327151 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 4646773 87.81% 87.81% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 644972 12.19% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5291746 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 9475188000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2972215996 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4135722477 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1255754 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 941197 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 956694 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66350 # Transaction distribution -system.membus.trans_dist::CleanEvict 231013 # Transaction distribution -system.membus.trans_dist::UpgradeReq 308 # Transaction distribution -system.membus.trans_dist::ReadExReq 1387 # Transaction distribution -system.membus.trans_dist::ReadExResp 1387 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 956696 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2213835 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2213835 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65563584 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 65563584 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 958391 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 958391 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 958391 # Request fanout histogram -system.membus.reqLayer0.occupancy 1760245062 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 5035040414 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.5 # Layer utilization (%) +sim_seconds 0.339069 +sim_ticks 339069355000 +final_tick 339069355000 +sim_freq 1000000000000 +host_inst_rate 200289 +host_op_rate 246583 +host_tick_rate 106004783 +host_mem_usage 288044 +host_seconds 3198.62 +sim_insts 640649299 +sim_ops 788724958 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 339069355000 +system.physmem.bytes_read::cpu.inst 272000 +system.physmem.bytes_read::cpu.data 48065856 +system.physmem.bytes_read::cpu.l2cache.prefetcher 12979392 +system.physmem.bytes_read::total 61317248 +system.physmem.bytes_inst_read::cpu.inst 272000 +system.physmem.bytes_inst_read::total 272000 +system.physmem.bytes_written::writebacks 4246400 +system.physmem.bytes_written::total 4246400 +system.physmem.num_reads::cpu.inst 4250 +system.physmem.num_reads::cpu.data 751029 +system.physmem.num_reads::cpu.l2cache.prefetcher 202803 +system.physmem.num_reads::total 958082 +system.physmem.num_writes::writebacks 66350 +system.physmem.num_writes::total 66350 +system.physmem.bw_read::cpu.inst 802196 +system.physmem.bw_read::cpu.data 141758184 +system.physmem.bw_read::cpu.l2cache.prefetcher 38279461 +system.physmem.bw_read::total 180839840 +system.physmem.bw_inst_read::cpu.inst 802196 +system.physmem.bw_inst_read::total 802196 +system.physmem.bw_write::writebacks 12523692 +system.physmem.bw_write::total 12523692 +system.physmem.bw_total::writebacks 12523692 +system.physmem.bw_total::cpu.inst 802196 +system.physmem.bw_total::cpu.data 141758184 +system.physmem.bw_total::cpu.l2cache.prefetcher 38279461 +system.physmem.bw_total::total 193363532 +system.physmem.readReqs 958083 +system.physmem.writeReqs 66350 +system.physmem.readBursts 958083 +system.physmem.writeBursts 66350 +system.physmem.bytesReadDRAM 61296960 +system.physmem.bytesReadWrQ 20352 +system.physmem.bytesWritten 4240000 +system.physmem.bytesReadSys 61317312 +system.physmem.bytesWrittenSys 4246400 +system.physmem.servicedByWrQ 318 +system.physmem.mergedWrBursts 71 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 19910 +system.physmem.perBankRdBursts::1 19573 +system.physmem.perBankRdBursts::2 657828 +system.physmem.perBankRdBursts::3 21032 +system.physmem.perBankRdBursts::4 19718 +system.physmem.perBankRdBursts::5 21045 +system.physmem.perBankRdBursts::6 19700 +system.physmem.perBankRdBursts::7 20038 +system.physmem.perBankRdBursts::8 19491 +system.physmem.perBankRdBursts::9 20101 +system.physmem.perBankRdBursts::10 19540 +system.physmem.perBankRdBursts::11 19692 +system.physmem.perBankRdBursts::12 19618 +system.physmem.perBankRdBursts::13 21105 +system.physmem.perBankRdBursts::14 19493 +system.physmem.perBankRdBursts::15 19881 +system.physmem.perBankWrBursts::0 4272 +system.physmem.perBankWrBursts::1 4107 +system.physmem.perBankWrBursts::2 4147 +system.physmem.perBankWrBursts::3 4153 +system.physmem.perBankWrBursts::4 4251 +system.physmem.perBankWrBursts::5 4229 +system.physmem.perBankWrBursts::6 4174 +system.physmem.perBankWrBursts::7 4096 +system.physmem.perBankWrBursts::8 4096 +system.physmem.perBankWrBursts::9 4095 +system.physmem.perBankWrBursts::10 4095 +system.physmem.perBankWrBursts::11 4097 +system.physmem.perBankWrBursts::12 4098 +system.physmem.perBankWrBursts::13 4094 +system.physmem.perBankWrBursts::14 4095 +system.physmem.perBankWrBursts::15 4151 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 339069344500 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 958083 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 66350 +system.physmem.rdQLenPdf::0 765133 +system.physmem.rdQLenPdf::1 120601 +system.physmem.rdQLenPdf::2 15570 +system.physmem.rdQLenPdf::3 6690 +system.physmem.rdQLenPdf::4 6457 +system.physmem.rdQLenPdf::5 7738 +system.physmem.rdQLenPdf::6 9158 +system.physmem.rdQLenPdf::7 10207 +system.physmem.rdQLenPdf::8 6741 +system.physmem.rdQLenPdf::9 3672 +system.physmem.rdQLenPdf::10 2435 +system.physmem.rdQLenPdf::11 1581 +system.physmem.rdQLenPdf::12 1116 +system.physmem.rdQLenPdf::13 666 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 1 +system.physmem.wrQLenPdf::1 1 +system.physmem.wrQLenPdf::2 1 +system.physmem.wrQLenPdf::3 1 +system.physmem.wrQLenPdf::4 1 +system.physmem.wrQLenPdf::5 1 +system.physmem.wrQLenPdf::6 1 +system.physmem.wrQLenPdf::7 1 +system.physmem.wrQLenPdf::8 1 +system.physmem.wrQLenPdf::9 1 +system.physmem.wrQLenPdf::10 1 +system.physmem.wrQLenPdf::11 1 +system.physmem.wrQLenPdf::12 1 +system.physmem.wrQLenPdf::13 1 +system.physmem.wrQLenPdf::14 1 +system.physmem.wrQLenPdf::15 511 +system.physmem.wrQLenPdf::16 556 +system.physmem.wrQLenPdf::17 857 +system.physmem.wrQLenPdf::18 1405 +system.physmem.wrQLenPdf::19 2061 +system.physmem.wrQLenPdf::20 2611 +system.physmem.wrQLenPdf::21 3025 +system.physmem.wrQLenPdf::22 3538 +system.physmem.wrQLenPdf::23 4041 +system.physmem.wrQLenPdf::24 4482 +system.physmem.wrQLenPdf::25 4954 +system.physmem.wrQLenPdf::26 5339 +system.physmem.wrQLenPdf::27 5747 +system.physmem.wrQLenPdf::28 6156 +system.physmem.wrQLenPdf::29 6357 +system.physmem.wrQLenPdf::30 4787 +system.physmem.wrQLenPdf::31 4236 +system.physmem.wrQLenPdf::32 4138 +system.physmem.wrQLenPdf::33 191 +system.physmem.wrQLenPdf::34 168 +system.physmem.wrQLenPdf::35 135 +system.physmem.wrQLenPdf::36 120 +system.physmem.wrQLenPdf::37 116 +system.physmem.wrQLenPdf::38 89 +system.physmem.wrQLenPdf::39 84 +system.physmem.wrQLenPdf::40 75 +system.physmem.wrQLenPdf::41 73 +system.physmem.wrQLenPdf::42 60 +system.physmem.wrQLenPdf::43 58 +system.physmem.wrQLenPdf::44 51 +system.physmem.wrQLenPdf::45 45 +system.physmem.wrQLenPdf::46 44 +system.physmem.wrQLenPdf::47 32 +system.physmem.wrQLenPdf::48 26 +system.physmem.wrQLenPdf::49 29 +system.physmem.wrQLenPdf::50 22 +system.physmem.wrQLenPdf::51 15 +system.physmem.wrQLenPdf::52 12 +system.physmem.wrQLenPdf::53 10 +system.physmem.wrQLenPdf::54 6 +system.physmem.wrQLenPdf::55 1 +system.physmem.wrQLenPdf::56 1 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 196319 +system.physmem.bytesPerActivate::mean 333.816859 +system.physmem.bytesPerActivate::gmean 191.183939 +system.physmem.bytesPerActivate::stdev 355.380336 +system.physmem.bytesPerActivate::0-127 65406 33.32% 33.32% +system.physmem.bytesPerActivate::128-255 61086 31.12% 64.43% +system.physmem.bytesPerActivate::256-383 15476 7.88% 72.31% +system.physmem.bytesPerActivate::384-511 3179 1.62% 73.93% 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+system.membus.reqLayer0.utilization 0.5 +system.membus.respLayer1.occupancy 5035040414 +system.membus.respLayer1.utilization 1.5 ---------- End Simulation Statistics ---------- |