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authorNilay Vaish <nilay@cs.wisc.edu>2012-12-11 10:06:01 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2012-12-11 10:06:01 -0600
commit141ee3879459eea62d6176119fbc2c432a5fb124 (patch)
tree495c71e7c8b3e8b726d5111277ef5b99377b35a7 /tests/long
parentf3d0be210f889da927d921d21a6c27ba94fde746 (diff)
downloadgem5-141ee3879459eea62d6176119fbc2c432a5fb124.tar.xz
regressions: stats update due to stats from ruby prefetcher
Diffstat (limited to 'tests/long')
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini28
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats99
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt28
3 files changed, 131 insertions, 24 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
index ab02ce91f..0ce5d3fc8 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -629,15 +629,17 @@ sys=system
[system.l1_cntrl0]
type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory sequencer
+children=L1DcacheMemory L1IcacheMemory prefetcher sequencer
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
buffer_size=0
cntrl_id=0
+enable_prefetch=false
l1_request_latency=2
l1_response_latency=2
l2_select_num_bits=0
number_of_TBEs=256
+prefetcher=system.l1_cntrl0.prefetcher
recycle_latency=10
ruby_system=system.ruby
send_evictions=false
@@ -674,6 +676,16 @@ start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
+[system.l1_cntrl0.prefetcher]
+type=Prefetcher
+cross_page=false
+nonunit_filter=8
+num_startup_pfs=1
+num_streams=4
+pf_per_stream=1
+train_misses=4
+unit_filter=8
+
[system.l1_cntrl0.sequencer]
type=RubySequencer
access_phys_mem=true
@@ -694,15 +706,17 @@ slave=system.cpu0.icache_port system.cpu0.dcache_port system.cpu0.itb.walker.por
[system.l1_cntrl1]
type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory sequencer
+children=L1DcacheMemory L1IcacheMemory prefetcher sequencer
L1DcacheMemory=system.l1_cntrl1.L1DcacheMemory
L1IcacheMemory=system.l1_cntrl1.L1IcacheMemory
buffer_size=0
cntrl_id=1
+enable_prefetch=false
l1_request_latency=2
l1_response_latency=2
l2_select_num_bits=0
number_of_TBEs=256
+prefetcher=system.l1_cntrl1.prefetcher
recycle_latency=10
ruby_system=system.ruby
send_evictions=false
@@ -739,6 +753,16 @@ start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
+[system.l1_cntrl1.prefetcher]
+type=Prefetcher
+cross_page=false
+nonunit_filter=8
+num_startup_pfs=1
+num_streams=4
+pf_per_stream=1
+train_misses=4
+unit_filter=8
+
[system.l1_cntrl1.sequencer]
type=RubySequencer
access_phys_mem=true
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
index f731c9785..4cac199f9 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -1,24 +1,24 @@
-Real time: Oct/27/2012 15:45:09
+Real time: Dec/11/2012 06:57:21
Profiler Stats
--------------
-Elapsed_time_in_seconds: 671
-Elapsed_time_in_minutes: 11.1833
-Elapsed_time_in_hours: 0.186389
-Elapsed_time_in_days: 0.0077662
+Elapsed_time_in_seconds: 720
+Elapsed_time_in_minutes: 12
+Elapsed_time_in_hours: 0.2
+Elapsed_time_in_days: 0.00833333
-Virtual_time_in_seconds: 665.95
-Virtual_time_in_minutes: 11.0992
-Virtual_time_in_hours: 0.184986
-Virtual_time_in_days: 0.00770775
+Virtual_time_in_seconds: 718.24
+Virtual_time_in_minutes: 11.9707
+Virtual_time_in_hours: 0.199511
+Virtual_time_in_days: 0.00831296
Ruby_current_time: 10410012988
Ruby_start_time: 0
Ruby_cycles: 10410012988
-mbytes_resident: 259.211
-mbytes_total: 493.871
-resident_ratio: 0.524863
+mbytes_resident: 260.055
+mbytes_total: 495.168
+resident_ratio: 0.525201
ruby_cycles_executed: [ 10410012989 10410012989 ]
@@ -87,13 +87,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4899179 average: 0.0429682 |
Resource Usage
--------------
page_size: 4096
-user_time: 665
+user_time: 718
system_time: 0
-page_reclaims: 56440
-page_faults: 21
+page_reclaims: 57537
+page_faults: 25
swaps: 0
-block_inputs: 30000
-block_outputs: 536
+block_inputs: 16336
+block_outputs: 512
Network Stats
-------------
@@ -235,6 +235,9 @@ Data_all_Acks [854313 427607 ] 1281920
Ack [20626 22980 ] 43606
Ack_all [22417 23930 ] 46347
WB_Ack [1509156 186097 ] 1695253
+PF_Load [0 0 ] 0
+PF_Ifetch [0 0 ] 0
+PF_Store [0 0 ] 0
- Transitions -
NP Load [1283896 113817 ] 1397713
@@ -242,18 +245,26 @@ NP Ifetch [500075 286188 ] 786263
NP Store [296389 110024 ] 406413
NP Inv [6714 2646 ] 9360
NP L1_Replacement [0 0 ] 0
+NP PF_Load [0 0 ] 0
+NP PF_Ifetch [0 0 ] 0
+NP PF_Store [0 0 ] 0
I Load [16574 16247 ] 32821
I Ifetch [383 392 ] 775
I Store [7661 9474 ] 17135
I Inv [0 0 ] 0
I L1_Replacement [14969 11940 ] 26909
+I PF_Load [0 0 ] 0
+I PF_Ifetch [0 0 ] 0
+I PF_Store [0 0 ] 0
S Load [793915 479736 ] 1273651
S Ifetch [108316996 19344327 ] 127661323
S Store [20626 22981 ] 43607
S Inv [23501 22199 ] 45700
S L1_Replacement [555211 310968 ] 866179
+S PF_Load [0 0 ] 0
+S PF_Store [0 0 ] 0
E Load [3115881 532241 ] 3648122
E Ifetch [0 0 ] 0
@@ -263,6 +274,8 @@ E L1_Replacement [1105264 51360 ] 1156624
E Fwd_GETX [95 109 ] 204
E Fwd_GETS [1520 1047 ] 2567
E Fwd_GET_INSTR [1 0 ] 1
+E PF_Load [0 0 ] 0
+E PF_Store [0 0 ] 0
M Load [6446882 2553818 ] 9000700
M Ifetch [0 0 ] 0
@@ -272,6 +285,8 @@ M L1_Replacement [403892 134737 ] 538629
M Fwd_GETX [15889 15493 ] 31382
M Fwd_GETS [22982 22269 ] 45251
M Fwd_GET_INSTR [4 0 ] 4
+M PF_Load [0 0 ] 0
+M PF_Store [0 0 ] 0
IS Load [0 0 ] 0
IS Ifetch [0 0 ] 0
@@ -281,6 +296,8 @@ IS L1_Replacement [0 0 ] 0
IS Data_Exclusive [1225558 83079 ] 1308637
IS DataS_fromL1 [23316 24507 ] 47823
IS Data_all_Acks [552054 309058 ] 861112
+IS PF_Load [0 0 ] 0
+IS PF_Store [0 0 ] 0
IM Load [0 0 ] 0
IM Ifetch [0 0 ] 0
@@ -290,6 +307,8 @@ IM L1_Replacement [0 0 ] 0
IM Data [1791 950 ] 2741
IM Data_all_Acks [302259 118549 ] 420808
IM Ack [0 0 ] 0
+IM PF_Load [0 0 ] 0
+IM PF_Store [0 0 ] 0
SM Load [0 0 ] 0
SM Ifetch [0 0 ] 0
@@ -298,6 +317,8 @@ SM Inv [0 1 ] 1
SM L1_Replacement [0 0 ] 0
SM Ack [20626 22980 ] 43606
SM Ack_all [22417 23930 ] 46347
+SM PF_Load [0 0 ] 0
+SM PF_Store [0 0 ] 0
IS_I Load [0 0 ] 0
IS_I Ifetch [0 0 ] 0
@@ -307,6 +328,8 @@ IS_I L1_Replacement [0 0 ] 0
IS_I Data_Exclusive [0 0 ] 0
IS_I DataS_fromL1 [0 0 ] 0
IS_I Data_all_Acks [0 0 ] 0
+IS_I PF_Load [0 0 ] 0
+IS_I PF_Store [0 0 ] 0
M_I Load [0 0 ] 0
M_I Ifetch [5 1 ] 6
@@ -317,6 +340,8 @@ M_I Fwd_GETX [0 0 ] 0
M_I Fwd_GETS [0 0 ] 0
M_I Fwd_GET_INSTR [0 0 ] 0
M_I WB_Ack [1509156 186097 ] 1695253
+M_I PF_Load [0 0 ] 0
+M_I PF_Store [0 0 ] 0
SINK_WB_ACK Load [0 0 ] 0
SINK_WB_ACK Ifetch [0 0 ] 0
@@ -324,6 +349,46 @@ SINK_WB_ACK Store [0 0 ] 0
SINK_WB_ACK Inv [0 0 ] 0
SINK_WB_ACK L1_Replacement [0 0 ] 0
SINK_WB_ACK WB_Ack [0 0 ] 0
+SINK_WB_ACK PF_Load [0 0 ] 0
+SINK_WB_ACK PF_Store [0 0 ] 0
+
+PF_IS Load [0 0 ] 0
+PF_IS Ifetch [0 0 ] 0
+PF_IS Store [0 0 ] 0
+PF_IS Inv [0 0 ] 0
+PF_IS L1_Replacement [0 0 ] 0
+PF_IS Data_Exclusive [0 0 ] 0
+PF_IS DataS_fromL1 [0 0 ] 0
+PF_IS Data_all_Acks [0 0 ] 0
+PF_IS PF_Load [0 0 ] 0
+PF_IS PF_Store [0 0 ] 0
+
+PF_IM Load [0 0 ] 0
+PF_IM Ifetch [0 0 ] 0
+PF_IM Store [0 0 ] 0
+PF_IM Inv [0 0 ] 0
+PF_IM L1_Replacement [0 0 ] 0
+PF_IM Data [0 0 ] 0
+PF_IM Data_all_Acks [0 0 ] 0
+PF_IM Ack [0 0 ] 0
+PF_IM PF_Load [0 0 ] 0
+PF_IM PF_Store [0 0 ] 0
+
+PF_SM Load [0 0 ] 0
+PF_SM Ifetch [0 0 ] 0
+PF_SM Store [0 0 ] 0
+PF_SM Inv [0 0 ] 0
+PF_SM L1_Replacement [0 0 ] 0
+PF_SM Ack [0 0 ] 0
+PF_SM Ack_all [0 0 ] 0
+
+PF_IS_I Load [0 0 ] 0
+PF_IS_I Store [0 0 ] 0
+PF_IS_I Inv [0 0 ] 0
+PF_IS_I L1_Replacement [0 0 ] 0
+PF_IS_I Data_Exclusive [0 0 ] 0
+PF_IS_I DataS_fromL1 [0 0 ] 0
+PF_IS_I Data_all_Acks [0 0 ] 0
Cache Stats: system.l1_cntrl1.L1IcacheMemory
system.l1_cntrl1.L1IcacheMemory_total_misses: 286580
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
index c24f73d04..42a2727f0 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 5.205006 # Nu
sim_ticks 5205006494000 # Number of ticks simulated
final_tick 5205006494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 176611 # Simulator instruction rate (inst/s)
-host_op_rate 338881 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 8497542071 # Simulator tick rate (ticks/s)
-host_mem_usage 459536 # Number of bytes of host memory used
-host_seconds 612.53 # Real time elapsed on the host
+host_inst_rate 150447 # Simulator instruction rate (inst/s)
+host_op_rate 288677 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 7238673236 # Simulator tick rate (ticks/s)
+host_mem_usage 507056 # Number of bytes of host memory used
+host_seconds 719.06 # Real time elapsed on the host
sim_insts 108179755 # Number of instructions simulated
sim_ops 207574747 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 35216 # Number of bytes read from this memory
@@ -242,6 +242,15 @@ system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0
system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
+system.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
+system.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
+system.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
+system.l1_cntrl0.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
+system.l1_cntrl0.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
+system.l1_cntrl0.prefetcher.hits 0 # number of prefetched blocks accessed
+system.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
+system.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
+system.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
system.l1_cntrl1.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl1.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl1.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
@@ -254,6 +263,15 @@ system.l1_cntrl1.L1IcacheMemory.num_tag_array_reads 0
system.l1_cntrl1.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes
system.l1_cntrl1.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.l1_cntrl1.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
+system.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed
+system.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
+system.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made
+system.l1_cntrl1.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
+system.l1_cntrl1.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
+system.l1_cntrl1.prefetcher.hits 0 # number of prefetched blocks accessed
+system.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
+system.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages
+system.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads
system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes
system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads